hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define HARD_DEBUG_PPC_IO
  27 //#define DEBUG_PPC_IO
  28
  29 /* SMP is not enabled, for now */
  30 #define MAX_CPUS 1
  31
  32 #define BIOS_FILENAME "ppc_rom.bin"
  33 #define KERNEL_LOAD_ADDR 0x01000000
  34 #define INITRD_LOAD_ADDR 0x01800000
  35
  36 extern int loglevel;
  37 extern FILE *logfile;
  38
  39 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  40 #define DEBUG_PPC_IO
  41 #endif
  42
  43 #if defined (HARD_DEBUG_PPC_IO)
  44 #define PPC_IO_DPRINTF(fmt, args...)                     \
  45 do {                                                     \
  46     if (loglevel & CPU_LOG_IOPORT) {                     \
  47         fprintf(logfile, "%s: " fmt, __func__ , ##args); \
  48     } else {                                             \
  49         printf("%s : " fmt, __func__ , ##args);          \
  50     }                                                    \
  51 } while (0)
  52 #elif defined (DEBUG_PPC_IO)
  53 #define PPC_IO_DPRINTF(fmt, args...)                     \
  54 do {                                                     \
  55     if (loglevel & CPU_LOG_IOPORT) {                     \
  56         fprintf(logfile, "%s: " fmt, __func__ , ##args); \
  57     }                                                    \
  58 } while (0)
  59 #else
  60 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
  61 #endif
  62
  63 /* Constants for devices init */
  64 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  65 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  66 static const int ide_irq[2] = { 13, 13 };
  67
  68 #define NE2000_NB_MAX 6
  69
  70 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  71 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  72
  73 //static PITState *pit;
  74
  75 /* ISA IO ports bridge */
  76 #define PPC_IO_BASE 0x80000000
  77
  78 /* Speaker port 0x61 */
  79 int speaker_data_on;
  80 int dummy_refresh_clock;
  81
  82 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  83 {
  84 #if 0
  85     speaker_data_on = (val >> 1) & 1;
  86     pit_set_gate(pit, 2, val & 1);
  87 #endif
  88 }
  89
  90 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
  91 {
  92 #if 0
  93     int out;
  94     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
  95     dummy_refresh_clock ^= 1;
  96     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
  97         (dummy_refresh_clock << 4);
  98 #endif
  99     return 0;
 100 }
 101
 102 /* PCI intack register */
 103 /* Read-only register (?) */
 104 static void _PPC_intack_write (void *opaque,
 105                                target_phys_addr_t addr, uint32_t value)
 106 {
 107     //    printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
 108 }
 109
 110 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
 111 {
 112     uint32_t retval = 0;
 113
 114     if (addr == 0xBFFFFFF0)
 115         retval = pic_intack_read(isa_pic);
 116     //   printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
 117
 118     return retval;
 119 }
 120
 121 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 122 {
 123     return _PPC_intack_read(addr);
 124 }
 125
 126 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 127 {
 128 #ifdef TARGET_WORDS_BIGENDIAN
 129     return bswap16(_PPC_intack_read(addr));
 130 #else
 131     return _PPC_intack_read(addr);
 132 #endif
 133 }
 134
 135 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 136 {
 137 #ifdef TARGET_WORDS_BIGENDIAN
 138     return bswap32(_PPC_intack_read(addr));
 139 #else
 140     return _PPC_intack_read(addr);
 141 #endif
 142 }
 143
 144 static CPUWriteMemoryFunc *PPC_intack_write[] = {
 145     &_PPC_intack_write,
 146     &_PPC_intack_write,
 147     &_PPC_intack_write,
 148 };
 149
 150 static CPUReadMemoryFunc *PPC_intack_read[] = {
 151     &PPC_intack_readb,
 152     &PPC_intack_readw,
 153     &PPC_intack_readl,
 154 };
 155
 156 /* PowerPC control and status registers */
 157 #if 0 // Not used
 158 static struct {
 159     /* IDs */
 160     uint32_t veni_devi;
 161     uint32_t revi;
 162     /* Control and status */
 163     uint32_t gcsr;
 164     uint32_t xcfr;
 165     uint32_t ct32;
 166     uint32_t mcsr;
 167     /* General purpose registers */
 168     uint32_t gprg[6];
 169     /* Exceptions */
 170     uint32_t feen;
 171     uint32_t fest;
 172     uint32_t fema;
 173     uint32_t fecl;
 174     uint32_t eeen;
 175     uint32_t eest;
 176     uint32_t eecl;
 177     uint32_t eeint;
 178     uint32_t eemck0;
 179     uint32_t eemck1;
 180     /* Error diagnostic */
 181 } XCSR;
 182
 183 static void PPC_XCSR_writeb (void *opaque,
 184                              target_phys_addr_t addr, uint32_t value)
 185 {
 186     printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
 187 }
 188
 189 static void PPC_XCSR_writew (void *opaque,
 190                              target_phys_addr_t addr, uint32_t value)
 191 {
 192 #ifdef TARGET_WORDS_BIGENDIAN
 193     value = bswap16(value);
 194 #endif
 195     printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
 196 }
 197
 198 static void PPC_XCSR_writel (void *opaque,
 199                              target_phys_addr_t addr, uint32_t value)
 200 {
 201 #ifdef TARGET_WORDS_BIGENDIAN
 202     value = bswap32(value);
 203 #endif
 204     printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
 205 }
 206
 207 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 208 {
 209     uint32_t retval = 0;
 210
 211     printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
 212
 213     return retval;
 214 }
 215
 216 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 217 {
 218     uint32_t retval = 0;
 219
 220     printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
 221 #ifdef TARGET_WORDS_BIGENDIAN
 222     retval = bswap16(retval);
 223 #endif
 224
 225     return retval;
 226 }
 227
 228 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 229 {
 230     uint32_t retval = 0;
 231
 232     printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
 233 #ifdef TARGET_WORDS_BIGENDIAN
 234     retval = bswap32(retval);
 235 #endif
 236
 237     return retval;
 238 }
 239
 240 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
 241     &PPC_XCSR_writeb,
 242     &PPC_XCSR_writew,
 243     &PPC_XCSR_writel,
 244 };
 245
 246 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
 247     &PPC_XCSR_readb,
 248     &PPC_XCSR_readw,
 249     &PPC_XCSR_readl,
 250 };
 251 #endif
 252
 253 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 254 typedef struct sysctrl_t {
 255     m48t59_t *nvram;
 256     uint8_t state;
 257     uint8_t syscontrol;
 258     uint8_t fake_io[2];
 259     int contiguous_map;
 260     int endian;
 261 } sysctrl_t;
 262
 263 enum {
 264     STATE_HARDFILE = 0x01,
 265 };
 266
 267 static sysctrl_t *sysctrl;
 268
 269 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 270 {
 271     sysctrl_t *sysctrl = opaque;
 272
 273     PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
 274     sysctrl->fake_io[addr - 0x0398] = val;
 275 }
 276
 277 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 278 {
 279     sysctrl_t *sysctrl = opaque;
 280
 281     PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
 282                    sysctrl->fake_io[addr - 0x0398]);
 283     return sysctrl->fake_io[addr - 0x0398];
 284 }
 285
 286 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 287 {
 288     sysctrl_t *sysctrl = opaque;
 289
 290     PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
 291     switch (addr) {
 292     case 0x0092:
 293         /* Special port 92 */
 294         /* Check soft reset asked */
 295         if (val & 0x01) {
 296             //            cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET);
 297         }
 298         /* Check LE mode */
 299         if (val & 0x02) {
 300             sysctrl->endian = 1;
 301         } else {
 302             sysctrl->endian = 0;
 303         }
 304         break;
 305     case 0x0800:
 306         /* Motorola CPU configuration register : read-only */
 307         break;
 308     case 0x0802:
 309         /* Motorola base module feature register : read-only */
 310         break;
 311     case 0x0803:
 312         /* Motorola base module status register : read-only */
 313         break;
 314     case 0x0808:
 315         /* Hardfile light register */
 316         if (val & 1)
 317             sysctrl->state |= STATE_HARDFILE;
 318         else
 319             sysctrl->state &= ~STATE_HARDFILE;
 320         break;
 321     case 0x0810:
 322         /* Password protect 1 register */
 323         if (sysctrl->nvram != NULL)
 324             m48t59_toggle_lock(sysctrl->nvram, 1);
 325         break;
 326     case 0x0812:
 327         /* Password protect 2 register */
 328         if (sysctrl->nvram != NULL)
 329             m48t59_toggle_lock(sysctrl->nvram, 2);
 330         break;
 331     case 0x0814:
 332         /* L2 invalidate register */
 333         //        tlb_flush(first_cpu, 1);
 334         break;
 335     case 0x081C:
 336         /* system control register */
 337         sysctrl->syscontrol = val & 0x0F;
 338         break;
 339     case 0x0850:
 340         /* I/O map type register */
 341         sysctrl->contiguous_map = val & 0x01;
 342         break;
 343     default:
 344         printf("ERROR: unaffected IO port write: %04lx => %02x\n",
 345                (long)addr, val);
 346         break;
 347     }
 348 }
 349
 350 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 351 {
 352     sysctrl_t *sysctrl = opaque;
 353     uint32_t retval = 0xFF;
 354
 355     switch (addr) {
 356     case 0x0092:
 357         /* Special port 92 */
 358         retval = 0x00;
 359         break;
 360     case 0x0800:
 361         /* Motorola CPU configuration register */
 362         retval = 0xEF; /* MPC750 */
 363         break;
 364     case 0x0802:
 365         /* Motorola Base module feature register */
 366         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 367         break;
 368     case 0x0803:
 369         /* Motorola base module status register */
 370         retval = 0xE0; /* Standard MPC750 */
 371         break;
 372     case 0x080C:
 373         /* Equipment present register:
 374          *  no L2 cache
 375          *  no upgrade processor
 376          *  no cards in PCI slots
 377          *  SCSI fuse is bad
 378          */
 379         retval = 0x3C;
 380         break;
 381     case 0x0810:
 382         /* Motorola base module extended feature register */
 383         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 384         break;
 385     case 0x0814:
 386         /* L2 invalidate: don't care */
 387         break;
 388     case 0x0818:
 389         /* Keylock */
 390         retval = 0x00;
 391         break;
 392     case 0x081C:
 393         /* system control register
 394          * 7 - 6 / 1 - 0: L2 cache enable
 395          */
 396         retval = sysctrl->syscontrol;
 397         break;
 398     case 0x0823:
 399         /* */
 400         retval = 0x03; /* no L2 cache */
 401         break;
 402     case 0x0850:
 403         /* I/O map type register */
 404         retval = sysctrl->contiguous_map;
 405         break;
 406     default:
 407         printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
 408         break;
 409     }
 410     PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
 411
 412     return retval;
 413 }
 414
 415 static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
 416                                                          target_phys_addr_t
 417                                                          addr)
 418 {
 419     if (sysctrl->contiguous_map == 0) {
 420         /* 64 KB contiguous space for IOs */
 421         addr &= 0xFFFF;
 422     } else {
 423         /* 8 MB non-contiguous space for IOs */
 424         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 425     }
 426
 427     return addr;
 428 }
 429
 430 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 431                                 uint32_t value)
 432 {
 433     sysctrl_t *sysctrl = opaque;
 434
 435     addr = prep_IO_address(sysctrl, addr);
 436     cpu_outb(NULL, addr, value);
 437 }
 438
 439 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 440 {
 441     sysctrl_t *sysctrl = opaque;
 442     uint32_t ret;
 443
 444     addr = prep_IO_address(sysctrl, addr);
 445     ret = cpu_inb(NULL, addr);
 446
 447     return ret;
 448 }
 449
 450 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 451                                 uint32_t value)
 452 {
 453     sysctrl_t *sysctrl = opaque;
 454
 455     addr = prep_IO_address(sysctrl, addr);
 456 #ifdef TARGET_WORDS_BIGENDIAN
 457     value = bswap16(value);
 458 #endif
 459     PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
 460     cpu_outw(NULL, addr, value);
 461 }
 462
 463 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 464 {
 465     sysctrl_t *sysctrl = opaque;
 466     uint32_t ret;
 467
 468     addr = prep_IO_address(sysctrl, addr);
 469     ret = cpu_inw(NULL, addr);
 470 #ifdef TARGET_WORDS_BIGENDIAN
 471     ret = bswap16(ret);
 472 #endif
 473     PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
 474
 475     return ret;
 476 }
 477
 478 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 479                                 uint32_t value)
 480 {
 481     sysctrl_t *sysctrl = opaque;
 482
 483     addr = prep_IO_address(sysctrl, addr);
 484 #ifdef TARGET_WORDS_BIGENDIAN
 485     value = bswap32(value);
 486 #endif
 487     PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
 488     cpu_outl(NULL, addr, value);
 489 }
 490
 491 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 492 {
 493     sysctrl_t *sysctrl = opaque;
 494     uint32_t ret;
 495
 496     addr = prep_IO_address(sysctrl, addr);
 497     ret = cpu_inl(NULL, addr);
 498 #ifdef TARGET_WORDS_BIGENDIAN
 499     ret = bswap32(ret);
 500 #endif
 501     PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
 502
 503     return ret;
 504 }
 505
 506 CPUWriteMemoryFunc *PPC_prep_io_write[] = {
 507     &PPC_prep_io_writeb,
 508     &PPC_prep_io_writew,
 509     &PPC_prep_io_writel,
 510 };
 511
 512 CPUReadMemoryFunc *PPC_prep_io_read[] = {
 513     &PPC_prep_io_readb,
 514     &PPC_prep_io_readw,
 515     &PPC_prep_io_readl,
 516 };
 517
 518 #define NVRAM_SIZE        0x2000
 519
 520 /* PowerPC PREP hardware initialisation */
 521 static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
 522                            DisplayState *ds, const char **fd_filename,
 523                            int snapshot, const char *kernel_filename,
 524                            const char *kernel_cmdline,
 525                            const char *initrd_filename,
 526                            const char *cpu_model)
 527 {
 528     CPUState *env, *envs[MAX_CPUS];
 529     char buf[1024];
 530     m48t59_t *nvram;
 531     int PPC_io_memory;
 532     int linux_boot, i, nb_nics1, bios_size;
 533     unsigned long bios_offset;
 534     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 535     ppc_def_t *def;
 536     PCIBus *pci_bus;
 537     qemu_irq *i8259;
 538
 539     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 540     if (sysctrl == NULL)
 541         return;
 542
 543     linux_boot = (kernel_filename != NULL);
 544
 545     /* init CPUs */
 546     env = cpu_init();
 547     if (cpu_model == NULL)
 548         cpu_model = "default";
 549     ppc_find_by_name(cpu_model, &def);
 550     if (def == NULL) {
 551         cpu_abort(env, "Unable to find PowerPC CPU definition\n");
 552     }
 553     for (i = 0; i < smp_cpus; i++) {
 554         cpu_ppc_register(env, def);
 555         cpu_ppc_reset(env);
 556         /* Set time-base frequency to 100 Mhz */
 557         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 558         qemu_register_reset(&cpu_ppc_reset, env);
 559         register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 560         envs[i] = env;
 561     }
 562
 563     /* allocate RAM */
 564     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 565
 566     /* allocate and load BIOS */
 567     bios_offset = ram_size + vga_ram_size;
 568     if (bios_name == NULL)
 569         bios_name = BIOS_FILENAME;
 570     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 571     bios_size = load_image(buf, phys_ram_base + bios_offset);
 572     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 573         cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
 574         exit(1);
 575     }
 576     bios_size = (bios_size + 0xfff) & ~0xfff;
 577     cpu_register_physical_memory((uint32_t)(-bios_size),
 578                                  bios_size, bios_offset | IO_MEM_ROM);
 579
 580     if (linux_boot) {
 581         kernel_base = KERNEL_LOAD_ADDR;
 582         /* now we can load the kernel */
 583         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 584         if (kernel_size < 0) {
 585             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 586                       kernel_filename);
 587             exit(1);
 588         }
 589         /* load initrd */
 590         if (initrd_filename) {
 591             initrd_base = INITRD_LOAD_ADDR;
 592             initrd_size = load_image(initrd_filename,
 593                                      phys_ram_base + initrd_base);
 594             if (initrd_size < 0) {
 595                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 596                           initrd_filename);
 597                 exit(1);
 598             }
 599         } else {
 600             initrd_base = 0;
 601             initrd_size = 0;
 602         }
 603         boot_device = 'm';
 604     } else {
 605         kernel_base = 0;
 606         kernel_size = 0;
 607         initrd_base = 0;
 608         initrd_size = 0;
 609     }
 610
 611     isa_mem_base = 0xc0000000;
 612     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 613         cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
 614         exit(1);
 615     }
 616     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 617     pci_bus = pci_prep_init(i8259);
 618     //    pci_bus = i440fx_init();
 619     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 620     PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
 621                                            PPC_prep_io_write, sysctrl);
 622     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 623
 624     /* init basic PC hardware */
 625     pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
 626                  vga_ram_size, 0, 0);
 627     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 628     //    pit = pit_init(0x40, i8259[0]);
 629     rtc_init(0x70, i8259[8]);
 630
 631     serial_init(0x3f8, i8259[4], serial_hds[0]);
 632     nb_nics1 = nb_nics;
 633     if (nb_nics1 > NE2000_NB_MAX)
 634         nb_nics1 = NE2000_NB_MAX;
 635     for(i = 0; i < nb_nics1; i++) {
 636         if (nd_table[0].model == NULL
 637             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 638             isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
 639         } else if (strcmp(nd_table[0].model, "?") == 0) {
 640             fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
 641             exit (1);
 642         } else {
 643             /* Why ? */
 644             cpu_abort(env, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 645             exit (1);
 646         }
 647     }
 648
 649     for(i = 0; i < 2; i++) {
 650         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 651                      bs_table[2 * i], bs_table[2 * i + 1]);
 652     }
 653     i8042_init(i8259[1], i8259[12], 0x60);
 654     DMA_init(1);
 655     //    AUD_init();
 656     //    SB16_init();
 657
 658     fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
 659
 660     /* Register speaker port */
 661     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 662     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 663     /* Register fake IO ports for PREP */
 664     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 665     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 666     /* System control ports */
 667     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 668     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 669     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 670     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 671     /* PCI intack location */
 672     PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
 673                                            PPC_intack_write, NULL);
 674     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 675     /* PowerPC control and status register group */
 676 #if 0
 677     PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
 678                                            NULL);
 679     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 680 #endif
 681
 682     if (usb_enabled) {
 683         usb_ohci_init_pci(pci_bus, 3, -1);
 684     }
 685
 686     nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 687     if (nvram == NULL)
 688         return;
 689     sysctrl->nvram = nvram;
 690
 691     /* Initialise NVRAM */
 692     PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
 693                          kernel_base, kernel_size,
 694                          kernel_cmdline,
 695                          initrd_base, initrd_size,
 696                          /* XXX: need an option to load a NVRAM image */
 697                          0,
 698                          graphic_width, graphic_height, graphic_depth);
 699
 700     /* Special port to get debug messages from Open-Firmware */
 701     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 702 }
 703
 704 QEMUMachine prep_machine = {
 705     "prep",
 706     "PowerPC PREP platform",
 707     ppc_prep_init,
 708 };