hw/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GNU LGPL
   8  */
   9
  10 #include "vl.h"
  11
  12 #define PL110_CR_EN   0x001
  13 #define PL110_CR_BGR  0x100
  14 #define PL110_CR_BEBO 0x200
  15 #define PL110_CR_BEPO 0x400
  16 #define PL110_CR_PWR  0x800
  17
  18 enum pl110_bppmode
  19 {
  20     BPP_1,
  21     BPP_2,
  22     BPP_4,
  23     BPP_8,
  24     BPP_16,
  25     BPP_32
  26 };
  27
  28 typedef struct {
  29     uint32_t base;
  30     DisplayState *ds;
  31     /* The Versatile/PB uses a slightly modified PL110 controller.  */
  32     int versatile;
  33     uint32_t timing[4];
  34     uint32_t cr;
  35     uint32_t upbase;
  36     uint32_t lpbase;
  37     uint32_t int_status;
  38     uint32_t int_mask;
  39     int cols;
  40     int rows;
  41     enum pl110_bppmode bpp;
  42     int invalidate;
  43     uint32_t pallette[256];
  44     uint32_t raw_pallette[128];
  45     qemu_irq irq;
  46 } pl110_state;
  47
  48 static const unsigned char pl110_id[] =
  49 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  50
  51 /* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
  52    has a different ID.  However Linux only looks for the normal ID.  */
  53 #if 0
  54 static const unsigned char pl110_versatile_id[] =
  55 { 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  56 #else
  57 #define pl110_versatile_id pl110_id
  58 #endif
  59
  60 static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
  61 {
  62     return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
  63 }
  64
  65 static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
  66 {
  67     return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
  68 }
  69
  70 static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
  71 {
  72     return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
  73 }
  74
  75 static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
  76 {
  77     return (r << 16) | (g << 8) | b;
  78 }
  79
  80 static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
  81 {
  82     return (r << 16) | (g << 8) | b;
  83 }
  84
  85 typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int);
  86
  87 #define BITS 8
  88 #include "pl110_template.h"
  89 #define BITS 15
  90 #include "pl110_template.h"
  91 #define BITS 16
  92 #include "pl110_template.h"
  93 #define BITS 24
  94 #include "pl110_template.h"
  95 #define BITS 32
  96 #include "pl110_template.h"
  97
  98 static int pl110_enabled(pl110_state *s)
  99 {
 100   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 101 }
 102
 103 static void pl110_update_display(void *opaque)
 104 {
 105     pl110_state *s = (pl110_state *)opaque;
 106     drawfn* fntable;
 107     drawfn fn;
 108     uint32_t *pallette;
 109     uint32_t addr;
 110     uint32_t base;
 111     int dest_width;
 112     int src_width;
 113     uint8_t *dest;
 114     uint8_t *src;
 115     int first, last = 0;
 116     int dirty, new_dirty;
 117     int i;
 118     int bpp_offset;
 119
 120     if (!pl110_enabled(s))
 121         return;
 122
 123     switch (s->ds->depth) {
 124     case 0:
 125         return;
 126     case 8:
 127         fntable = pl110_draw_fn_8;
 128         dest_width = 1;
 129         break;
 130     case 15:
 131         fntable = pl110_draw_fn_15;
 132         dest_width = 2;
 133         break;
 134     case 16:
 135         fntable = pl110_draw_fn_16;
 136         dest_width = 2;
 137         break;
 138     case 24:
 139         fntable = pl110_draw_fn_24;
 140         dest_width = 3;
 141         break;
 142     case 32:
 143         fntable = pl110_draw_fn_32;
 144         dest_width = 4;
 145         break;
 146     default:
 147         fprintf(stderr, "pl110: Bad color depth\n");
 148         exit(1);
 149     }
 150     if (s->cr & PL110_CR_BGR)
 151         bpp_offset = 0;
 152     else
 153         bpp_offset = 18;
 154
 155     if (s->cr & PL110_CR_BEBO)
 156         fn = fntable[s->bpp + 6 + bpp_offset];
 157     else if (s->cr & PL110_CR_BEPO)
 158         fn = fntable[s->bpp + 12 + bpp_offset];
 159     else
 160         fn = fntable[s->bpp + bpp_offset];
 161
 162     src_width = s->cols;
 163     switch (s->bpp) {
 164     case BPP_1:
 165         src_width >>= 3;
 166         break;
 167     case BPP_2:
 168         src_width >>= 2;
 169         break;
 170     case BPP_4:
 171         src_width >>= 1;
 172         break;
 173     case BPP_8:
 174         break;
 175     case BPP_16:
 176         src_width <<= 1;
 177         break;
 178     case BPP_32:
 179         src_width <<= 2;
 180         break;
 181     }
 182     dest_width *= s->cols;
 183     pallette = s->pallette;
 184     base = s->upbase;
 185     /* HACK: Arm aliases physical memory at 0x80000000.  */
 186     if (base > 0x80000000)
 187         base -= 0x80000000;
 188     src = phys_ram_base + base;
 189     dest = s->ds->data;
 190     first = -1;
 191     addr = base;
 192
 193     dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
 194     new_dirty = dirty;
 195     for (i = 0; i < s->rows; i++) {
 196         if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
 197             uint32_t tmp;
 198             new_dirty = 0;
 199             for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
 200                 new_dirty |= cpu_physical_memory_get_dirty(addr + tmp,
 201                                                            VGA_DIRTY_FLAG);
 202             }
 203         }
 204
 205         if (dirty || new_dirty || s->invalidate) {
 206             fn(pallette, dest, src, s->cols);
 207             if (first == -1)
 208                 first = i;
 209             last = i;
 210         }
 211         dirty = new_dirty;
 212         addr += src_width;
 213         dest += dest_width;
 214         src += src_width;
 215     }
 216     if (first < 0)
 217       return;
 218
 219     s->invalidate = 0;
 220     cpu_physical_memory_reset_dirty(base + first * src_width,
 221                                     base + (last + 1) * src_width,
 222                                     VGA_DIRTY_FLAG);
 223     dpy_update(s->ds, 0, first, s->cols, last - first + 1);
 224 }
 225
 226 static void pl110_invalidate_display(void * opaque)
 227 {
 228     pl110_state *s = (pl110_state *)opaque;
 229     s->invalidate = 1;
 230 }
 231
 232 static void pl110_update_pallette(pl110_state *s, int n)
 233 {
 234     int i;
 235     uint32_t raw;
 236     unsigned int r, g, b;
 237
 238     raw = s->raw_pallette[n];
 239     n <<= 1;
 240     for (i = 0; i < 2; i++) {
 241         r = (raw & 0x1f) << 3;
 242         raw >>= 5;
 243         g = (raw & 0x1f) << 3;
 244         raw >>= 5;
 245         b = (raw & 0x1f) << 3;
 246         /* The I bit is ignored.  */
 247         raw >>= 6;
 248         switch (s->ds->depth) {
 249         case 8:
 250             s->pallette[n] = rgb_to_pixel8(r, g, b);
 251             break;
 252         case 15:
 253             s->pallette[n] = rgb_to_pixel15(r, g, b);
 254             break;
 255         case 16:
 256             s->pallette[n] = rgb_to_pixel16(r, g, b);
 257             break;
 258         case 24:
 259         case 32:
 260             s->pallette[n] = rgb_to_pixel32(r, g, b);
 261             break;
 262         }
 263         n++;
 264     }
 265 }
 266
 267 static void pl110_resize(pl110_state *s, int width, int height)
 268 {
 269     if (width != s->cols || height != s->rows) {
 270         if (pl110_enabled(s)) {
 271             dpy_resize(s->ds, width, height);
 272         }
 273     }
 274     s->cols = width;
 275     s->rows = height;
 276 }
 277
 278 /* Update interrupts.  */
 279 static void pl110_update(pl110_state *s)
 280 {
 281   /* TODO: Implement interrupts.  */
 282 }
 283
 284 static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
 285 {
 286     pl110_state *s = (pl110_state *)opaque;
 287
 288     offset -= s->base;
 289     if (offset >= 0xfe0 && offset < 0x1000) {
 290         if (s->versatile)
 291             return pl110_versatile_id[(offset - 0xfe0) >> 2];
 292         else
 293             return pl110_id[(offset - 0xfe0) >> 2];
 294     }
 295     if (offset >= 0x200 && offset < 0x400) {
 296         return s->raw_pallette[(offset - 0x200) >> 2];
 297     }
 298     switch (offset >> 2) {
 299     case 0: /* LCDTiming0 */
 300         return s->timing[0];
 301     case 1: /* LCDTiming1 */
 302         return s->timing[1];
 303     case 2: /* LCDTiming2 */
 304         return s->timing[2];
 305     case 3: /* LCDTiming3 */
 306         return s->timing[3];
 307     case 4: /* LCDUPBASE */
 308         return s->upbase;
 309     case 5: /* LCDLPBASE */
 310         return s->lpbase;
 311     case 6: /* LCDIMSC */
 312         if (s->versatile)
 313           return s->cr;
 314         return s->int_mask;
 315     case 7: /* LCDControl */
 316         if (s->versatile)
 317           return s->int_mask;
 318         return s->cr;
 319     case 8: /* LCDRIS */
 320         return s->int_status;
 321     case 9: /* LCDMIS */
 322         return s->int_status & s->int_mask;
 323     case 11: /* LCDUPCURR */
 324         /* TODO: Implement vertical refresh.  */
 325         return s->upbase;
 326     case 12: /* LCDLPCURR */
 327         return s->lpbase;
 328     default:
 329         cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset);
 330         return 0;
 331     }
 332 }
 333
 334 static void pl110_write(void *opaque, target_phys_addr_t offset,
 335                         uint32_t val)
 336 {
 337     pl110_state *s = (pl110_state *)opaque;
 338     int n;
 339
 340     /* For simplicity invalidate the display whenever a control register
 341        is writen to.  */
 342     s->invalidate = 1;
 343     offset -= s->base;
 344     if (offset >= 0x200 && offset < 0x400) {
 345         /* Pallette.  */
 346         n = (offset - 0x200) >> 2;
 347         s->raw_pallette[(offset - 0x200) >> 2] = val;
 348         pl110_update_pallette(s, n);
 349         return;
 350     }
 351     switch (offset >> 2) {
 352     case 0: /* LCDTiming0 */
 353         s->timing[0] = val;
 354         n = ((val & 0xfc) + 4) * 4;
 355         pl110_resize(s, n, s->rows);
 356         break;
 357     case 1: /* LCDTiming1 */
 358         s->timing[1] = val;
 359         n = (val & 0x3ff) + 1;
 360         pl110_resize(s, s->cols, n);
 361         break;
 362     case 2: /* LCDTiming2 */
 363         s->timing[2] = val;
 364         break;
 365     case 3: /* LCDTiming3 */
 366         s->timing[3] = val;
 367         break;
 368     case 4: /* LCDUPBASE */
 369         s->upbase = val;
 370         break;
 371     case 5: /* LCDLPBASE */
 372         s->lpbase = val;
 373         break;
 374     case 6: /* LCDIMSC */
 375         if (s->versatile)
 376             goto control;
 377     imsc:
 378         s->int_mask = val;
 379         pl110_update(s);
 380         break;
 381     case 7: /* LCDControl */
 382         if (s->versatile)
 383             goto imsc;
 384     control:
 385         s->cr = val;
 386         s->bpp = (val >> 1) & 7;
 387         if (pl110_enabled(s)) {
 388             dpy_resize(s->ds, s->cols, s->rows);
 389         }
 390         break;
 391     case 10: /* LCDICR */
 392         s->int_status &= ~val;
 393         pl110_update(s);
 394         break;
 395     default:
 396         cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset);
 397     }
 398 }
 399
 400 static CPUReadMemoryFunc *pl110_readfn[] = {
 401    pl110_read,
 402    pl110_read,
 403    pl110_read
 404 };
 405
 406 static CPUWriteMemoryFunc *pl110_writefn[] = {
 407    pl110_write,
 408    pl110_write,
 409    pl110_write
 410 };
 411
 412 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq,
 413                  int versatile)
 414 {
 415     pl110_state *s;
 416     int iomemtype;
 417
 418     s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
 419     iomemtype = cpu_register_io_memory(0, pl110_readfn,
 420                                        pl110_writefn, s);
 421     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 422     s->base = base;
 423     s->ds = ds;
 424     s->versatile = versatile;
 425     s->irq = irq;
 426     graphic_console_init(ds, pl110_update_display, pl110_invalidate_display,
 427                          NULL, s);
 428     /* ??? Save/restore.  */
 429     return s;
 430 }