4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 struct omap_lcd_panel_s
{
24 target_phys_addr_t base
;
28 ram_addr_t emiff_base
;
41 struct omap_dma_lcd_channel_s
*dma
;
42 uint16_t palette
[256];
49 static void omap_lcd_interrupts(struct omap_lcd_panel_s
*s
)
51 if (s
->frame_done
&& (s
->interrupts
& 1)) {
52 qemu_irq_raise(s
->irq
);
56 if (s
->palette_done
&& (s
->interrupts
& 2)) {
57 qemu_irq_raise(s
->irq
);
62 qemu_irq_raise(s
->irq
);
66 qemu_irq_lower(s
->irq
);
69 #include "pixel_ops.h"
71 typedef void draw_line_func(
72 uint8_t *d
, const uint8_t *s
, int width
, const uint16_t *pal
);
75 #include "omap_lcd_template.h"
77 #include "omap_lcd_template.h"
79 #include "omap_lcd_template.h"
81 #include "omap_lcd_template.h"
83 static draw_line_func
*draw_line_table2
[33] = {
89 }, *draw_line_table4
[33] = {
95 }, *draw_line_table8
[33] = {
100 [32] = draw_line8_32
,
101 }, *draw_line_table12
[33] = {
104 [15] = draw_line12_15
,
105 [16] = draw_line12_16
,
106 [32] = draw_line12_32
,
107 }, *draw_line_table16
[33] = {
110 [15] = draw_line16_15
,
111 [16] = draw_line16_16
,
112 [32] = draw_line16_32
,
115 void omap_update_display(void *opaque
)
117 struct omap_lcd_panel_s
*omap_lcd
= (struct omap_lcd_panel_s
*) opaque
;
118 draw_line_func
*draw_line
;
119 int size
, dirty
[2], minline
, maxline
, height
;
120 int line
, width
, linesize
, step
, bpp
, frame_offset
;
121 ram_addr_t frame_base
, scanline
, newline
, x
;
124 if (!omap_lcd
|| omap_lcd
->plm
== 1 ||
125 !omap_lcd
->enable
|| !omap_lcd
->state
->depth
)
129 if (omap_lcd
->plm
!= 2) {
130 memcpy(omap_lcd
->palette
, phys_ram_base
+
131 omap_lcd
->dma
->phys_framebuffer
[
132 omap_lcd
->dma
->current_frame
], 0x200);
133 switch (omap_lcd
->palette
[0] >> 12 & 7) {
135 frame_offset
+= 0x200;
138 frame_offset
+= 0x20;
143 switch ((omap_lcd
->palette
[0] >> 12) & 7) {
145 draw_line
= draw_line_table2
[omap_lcd
->state
->depth
];
150 draw_line
= draw_line_table4
[omap_lcd
->state
->depth
];
155 draw_line
= draw_line_table8
[omap_lcd
->state
->depth
];
161 draw_line
= draw_line_table12
[omap_lcd
->state
->depth
];
163 draw_line
= draw_line_table16
[omap_lcd
->state
->depth
];
168 /* Unsupported at the moment. */
173 width
= omap_lcd
->width
;
174 if (width
!= omap_lcd
->state
->width
||
175 omap_lcd
->height
!= omap_lcd
->state
->height
) {
176 dpy_resize(omap_lcd
->state
,
177 omap_lcd
->width
, omap_lcd
->height
);
178 omap_lcd
->invalidate
= 1;
181 if (omap_lcd
->dma
->current_frame
== 0)
182 size
= omap_lcd
->dma
->src_f1_bottom
- omap_lcd
->dma
->src_f1_top
;
184 size
= omap_lcd
->dma
->src_f2_bottom
- omap_lcd
->dma
->src_f2_top
;
186 if (frame_offset
+ ((width
* omap_lcd
->height
* bpp
) >> 3) > size
+ 2) {
187 omap_lcd
->sync_error
= 1;
188 omap_lcd_interrupts(omap_lcd
);
189 omap_lcd
->enable
= 0;
194 frame_base
= omap_lcd
->dma
->phys_framebuffer
[
195 omap_lcd
->dma
->current_frame
] + frame_offset
;
196 omap_lcd
->dma
->condition
|= 1 << omap_lcd
->dma
->current_frame
;
197 if (omap_lcd
->dma
->interrupts
& 1)
198 qemu_irq_raise(omap_lcd
->dma
->irq
);
199 if (omap_lcd
->dma
->dual
)
200 omap_lcd
->dma
->current_frame
^= 1;
202 if (!omap_lcd
->state
->depth
)
206 height
= omap_lcd
->height
;
207 if (omap_lcd
->subpanel
& (1 << 31)) {
208 if (omap_lcd
->subpanel
& (1 << 29))
209 line
= (omap_lcd
->subpanel
>> 16) & 0x3ff;
211 height
= (omap_lcd
->subpanel
>> 16) & 0x3ff;
212 /* TODO: fill the rest of the panel with DPD */
214 step
= width
* bpp
>> 3;
215 scanline
= frame_base
+ step
* line
;
216 s
= (uint8_t *) (phys_ram_base
+ scanline
);
217 d
= omap_lcd
->state
->data
;
218 linesize
= omap_lcd
->state
->linesize
;
220 dirty
[0] = dirty
[1] =
221 cpu_physical_memory_get_dirty(scanline
, VGA_DIRTY_FLAG
);
224 for (; line
< height
; line
++) {
225 newline
= scanline
+ step
;
226 for (x
= scanline
+ TARGET_PAGE_SIZE
; x
< newline
;
227 x
+= TARGET_PAGE_SIZE
) {
228 dirty
[1] = cpu_physical_memory_get_dirty(x
, VGA_DIRTY_FLAG
);
229 dirty
[0] |= dirty
[1];
231 if (dirty
[0] || omap_lcd
->invalidate
) {
232 draw_line(d
, s
, width
, omap_lcd
->palette
);
243 if (maxline
>= minline
) {
244 dpy_update(omap_lcd
->state
, 0, minline
, width
, maxline
);
245 cpu_physical_memory_reset_dirty(frame_base
+ step
* minline
,
246 frame_base
+ step
* maxline
, VGA_DIRTY_FLAG
);
250 static int ppm_save(const char *filename
, uint8_t *data
,
251 int w
, int h
, int linesize
)
258 f
= fopen(filename
, "wb");
261 fprintf(f
, "P6\n%d %d\n%d\n", w
, h
, 255);
264 for (y
= 0; y
< h
; y
++) {
266 for (x
= 0; x
< w
; x
++) {
270 fputc((v
>> 8) & 0xf8, f
);
271 fputc((v
>> 3) & 0xfc, f
);
272 fputc((v
<< 3) & 0xf8, f
);
277 fputc((v
>> 16) & 0xff, f
);
278 fputc((v
>> 8) & 0xff, f
);
279 fputc((v
) & 0xff, f
);
290 void omap_screen_dump(void *opaque
, const char *filename
) {
291 struct omap_lcd_panel_s
*omap_lcd
= opaque
;
292 omap_update_display(opaque
);
293 if (omap_lcd
&& omap_lcd
->state
->data
)
294 ppm_save(filename
, omap_lcd
->state
->data
,
295 omap_lcd
->width
, omap_lcd
->height
,
296 omap_lcd
->state
->linesize
);
299 void omap_invalidate_display(void *opaque
) {
300 struct omap_lcd_panel_s
*omap_lcd
= opaque
;
301 omap_lcd
->invalidate
= 1;
304 void omap_lcd_update(struct omap_lcd_panel_s
*s
) {
306 s
->dma
->current_frame
= -1;
310 omap_lcd_interrupts(s
);
314 if (s
->dma
->current_frame
== -1) {
317 s
->dma
->current_frame
= 0;
320 if (!s
->dma
->mpu
->port
[s
->dma
->src
].addr_valid(s
->dma
->mpu
,
321 s
->dma
->src_f1_top
) ||
323 s
->dma
->src
].addr_valid(s
->dma
->mpu
,
324 s
->dma
->src_f1_bottom
) ||
327 s
->dma
->src
].addr_valid(s
->dma
->mpu
,
328 s
->dma
->src_f2_top
) ||
330 s
->dma
->src
].addr_valid(s
->dma
->mpu
,
331 s
->dma
->src_f2_bottom
)))) {
332 s
->dma
->condition
|= 1 << 2;
333 if (s
->dma
->interrupts
& (1 << 1))
334 qemu_irq_raise(s
->dma
->irq
);
339 if (s
->dma
->src
== imif
) {
340 /* Framebuffers are in SRAM */
341 s
->dma
->phys_framebuffer
[0] = s
->imif_base
+
342 s
->dma
->src_f1_top
- OMAP_IMIF_BASE
;
344 s
->dma
->phys_framebuffer
[1] = s
->imif_base
+
345 s
->dma
->src_f2_top
- OMAP_IMIF_BASE
;
347 /* Framebuffers are in RAM */
348 s
->dma
->phys_framebuffer
[0] = s
->emiff_base
+
349 s
->dma
->src_f1_top
- OMAP_EMIFF_BASE
;
351 s
->dma
->phys_framebuffer
[1] = s
->emiff_base
+
352 s
->dma
->src_f2_top
- OMAP_EMIFF_BASE
;
355 if (s
->plm
!= 2 && !s
->palette_done
) {
356 memcpy(s
->palette
, phys_ram_base
+
357 s
->dma
->phys_framebuffer
[s
->dma
->current_frame
], 0x200);
359 omap_lcd_interrupts(s
);
363 static uint32_t omap_lcdc_read(void *opaque
, target_phys_addr_t addr
)
365 struct omap_lcd_panel_s
*s
= (struct omap_lcd_panel_s
*) opaque
;
366 int offset
= addr
- s
->base
;
369 case 0x00: /* LCD_CONTROL */
370 return (s
->tft
<< 23) | (s
->plm
<< 20) |
371 (s
->tft
<< 7) | (s
->interrupts
<< 3) |
372 (s
->mono
<< 1) | s
->enable
| s
->ctrl
| 0xfe000c34;
374 case 0x04: /* LCD_TIMING0 */
375 return (s
->timing
[0] << 10) | (s
->width
- 1) | 0x0000000f;
377 case 0x08: /* LCD_TIMING1 */
378 return (s
->timing
[1] << 10) | (s
->height
- 1);
380 case 0x0c: /* LCD_TIMING2 */
381 return s
->timing
[2] | 0xfc000000;
383 case 0x10: /* LCD_STATUS */
384 return (s
->palette_done
<< 6) | (s
->sync_error
<< 2) | s
->frame_done
;
386 case 0x14: /* LCD_SUBPANEL */
396 static void omap_lcdc_write(void *opaque
, target_phys_addr_t addr
,
399 struct omap_lcd_panel_s
*s
= (struct omap_lcd_panel_s
*) opaque
;
400 int offset
= addr
- s
->base
;
403 case 0x00: /* LCD_CONTROL */
404 s
->plm
= (value
>> 20) & 3;
405 s
->tft
= (value
>> 7) & 1;
406 s
->interrupts
= (value
>> 3) & 3;
407 s
->mono
= (value
>> 1) & 1;
408 s
->ctrl
= value
& 0x01cff300;
409 if (s
->enable
!= (value
& 1)) {
410 s
->enable
= value
& 1;
415 case 0x04: /* LCD_TIMING0 */
416 s
->timing
[0] = value
>> 10;
417 s
->width
= (value
& 0x3ff) + 1;
420 case 0x08: /* LCD_TIMING1 */
421 s
->timing
[1] = value
>> 10;
422 s
->height
= (value
& 0x3ff) + 1;
425 case 0x0c: /* LCD_TIMING2 */
426 s
->timing
[2] = value
;
429 case 0x10: /* LCD_STATUS */
432 case 0x14: /* LCD_SUBPANEL */
433 s
->subpanel
= value
& 0xa1ffffff;
441 static CPUReadMemoryFunc
*omap_lcdc_readfn
[] = {
447 static CPUWriteMemoryFunc
*omap_lcdc_writefn
[] = {
453 void omap_lcdc_reset(struct omap_lcd_panel_s
*s
)
455 s
->dma
->current_frame
= -1;
475 struct omap_lcd_panel_s
*omap_lcdc_init(target_phys_addr_t base
, qemu_irq irq
,
476 struct omap_dma_lcd_channel_s
*dma
, DisplayState
*ds
,
477 ram_addr_t imif_base
, ram_addr_t emiff_base
, omap_clk clk
)
480 struct omap_lcd_panel_s
*s
= (struct omap_lcd_panel_s
*)
481 qemu_mallocz(sizeof(struct omap_lcd_panel_s
));
487 s
->imif_base
= imif_base
;
488 s
->emiff_base
= emiff_base
;
491 iomemtype
= cpu_register_io_memory(0, omap_lcdc_readfn
,
492 omap_lcdc_writefn
, s
);
493 cpu_register_physical_memory(s
->base
, 0x100, iomemtype
);
495 graphic_console_init(ds
, omap_update_display
,
496 omap_invalidate_display
, omap_screen_dump
, s
);