hw/mipsnet.c

   1 #include "vl.h"
   2
   3 #define DEBUG_MIPSNET_SEND
   4 #define DEBUG_MIPSNET_RECEIVE
   5 //#define DEBUG_MIPSNET_DATA
   6 #define DEBUG_MIPSNET_IRQ
   7
   8 /* MIPSnet register offsets */
   9
  10 #define MIPSNET_DEV_ID          0x00
  11 # define MIPSNET_DEV_ID_STRING  "MIPSNET0"
  12 #define MIPSNET_BUSY            0x08
  13 #define MIPSNET_RX_DATA_COUNT   0x0c
  14 #define MIPSNET_TX_DATA_COUNT   0x10
  15 #define MIPSNET_INT_CTL         0x14
  16 # define MIPSNET_INTCTL_TXDONE          0x00000001
  17 # define MIPSNET_INTCTL_RXDONE          0x00000002
  18 # define MIPSNET_INTCTL_TESTBIT         0x80000000
  19 #define MIPSNET_INTERRUPT_INFO  0x18
  20 #define MIPSNET_RX_DATA_BUFFER  0x1c
  21 #define MIPSNET_TX_DATA_BUFFER  0x20
  22
  23 #define MAX_ETH_FRAME_SIZE      1514
  24
  25 typedef struct MIPSnetState {
  26     uint32_t busy;
  27     uint32_t rx_count;
  28     uint32_t rx_read;
  29     uint32_t tx_count;
  30     uint32_t tx_written;
  31     uint32_t intctl;
  32     uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
  33     uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
  34     qemu_irq irq;
  35     VLANClientState *vc;
  36     NICInfo *nd;
  37 } MIPSnetState;
  38
  39 static void mipsnet_reset(MIPSnetState *s)
  40 {
  41     s->busy = 1;
  42     s->rx_count = 0;
  43     s->rx_read = 0;
  44     s->tx_count = 0;
  45     s->tx_written = 0;
  46     s->intctl = 0;
  47     memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
  48     memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
  49 }
  50
  51 static void mipsnet_update_irq(MIPSnetState *s)
  52 {
  53     int isr = !!s->intctl;
  54 #ifdef DEBUG_MIPSNET_IRQ
  55     printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
  56 #endif
  57     qemu_set_irq(s->irq, isr);
  58 }
  59
  60 static int mipsnet_buffer_full(MIPSnetState *s)
  61 {
  62     if (s->rx_count >= MAX_ETH_FRAME_SIZE)
  63         return 1;
  64     return 0;
  65 }
  66
  67 static int mipsnet_can_receive(void *opaque)
  68 {
  69     MIPSnetState *s = opaque;
  70
  71     if (s->busy)
  72         return 0;
  73     return !mipsnet_buffer_full(s);
  74 }
  75
  76 static void mipsnet_receive(void *opaque, const uint8_t *buf, int size)
  77 {
  78     MIPSnetState *s = opaque;
  79
  80 #ifdef DEBUG_MIPSNET_RECEIVE
  81     printf("mipsnet: receiving len=%d\n", size);
  82 #endif
  83     if (!mipsnet_can_receive(opaque))
  84         return;
  85
  86     s->busy = 1;
  87
  88     /* Just accept everything. */
  89
  90     /* Write packet data. */
  91     memcpy(s->rx_buffer, buf, size);
  92
  93     s->rx_count = size;
  94     s->rx_read = 0;
  95
  96     /* Now we can signal we have received something. */
  97     s->intctl |= MIPSNET_INTCTL_RXDONE;
  98     mipsnet_update_irq(s);
  99 }
 100
 101 static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
 102 {
 103     MIPSnetState *s = opaque;
 104     int ret = 0;
 105     const char *devid = MIPSNET_DEV_ID_STRING;
 106
 107     addr &= 0x3f;
 108     switch (addr) {
 109     case MIPSNET_DEV_ID:
 110         ret = *((uint32_t *)&devid);
 111         break;
 112     case MIPSNET_DEV_ID + 4:
 113         ret = *((uint32_t *)(&devid + 4));
 114         break;
 115     case MIPSNET_BUSY:
 116         ret = s->busy;
 117         break;
 118     case MIPSNET_RX_DATA_COUNT:
 119         ret = s->rx_count;
 120         break;
 121     case MIPSNET_TX_DATA_COUNT:
 122         ret = s->tx_count;
 123         break;
 124     case MIPSNET_INT_CTL:
 125         ret = s->intctl;
 126         s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
 127         break;
 128     case MIPSNET_INTERRUPT_INFO:
 129         /* XXX: This seems to be a per-VPE interrupt number. */
 130         ret = 0;
 131         break;
 132     case MIPSNET_RX_DATA_BUFFER:
 133         if (s->rx_count) {
 134             s->rx_count--;
 135             ret = s->rx_buffer[s->rx_read++];
 136         }
 137         break;
 138     /* Reads as zero. */
 139     case MIPSNET_TX_DATA_BUFFER:
 140     default:
 141         break;
 142     }
 143 #ifdef DEBUG_MIPSNET_DATA
 144     printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
 145 #endif
 146     return ret;
 147 }
 148
 149 static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 150 {
 151     MIPSnetState *s = opaque;
 152
 153     addr &= 0x3f;
 154 #ifdef DEBUG_MIPSNET_DATA
 155     printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
 156 #endif
 157     switch (addr) {
 158     case MIPSNET_TX_DATA_COUNT:
 159         s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
 160         s->tx_written = 0;
 161         break;
 162     case MIPSNET_INT_CTL:
 163         if (val & MIPSNET_INTCTL_TXDONE) {
 164             s->intctl &= ~MIPSNET_INTCTL_TXDONE;
 165         } else if (val & MIPSNET_INTCTL_RXDONE) {
 166             s->intctl &= ~MIPSNET_INTCTL_RXDONE;
 167         } else if (val & MIPSNET_INTCTL_TESTBIT) {
 168             mipsnet_reset(s);
 169             s->intctl |= MIPSNET_INTCTL_TESTBIT;
 170         } else if (!val) {
 171             /* ACK testbit interrupt, flag was cleared on read. */
 172         }
 173         s->busy = !!s->intctl;
 174         mipsnet_update_irq(s);
 175         break;
 176     case MIPSNET_TX_DATA_BUFFER:
 177         s->tx_buffer[s->tx_written++] = val;
 178         if (s->tx_written == s->tx_count) {
 179             /* Send buffer. */
 180 #ifdef DEBUG_MIPSNET_SEND
 181             printf("mipsnet: sending len=%d\n", s->tx_count);
 182 #endif
 183             qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
 184             s->tx_count = s->tx_written = 0;
 185             s->intctl |= MIPSNET_INTCTL_TXDONE;
 186             s->busy = 1;
 187             mipsnet_update_irq(s);
 188         }
 189         break;
 190     /* Read-only registers */
 191     case MIPSNET_DEV_ID:
 192     case MIPSNET_BUSY:
 193     case MIPSNET_RX_DATA_COUNT:
 194     case MIPSNET_INTERRUPT_INFO:
 195     case MIPSNET_RX_DATA_BUFFER:
 196     default:
 197         break;
 198     }
 199 }
 200
 201 static void mipsnet_save(QEMUFile *f, void *opaque)
 202 {
 203     MIPSnetState *s = opaque;
 204
 205     qemu_put_be32s(f, &s->busy);
 206     qemu_put_be32s(f, &s->rx_count);
 207     qemu_put_be32s(f, &s->rx_read);
 208     qemu_put_be32s(f, &s->tx_count);
 209     qemu_put_be32s(f, &s->tx_written);
 210     qemu_put_be32s(f, &s->intctl);
 211     qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
 212     qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
 213 }
 214
 215 static int mipsnet_load(QEMUFile *f, void *opaque, int version_id)
 216 {
 217     MIPSnetState *s = opaque;
 218
 219     if (version_id > 0)
 220         return -EINVAL;
 221
 222     qemu_get_be32s(f, &s->busy);
 223     qemu_get_be32s(f, &s->rx_count);
 224     qemu_get_be32s(f, &s->rx_read);
 225     qemu_get_be32s(f, &s->tx_count);
 226     qemu_get_be32s(f, &s->tx_written);
 227     qemu_get_be32s(f, &s->intctl);
 228     qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
 229     qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
 230
 231     return 0;
 232 }
 233
 234 void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
 235 {
 236     MIPSnetState *s;
 237
 238     s = qemu_mallocz(sizeof(MIPSnetState));
 239     if (!s)
 240         return;
 241
 242     register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
 243     register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
 244     register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
 245     register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
 246     register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
 247     register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
 248
 249     s->irq = irq;
 250     s->nd = nd;
 251     if (nd && nd->vlan) {
 252         s->vc = qemu_new_vlan_client(nd->vlan, mipsnet_receive,
 253                                      mipsnet_can_receive, s);
 254     } else {
 255         s->vc = NULL;
 256     }
 257
 258     snprintf(s->vc->info_str, sizeof(s->vc->info_str),
 259              "mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
 260               s->nd->macaddr[0],
 261               s->nd->macaddr[1],
 262               s->nd->macaddr[2],
 263               s->nd->macaddr[3],
 264               s->nd->macaddr[4],
 265               s->nd->macaddr[5]);
 266
 267     mipsnet_reset(s);
 268     register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
 269 }