hw/mips_r4k.c

   1 /*
   2  * QEMU/MIPS pseudo-board
   3  *
   4  * emulates a simple machine with ISA-like bus.
   5  * ISA IO space mapped to the 0x14000000 (PHYS) and
   6  * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
   7  * All peripherial devices are attached to this "bus" with
   8  * the standard PC ISA addresses.
   9 */
  10 #include "vl.h"
  11
  12 #ifdef TARGET_WORDS_BIGENDIAN
  13 #define BIOS_FILENAME "mips_bios.bin"
  14 #else
  15 #define BIOS_FILENAME "mipsel_bios.bin"
  16 #endif
  17
  18 #ifdef TARGET_MIPS64
  19 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
  20 #else
  21 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
  22 #endif
  23
  24 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
  25
  26 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  27 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  28 static const int ide_irq[2] = { 14, 15 };
  29
  30 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
  31 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
  32
  33 extern FILE *logfile;
  34
  35 static PITState *pit; /* PIT i8254 */
  36
  37 /*i8254 PIT is attached to the IRQ0 at PIC i8259 */
  38
  39 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
  40                               uint32_t val)
  41 {
  42     if ((addr & 0xffff) == 0 && val == 42)
  43         qemu_system_reset_request ();
  44     else if ((addr & 0xffff) == 4 && val == 42)
  45         qemu_system_shutdown_request ();
  46 }
  47
  48 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
  49 {
  50     return 0;
  51 }
  52
  53 static CPUWriteMemoryFunc *mips_qemu_write[] = {
  54     &mips_qemu_writel,
  55     &mips_qemu_writel,
  56     &mips_qemu_writel,
  57 };
  58
  59 static CPUReadMemoryFunc *mips_qemu_read[] = {
  60     &mips_qemu_readl,
  61     &mips_qemu_readl,
  62     &mips_qemu_readl,
  63 };
  64
  65 static int mips_qemu_iomemtype = 0;
  66
  67 static void load_kernel (CPUState *env, int ram_size,
  68                          const char *kernel_filename,
  69                          const char *kernel_cmdline,
  70                          const char *initrd_filename)
  71 {
  72     int64_t entry, kernel_low, kernel_high;
  73     long kernel_size, initrd_size;
  74     ram_addr_t initrd_offset;
  75
  76     kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND,
  77                            &entry, &kernel_low, &kernel_high);
  78     if (kernel_size >= 0) {
  79         if ((entry & ~0x7fffffffULL) == 0x80000000)
  80             entry = (int32_t)entry;
  81         env->PC[env->current_tc] = entry;
  82     } else {
  83         fprintf(stderr, "qemu: could not load kernel '%s'\n",
  84                 kernel_filename);
  85         exit(1);
  86     }
  87
  88     /* load initrd */
  89     initrd_size = 0;
  90     initrd_offset = 0;
  91     if (initrd_filename) {
  92         initrd_size = get_image_size (initrd_filename);
  93         if (initrd_size > 0) {
  94             initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
  95             if (initrd_offset + initrd_size > ram_size) {
  96                 fprintf(stderr,
  97                         "qemu: memory too small for initial ram disk '%s'\n",
  98                         initrd_filename);
  99                 exit(1);
 100             }
 101             initrd_size = load_image(initrd_filename,
 102                                      phys_ram_base + initrd_offset);
 103         }
 104         if (initrd_size == (target_ulong) -1) {
 105             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 106                     initrd_filename);
 107             exit(1);
 108         }
 109     }
 110
 111     /* Store command line.  */
 112     if (initrd_size > 0) {
 113         int ret;
 114         ret = sprintf(phys_ram_base + (16 << 20) - 256,
 115                       "rd_start=0x" TARGET_FMT_lx " rd_size=%li ",
 116                       PHYS_TO_VIRT((uint32_t)initrd_offset),
 117                       initrd_size);
 118         strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
 119     }
 120     else {
 121         strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
 122     }
 123
 124     *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 125     *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 126 }
 127
 128 static void main_cpu_reset(void *opaque)
 129 {
 130     CPUState *env = opaque;
 131     cpu_reset(env);
 132     cpu_mips_register(env, NULL);
 133
 134     if (env->kernel_filename)
 135         load_kernel (env, env->ram_size, env->kernel_filename,
 136                      env->kernel_cmdline, env->initrd_filename);
 137 }
 138
 139 static
 140 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
 141                     DisplayState *ds, const char **fd_filename, int snapshot,
 142                     const char *kernel_filename, const char *kernel_cmdline,
 143                     const char *initrd_filename, const char *cpu_model)
 144 {
 145     char buf[1024];
 146     unsigned long bios_offset;
 147     int bios_size;
 148     CPUState *env;
 149     RTCState *rtc_state;
 150     int i;
 151     mips_def_t *def;
 152     qemu_irq *i8259;
 153
 154     /* init CPUs */
 155     if (cpu_model == NULL) {
 156 #ifdef TARGET_MIPS64
 157         cpu_model = "R4000";
 158 #else
 159         cpu_model = "24Kf";
 160 #endif
 161     }
 162     if (mips_find_by_name(cpu_model, &def) != 0)
 163         def = NULL;
 164     env = cpu_init();
 165     cpu_mips_register(env, def);
 166     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 167     qemu_register_reset(main_cpu_reset, env);
 168
 169     /* allocate RAM */
 170     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 171
 172     if (!mips_qemu_iomemtype) {
 173         mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
 174                                                      mips_qemu_write, NULL);
 175     }
 176     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 177
 178     /* Try to load a BIOS image. If this fails, we continue regardless,
 179        but initialize the hardware ourselves. When a kernel gets
 180        preloaded we also initialize the hardware, since the BIOS wasn't
 181        run. */
 182     bios_offset = ram_size + vga_ram_size;
 183     if (bios_name == NULL)
 184         bios_name = BIOS_FILENAME;
 185     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 186     bios_size = load_image(buf, phys_ram_base + bios_offset);
 187     if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
 188         cpu_register_physical_memory(0x1fc00000,
 189                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 190     } else {
 191         /* not fatal */
 192         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 193                 buf);
 194     }
 195
 196     if (kernel_filename) {
 197         load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
 198                      initrd_filename);
 199         env->ram_size = ram_size;
 200         env->kernel_filename = kernel_filename;
 201         env->kernel_cmdline = kernel_cmdline;
 202         env->initrd_filename = initrd_filename;
 203     }
 204
 205     /* Init CPU internal devices */
 206     cpu_mips_irq_init_cpu(env);
 207     cpu_mips_clock_init(env);
 208     cpu_mips_irqctrl_init();
 209
 210     /* The PIC is attached to the MIPS CPU INT0 pin */
 211     i8259 = i8259_init(env->irq[2]);
 212
 213     rtc_state = rtc_init(0x70, i8259[8]);
 214
 215     /* Register 64 KB of ISA IO space at 0x14000000 */
 216     isa_mmio_init(0x14000000, 0x00010000);
 217     isa_mem_base = 0x10000000;
 218
 219     pit = pit_init(0x40, i8259[0]);
 220
 221     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 222         if (serial_hds[i]) {
 223             serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
 224         }
 225     }
 226
 227     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 228                  vga_ram_size);
 229
 230     if (nd_table[0].vlan) {
 231         if (nd_table[0].model == NULL
 232             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 233             isa_ne2000_init(0x300, i8259[9], &nd_table[0]);
 234         } else if (strcmp(nd_table[0].model, "?") == 0) {
 235             fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
 236             exit (1);
 237         } else {
 238             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 239             exit (1);
 240         }
 241     }
 242
 243     for(i = 0; i < 2; i++)
 244         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 245                      bs_table[2 * i], bs_table[2 * i + 1]);
 246
 247     i8042_init(i8259[1], i8259[12], 0x60);
 248     ds1225y_init(0x9000, "nvram");
 249 }
 250
 251 QEMUMachine mips_machine = {
 252     "mips",
 253     "mips r4k platform",
 254     mips_r4k_init,
 255 };