hw/sm502.c

   1 /*
   2  * QEMU sm502 emulation
   3  *
   4  * Copyright (c) 2009 yajin <yajin@vm-kernel.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /*sm502 is used in gdium system.*/
  26
  27 #include <stdio.h>
  28 #include <assert.h>
  29 #include "hw.h"
  30 #include "pc.h"
  31 #include "pci.h"
  32 #include "console.h"
  33 #include "devices.h"
  34 #include "sm502.h"
  35
  36 //#define DEBUG
  37 #define DEBUG_PCICONF                     (1<<0x0)
  38 #define DEBUG_CONF                           (1<<0x1)
  39 #define DEBUG_GPIO                           (1<<0x2)
  40 #define DEBUG_MMIO                                                              (1<<0x3)
  41
  42 #define DEBUG_ALL                         (0xffffffff)
  43 #define  DEBUG_FLAG                    DEBUG_ALL
  44
  45 #ifdef DEBUG
  46 #define debug_out(flag,out) {\
  47         if (flag & DEBUG_FLAG) printf out; \
  48         } while(0);
  49 #else
  50 #define debug_out(flag,out)
  51 #endif
  52 #if 0
  53 static uint32_t sm502_badwidth_read8(void *opaque, target_phys_addr_t addr)
  54 {
  55     SM502_8B_REG(addr);
  56     /*to make debug easy */
  57     exit(-1);
  58     return 0;
  59 }
  60
  61 static void sm502_badwidth_write8(void *opaque, target_phys_addr_t addr,
  62                            uint32_t value)
  63 {
  64     SM502_8B_REG(addr);
  65     exit(-1);
  66 }
  67
  68 static uint32_t sm502_badwidth_read16(void *opaque, target_phys_addr_t addr)
  69 {
  70     SM502_16B_REG(addr);
  71     /*to make debug easy */
  72     exit(-1);
  73     return 0;
  74 }
  75 static void sm502_badwidth_write16(void *opaque, target_phys_addr_t addr,
  76                             uint32_t value)
  77 {
  78     SM502_16B_REG(addr);
  79     exit(-1);
  80 }
  81 #endif
  82 static uint32_t sm502_badwidth_read32(void *opaque, target_phys_addr_t addr)
  83 {
  84     SM502_32B_REG(addr);
  85     /*to make debug easy */
  86     exit(-1);
  87     return 0;
  88 }
  89 static void sm502_badwidth_write32(void *opaque, target_phys_addr_t addr,
  90                             uint32_t value)
  91 {
  92     SM502_32B_REG(addr);
  93     exit(-1);
  94 }
  95
  96 void sm502_gpio_out_set(struct sm502_s *s, int line, qemu_irq handler)
  97 {
  98     if (line >= 64 || line < 0)
  99         cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
 100     s->out_handler[line & 63] = handler;
 101 }
 102
 103 qemu_irq *sm502_gpio_in_get(struct sm502_s *s, int line)
 104 {
 105     if (line >= 64 || line < 0)
 106         cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
 107     return s->in_handler + (line & 31);
 108 }
 109
 110 void sm502_gpio_set_pin(struct sm502_s *s, int line, int level)
 111 {
 112     if (line >= 64 || line < 0)
 113         cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
 114     if (level)
 115     {
 116         if (line < 32)
 117             s->gpio_data_low |= level << line;
 118         else
 119             s->gpio_data_high |= level << (line - 32);
 120     }
 121     else
 122     {
 123         if (line < 32)
 124             s->gpio_data_low &= (~(1 << line));
 125         else
 126             s->gpio_data_high &= (~(1 << (line - 32)));
 127     }
 128 }
 129
 130 int sm502_gpio_get_pin(struct sm502_s *s, int line)
 131 {
 132     if (line >= 64 || line < 0)
 133         cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
 134     if (line < 32)
 135         return (s->gpio_data_low & (1 << line)) >> line;
 136     else
 137         return (s->gpio_data_high & (1 << line)) >> line;
 138 }
 139
 140 static void sm502_gpio_set(void *opaque, int line, int level)
 141 {
 142     struct sm502_s *s = (struct sm502_s *) opaque;
 143     if (line >= 64 || line < 0)
 144         cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
 145     sm502_gpio_set_pin(s, line, level);
 146 }
 147
 148 static void sm502_gpio_init(struct sm502_s *s)
 149 {
 150     s->in_handler = qemu_allocate_irqs(sm502_gpio_set, s, 64);
 151 }
 152
 153 static uint32_t sm502_read32(void *opaque, target_phys_addr_t addr)
 154 {
 155     struct sm502_s *s = (struct sm502_s *) opaque;
 156
 157     debug_out(DEBUG_CONF,
 158               ("%s addr " TARGET_FMT_plx " pc " TARGET_FMT_plx "\n",
 159                __FUNCTION__, addr, cpu_single_env->active_tc.PC));
 160
 161     switch (addr)
 162     {
 163     case 0x0:
 164         return s->system_control;
 165     case 0x4:
 166         return s->misc_control;
 167     case 0x08:
 168         return s->gpio_low32;
 169     case 0x0c:
 170         return s->gpio_high32;
 171     case 0x10:
 172         return s->dram_control;
 173     case 0x14:
 174         return s->arb_control;
 175     case 0x24:
 176         return s->command_list_status;
 177     case 0x28:
 178         return s->raw_int_status;
 179     case 0x2c:
 180         return s->int_status;
 181     case 0x30:
 182         return s->int_mask;
 183     case 0x34:
 184         return s->debug_control;
 185     case 0x38:
 186         return s->current_gate;
 187     case 0x3c:
 188         return s->current_clock;
 189     case 0x40:
 190         return s->power0_gate;
 191     case 0x44:
 192         return s->power0_clock;
 193     case 0x48:
 194         return s->power1_gate;
 195     case 0x4c:
 196         return s->power1_clock;
 197     case 0x50:
 198         return s->sleep_gate;
 199     case 0x54:
 200         return s->power_control;
 201     case 0x58:
 202         return s->pci_master_base;
 203     case 0x5c:
 204         return s->endian_control;
 205     case 0x60:
 206         return s->device_id;
 207     case 0x64:
 208         return s->pll_clock_count;
 209     case 0x68:
 210         return s->misc_timing;
 211     case 0x6c:
 212         return s->current_sdram_clock;
 213     case 0x70:
 214         return s->non_cache_address;
 215     case 0x74:
 216         return s->pll_control;
 217     case 0x10000:
 218         return s->gpio_data_low;
 219     case 0x10004:
 220         return s->gpio_data_high;
 221     case 0x10008:
 222         return s->gpio_datadir_low;
 223     case 0x1000c:
 224         return s->gpio_datadir_high;
 225     case 0x10010:
 226         return s->gpio_int_setup;
 227     case 0x10014:
 228         return s->gpio_int_status;
 229     default:
 230         cpu_abort(cpu_single_env,
 231                   "%s undefined addr " TARGET_FMT_plx
 232                   "  pc " TARGET_FMT_plx "\n", __FUNCTION__, addr,
 233                   cpu_single_env->active_tc.PC);
 234
 235     }
 236
 237 }
 238
 239 static void sm502_write32(void *opaque, target_phys_addr_t addr, uint32_t value)
 240 {
 241     struct sm502_s *s = (struct sm502_s *) opaque;
 242     uint32_t diff;
 243     int ln;
 244
 245     debug_out(DEBUG_CONF,
 246               ("%s addr " TARGET_FMT_plx " value %x pc " TARGET_FMT_plx "\n",
 247                __FUNCTION__, addr, value, cpu_single_env->active_tc.PC));
 248
 249
 250     switch (addr)
 251     {
 252     case 0x24:
 253     case 0x38:
 254     case 0x3c:
 255     case 0x60:
 256     case 0x64:
 257     case 0x6c:
 258         SM502_RO_REG(addr);
 259         break;
 260     case 0x0:
 261         s->system_control = value & 0xff00b8f7;
 262         break;
 263     case 0x4:
 264         s->misc_control = value & 0xff7fff10;
 265         break;
 266     case 0x08:
 267         s->gpio_low32 = value;
 268         break;
 269     case 0x0c:
 270         s->gpio_high32 = value;
 271         break;
 272     case 0x10:
 273         s->dram_control = value & 0x7fffffc3;
 274         break;
 275     case 0x14:
 276         s->arb_control = value & 0x77777777;
 277         break;
 278     case 0x28:
 279         s->raw_int_status &= (~(value & 0x7f));
 280         break;
 281     case 0x2c:
 282         s->int_status = value & 0x400000;
 283         break;
 284     case 0x30:
 285         s->int_mask = value & 0xffdf3f5f;
 286         break;
 287     case 0x34:
 288         s->debug_control = value & 0xff;
 289         break;
 290     case 0x40:
 291         s->power0_gate = value & 0x71dff;
 292         break;
 293     case 0x44:
 294         s->power0_clock = value & 0xff3f1f1f;
 295         break;
 296     case 0x48:
 297         s->power1_gate = value & 0x61dff;
 298         break;
 299     case 0x4c:
 300         s->power1_clock = value & 0xff3f1f1f;
 301         break;
 302     case 0x50:
 303         s->sleep_gate = value & 0x786000;
 304         break;
 305     case 0x54:
 306         s->power_control = value & 0x7;
 307         break;
 308     case 0x58:
 309         s->pci_master_base = value & 0xfff00000;
 310         break;
 311     case 0x5c:
 312         s->endian_control = value & 0x1;
 313         break;
 314     case 0x68:
 315         s->misc_timing = value & 0xf1f1f4f;
 316         break;
 317     case 0x70:
 318         s->non_cache_address = value & 0x3fff;
 319         break;
 320     case 0x74:
 321         s->pll_control = value & 0x1fffff;
 322         break;
 323     case 0x10000:
 324         diff = (s->gpio_data_low ^ value) & s->gpio_datadir_low;
 325         s->gpio_data_low = value;
 326         while ((ln = ffs(diff)))
 327         {
 328             ln--;
 329             if (s->out_handler[ln])
 330                 qemu_set_irq(s->out_handler[ln], (value >> ln) & 1);
 331             diff &= ~(1 << ln);
 332         }
 333         break;
 334     case 0x10004:
 335         diff = (s->gpio_datadir_high ^ value) & s->gpio_datadir_high;
 336         s->gpio_data_high = value;
 337         while ((ln = ffs(diff)))
 338         {
 339             ln--;
 340             if (s->out_handler[ln + 32])
 341                 qemu_set_irq(s->out_handler[ln + 32], (value >> ln) & 1);
 342             diff &= ~(1 << ln);
 343         }
 344         break;
 345     case 0x10008:
 346         s->gpio_datadir_low = value;
 347         break;
 348     case 0x1000c:
 349         s->gpio_datadir_high = value;
 350         break;
 351     case 0x10010:
 352         s->gpio_int_setup = value & 0x7f7f7f;
 353         break;
 354     case 0x10014:
 355         s->gpio_int_status &= (~(value & 0x7f0000));
 356         break;
 357     default:
 358         cpu_abort(cpu_single_env,
 359                   "%s undefined addr " TARGET_FMT_plx
 360                   "  value %x pc " TARGET_FMT_plx "\n", __FUNCTION__, addr,
 361                   value, cpu_single_env->active_tc.PC);
 362
 363
 364     }
 365
 366 }
 367
 368
 369 static CPUReadMemoryFunc *sm502_readfn[] = {
 370     sm502_badwidth_read32,
 371     sm502_badwidth_read32,
 372     sm502_read32,
 373 };
 374
 375 static CPUWriteMemoryFunc *sm502_writefn[] = {
 376     sm502_badwidth_write32,
 377     sm502_badwidth_write32,
 378     sm502_write32,
 379 };
 380
 381 static uint32_t sm502_read_config(PCIDevice * d, uint32_t address, int len)
 382 {
 383     uint32_t val = 0;
 384
 385     debug_out(DEBUG_PCICONF, ("%s addr 0x%x  len %x pc " TARGET_FMT_plx "\n",
 386                               __FUNCTION__, address, len,
 387                               cpu_single_env->active_tc.PC));
 388
 389     switch (len)
 390     {
 391     default:
 392     case 4:
 393         if (address <= 0xfc)
 394             val = le32_to_cpu(*(uint32_t *) (d->config + address));
 395         break;
 396
 397     case 2:
 398         if (address <= 0xfe)
 399             val = le16_to_cpu(*(uint16_t *) (d->config + address));
 400         break;
 401     case 1:
 402         val = d->config[address];
 403         break;
 404     }
 405     return val;
 406
 407 }
 408
 409 static void sm502_write_config(PCIDevice * d, uint32_t address, uint32_t val,
 410                                int len)
 411 {
 412     int can_write, i;
 413     uint32_t addr;
 414     uint32_t new_sm502_mm_io;
 415     int iomemtype;
 416
 417     struct sm502_s *s = (struct sm502_s *) d;
 418
 419     debug_out(DEBUG_PCICONF,
 420               ("%s addr 0x%x value %x len %x pc " TARGET_FMT_plx "\n",
 421                __FUNCTION__, address, val, len, cpu_single_env->active_tc.PC));
 422
 423     /* not efficient, but simple */
 424     addr = address;
 425     for (i = 0; i < len; i++)
 426     {
 427         /* default read/write accesses */
 428         switch (addr)
 429         {
 430         case 0x00:
 431         case 0x01:
 432         case 0x02:
 433         case 0x03:
 434         case 0x08:
 435         case 0x09:
 436         case 0x0a:
 437         case 0x0b:
 438         case 0x0c:
 439         case 0x0d:
 440         case 0x2c:
 441         case 0x2d:
 442         case 0x2e:
 443         case 0x2f:
 444         case 0x34:
 445         case 0x35:
 446         case 0x36:
 447         case 0x37:
 448         case 0x40:
 449         case 0x41:
 450         case 0x42:
 451         case 0x43:
 452             can_write = 0;
 453             break;
 454         case 0x04:
 455         case 0x05:
 456         case 0x06:
 457         case 0x07:
 458         case 0x10:
 459         case 0x11:
 460         case 0x12:
 461         case 0x13:
 462         case 0x14:
 463         case 0x15:
 464         case 0x16:
 465         case 0x17:
 466         case 0x30:
 467         case 0x31:
 468         case 0x32:
 469         case 0x33:
 470         case 0x3c:
 471         case 0x3d:
 472         case 0x3e:
 473         case 0x3f:
 474         case 0x44:
 475         case 0x45:
 476         case 0x46:
 477         case 0x47:
 478             can_write = 1;
 479             break;
 480         default:
 481             /*reserved */
 482             can_write = 2;
 483             break;
 484         }
 485         if (can_write == 1)
 486         {
 487             d->config[addr] = (val & 0xff);
 488             if (addr == (0x14 + len - 1))
 489             {
 490                 /*write the last byte of mmio */
 491                 new_sm502_mm_io = le32_to_cpu(*(uint32_t *) (d->config + 0x14));
 492                 if (s->sm502_mm_io != new_sm502_mm_io)
 493                 {
 494                     /*remapped the Control register to CPU memory space */
 495                     iomemtype =
 496                         cpu_register_io_memory(0, sm502_readfn,
 497                                                sm502_writefn, s);
 498                     cpu_register_physical_memory(new_sm502_mm_io +
 499                                                  s->pci_mem_base, 0x200000,
 500                                                  iomemtype);
 501                     debug_out(DEBUG_MMIO,("new_sm502_mm_io %x pci_mem _base %llx\n",
 502                            new_sm502_mm_io, s->pci_mem_base));
 503                     if (s->sm502_mm_io != 0)
 504                         cpu_register_physical_memory(s->sm502_mm_io +
 505                                                      pci_mem_base, 0x200000,
 506                                                      IO_MEM_UNASSIGNED);
 507                     s->sm502_mm_io = new_sm502_mm_io;
 508                 }
 509             }
 510         }
 511         else if (can_write == 0)
 512         {
 513             fprintf(stderr,
 514                     "warnning. %s :write to read only pci conf register addr %x\n",
 515                     __FUNCTION__, addr);
 516         }
 517         else if (can_write == 2)
 518         {
 519             fprintf(stderr,
 520                     "warnning. %s :write to reserved pci conf register addr %x\n",
 521                     __FUNCTION__, addr);
 522         }
 523         if (++addr > 0xff)
 524             break;
 525         val >>= 8;
 526     }
 527 }
 528
 529 static void sm502_reset(struct sm502_s *s)
 530 {
 531     s->config[0] = 0x6F;
 532     s->config[1] = 0x12;
 533     s->config[2] = 0x01;
 534     s->config[3] = 0x05;
 535     s->config[6] = 0x30;
 536     s->config[7] = 0x02;
 537     s->config[10] = 0x30;
 538     s->config[11] = 0x02;
 539     s->config[0x34] = 0x40;
 540     s->config[0x40] = 0x01;
 541     s->config[0x42] = 0x01;
 542     s->config[0x43] = 0x06;
 543
 544     s->arb_control = 0x05146732;
 545     s->current_gate = 0x00021807;
 546     s->current_clock = 0x2a1a0a09;
 547     s->power0_gate = 0x00021807;
 548     s->power0_clock = 0x2a1a0a09;
 549     s->power1_gate = 0x00021807;
 550     s->power1_clock = 0x2a1a0a09;
 551     s->sleep_gate = 0x00018000;
 552     s->endian_control = 0x1;
 553     s->device_id = 0x050100a0;
 554     s->non_cache_address = 0x0000ffff;
 555     s->pll_control = 0x0000ffff;
 556
 557 }
 558
 559 struct sm502_s *sm502_init(PCIBus * bus, int devfn,
 560                            target_phys_addr_t pci_mem_base)
 561 {
 562     struct sm502_s *s = (struct sm502_s *) qemu_mallocz(sizeof(*s));
 563
 564     s = (struct sm502_s *) pci_register_device(bus, "SM502 PCI",
 565                                                sizeof(struct sm502_s), devfn,
 566                                                sm502_read_config,
 567                                                sm502_write_config);
 568     s->pci_mem_base = pci_mem_base;
 569
 570     sm502_gpio_init(s);
 571
 572     sm502_reset(s);
 573
 574     return s;
 575 }