target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "config.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #define CPUState struct CPUX86State
  46
  47 #include "cpu-defs.h"
  48
  49 #include "softfloat.h"
  50
  51 #define R_EAX 0
  52 #define R_ECX 1
  53 #define R_EDX 2
  54 #define R_EBX 3
  55 #define R_ESP 4
  56 #define R_EBP 5
  57 #define R_ESI 6
  58 #define R_EDI 7
  59
  60 #define R_AL 0
  61 #define R_CL 1
  62 #define R_DL 2
  63 #define R_BL 3
  64 #define R_AH 4
  65 #define R_CH 5
  66 #define R_DH 6
  67 #define R_BH 7
  68
  69 #define R_ES 0
  70 #define R_CS 1
  71 #define R_SS 2
  72 #define R_DS 3
  73 #define R_FS 4
  74 #define R_GS 5
  75
  76 /* segment descriptor fields */
  77 #define DESC_G_MASK     (1 << 23)
  78 #define DESC_B_SHIFT    22
  79 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  80 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  81 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  82 #define DESC_AVL_MASK   (1 << 20)
  83 #define DESC_P_MASK     (1 << 15)
  84 #define DESC_DPL_SHIFT  13
  85 #define DESC_DPL_MASK   (1 << DESC_DPL_SHIFT)
  86 #define DESC_S_MASK     (1 << 12)
  87 #define DESC_TYPE_SHIFT 8
  88 #define DESC_A_MASK     (1 << 8)
  89
  90 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  91 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  92 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  93
  94 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  95 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  96
  97 #define DESC_TSS_BUSY_MASK (1 << 9)
  98
  99 /* eflags masks */
 100 #define CC_C    0x0001
 101 #define CC_P    0x0004
 102 #define CC_A    0x0010
 103 #define CC_Z    0x0040
 104 #define CC_S    0x0080
 105 #define CC_O    0x0800
 106
 107 #define TF_SHIFT   8
 108 #define IOPL_SHIFT 12
 109 #define VM_SHIFT   17
 110
 111 #define TF_MASK                 0x00000100
 112 #define IF_MASK                 0x00000200
 113 #define DF_MASK                 0x00000400
 114 #define IOPL_MASK               0x00003000
 115 #define NT_MASK                 0x00004000
 116 #define RF_MASK                 0x00010000
 117 #define VM_MASK                 0x00020000
 118 #define AC_MASK                 0x00040000
 119 #define VIF_MASK                0x00080000
 120 #define VIP_MASK                0x00100000
 121 #define ID_MASK                 0x00200000
 122
 123 /* hidden flags - used internally by qemu to represent additional cpu
 124    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 125    redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
 126    position to ease oring with eflags. */
 127 /* current cpl */
 128 #define HF_CPL_SHIFT         0
 129 /* true if soft mmu is being used */
 130 #define HF_SOFTMMU_SHIFT     2
 131 /* true if hardware interrupts must be disabled for next instruction */
 132 #define HF_INHIBIT_IRQ_SHIFT 3
 133 /* 16 or 32 segments */
 134 #define HF_CS32_SHIFT        4
 135 #define HF_SS32_SHIFT        5
 136 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 137 #define HF_ADDSEG_SHIFT      6
 138 /* copy of CR0.PE (protected mode) */
 139 #define HF_PE_SHIFT          7
 140 #define HF_TF_SHIFT          8 /* must be same as eflags */
 141 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 142 #define HF_EM_SHIFT         10
 143 #define HF_TS_SHIFT         11
 144 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 145 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 146 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 147 #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 148 #define HF_VM_SHIFT         17 /* must be same as eflags */
 149 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 150 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 151 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 152
 153 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 154 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 155 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 156 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 157 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 158 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 159 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 160 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 161 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 162 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 163 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 164 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 165 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 166 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 167 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 168 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 169 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 170 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 171 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 172
 173 /* hflags2 */
 174
 175 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 176 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 177 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 178 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 179
 180 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 181 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 182 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 183 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 184
 185 #define CR0_PE_SHIFT 0
 186 #define CR0_MP_SHIFT 1
 187
 188 #define CR0_PE_MASK  (1 << 0)
 189 #define CR0_MP_MASK  (1 << 1)
 190 #define CR0_EM_MASK  (1 << 2)
 191 #define CR0_TS_MASK  (1 << 3)
 192 #define CR0_ET_MASK  (1 << 4)
 193 #define CR0_NE_MASK  (1 << 5)
 194 #define CR0_WP_MASK  (1 << 16)
 195 #define CR0_AM_MASK  (1 << 18)
 196 #define CR0_PG_MASK  (1 << 31)
 197
 198 #define CR4_VME_MASK  (1 << 0)
 199 #define CR4_PVI_MASK  (1 << 1)
 200 #define CR4_TSD_MASK  (1 << 2)
 201 #define CR4_DE_MASK   (1 << 3)
 202 #define CR4_PSE_MASK  (1 << 4)
 203 #define CR4_PAE_MASK  (1 << 5)
 204 #define CR4_PGE_MASK  (1 << 7)
 205 #define CR4_PCE_MASK  (1 << 8)
 206 #define CR4_OSFXSR_SHIFT 9
 207 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 208 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 209
 210 #define DR6_BD          (1 << 13)
 211 #define DR6_BS          (1 << 14)
 212 #define DR6_BT          (1 << 15)
 213 #define DR6_FIXED_1     0xffff0ff0
 214
 215 #define DR7_GD          (1 << 13)
 216 #define DR7_TYPE_SHIFT  16
 217 #define DR7_LEN_SHIFT   18
 218 #define DR7_FIXED_1     0x00000400
 219
 220 #define PG_PRESENT_BIT  0
 221 #define PG_RW_BIT       1
 222 #define PG_USER_BIT     2
 223 #define PG_PWT_BIT      3
 224 #define PG_PCD_BIT      4
 225 #define PG_ACCESSED_BIT 5
 226 #define PG_DIRTY_BIT    6
 227 #define PG_PSE_BIT      7
 228 #define PG_GLOBAL_BIT   8
 229 #define PG_NX_BIT       63
 230
 231 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 232 #define PG_RW_MASK       (1 << PG_RW_BIT)
 233 #define PG_USER_MASK     (1 << PG_USER_BIT)
 234 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 235 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 236 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 237 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 238 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 239 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 240 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 241
 242 #define PG_ERROR_W_BIT     1
 243
 244 #define PG_ERROR_P_MASK    0x01
 245 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 246 #define PG_ERROR_U_MASK    0x04
 247 #define PG_ERROR_RSVD_MASK 0x08
 248 #define PG_ERROR_I_D_MASK  0x10
 249
 250 #define MSR_IA32_TSC                    0x10
 251 #define MSR_IA32_APICBASE               0x1b
 252 #define MSR_IA32_APICBASE_BSP           (1<<8)
 253 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 254 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 255
 256 #define MSR_MTRRcap                     0xfe
 257 #define MSR_MTRRcap_VCNT                8
 258 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
 259 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
 260
 261 #define MSR_IA32_SYSENTER_CS            0x174
 262 #define MSR_IA32_SYSENTER_ESP           0x175
 263 #define MSR_IA32_SYSENTER_EIP           0x176
 264
 265 #define MSR_MCG_CAP                     0x179
 266 #define MSR_MCG_STATUS                  0x17a
 267 #define MSR_MCG_CTL                     0x17b
 268
 269 #define MSR_IA32_PERF_STATUS            0x198
 270
 271 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 272 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
 273
 274 #define MSR_MTRRfix64K_00000            0x250
 275 #define MSR_MTRRfix16K_80000            0x258
 276 #define MSR_MTRRfix16K_A0000            0x259
 277 #define MSR_MTRRfix4K_C0000             0x268
 278 #define MSR_MTRRfix4K_C8000             0x269
 279 #define MSR_MTRRfix4K_D0000             0x26a
 280 #define MSR_MTRRfix4K_D8000             0x26b
 281 #define MSR_MTRRfix4K_E0000             0x26c
 282 #define MSR_MTRRfix4K_E8000             0x26d
 283 #define MSR_MTRRfix4K_F0000             0x26e
 284 #define MSR_MTRRfix4K_F8000             0x26f
 285
 286 #define MSR_PAT                         0x277
 287
 288 #define MSR_MTRRdefType                 0x2ff
 289
 290 #define MSR_EFER                        0xc0000080
 291
 292 #define MSR_EFER_SCE   (1 << 0)
 293 #define MSR_EFER_LME   (1 << 8)
 294 #define MSR_EFER_LMA   (1 << 10)
 295 #define MSR_EFER_NXE   (1 << 11)
 296 #define MSR_EFER_SVME  (1 << 12)
 297 #define MSR_EFER_FFXSR (1 << 14)
 298
 299 #define MSR_STAR                        0xc0000081
 300 #define MSR_LSTAR                       0xc0000082
 301 #define MSR_CSTAR                       0xc0000083
 302 #define MSR_FMASK                       0xc0000084
 303 #define MSR_FSBASE                      0xc0000100
 304 #define MSR_GSBASE                      0xc0000101
 305 #define MSR_KERNELGSBASE                0xc0000102
 306
 307 #define MSR_VM_HSAVE_PA                 0xc0010117
 308
 309 /* cpuid_features bits */
 310 #define CPUID_FP87 (1 << 0)
 311 #define CPUID_VME  (1 << 1)
 312 #define CPUID_DE   (1 << 2)
 313 #define CPUID_PSE  (1 << 3)
 314 #define CPUID_TSC  (1 << 4)
 315 #define CPUID_MSR  (1 << 5)
 316 #define CPUID_PAE  (1 << 6)
 317 #define CPUID_MCE  (1 << 7)
 318 #define CPUID_CX8  (1 << 8)
 319 #define CPUID_APIC (1 << 9)
 320 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 321 #define CPUID_MTRR (1 << 12)
 322 #define CPUID_PGE  (1 << 13)
 323 #define CPUID_MCA  (1 << 14)
 324 #define CPUID_CMOV (1 << 15)
 325 #define CPUID_PAT  (1 << 16)
 326 #define CPUID_PSE36   (1 << 17)
 327 #define CPUID_PN   (1 << 18)
 328 #define CPUID_CLFLUSH (1 << 19)
 329 #define CPUID_DTS (1 << 21)
 330 #define CPUID_ACPI (1 << 22)
 331 #define CPUID_MMX  (1 << 23)
 332 #define CPUID_FXSR (1 << 24)
 333 #define CPUID_SSE  (1 << 25)
 334 #define CPUID_SSE2 (1 << 26)
 335 #define CPUID_SS (1 << 27)
 336 #define CPUID_HT (1 << 28)
 337 #define CPUID_TM (1 << 29)
 338 #define CPUID_IA64 (1 << 30)
 339 #define CPUID_PBE (1 << 31)
 340
 341 #define CPUID_EXT_SSE3     (1 << 0)
 342 #define CPUID_EXT_DTES64   (1 << 2)
 343 #define CPUID_EXT_MONITOR  (1 << 3)
 344 #define CPUID_EXT_DSCPL    (1 << 4)
 345 #define CPUID_EXT_VMX      (1 << 5)
 346 #define CPUID_EXT_SMX      (1 << 6)
 347 #define CPUID_EXT_EST      (1 << 7)
 348 #define CPUID_EXT_TM2      (1 << 8)
 349 #define CPUID_EXT_SSSE3    (1 << 9)
 350 #define CPUID_EXT_CID      (1 << 10)
 351 #define CPUID_EXT_CX16     (1 << 13)
 352 #define CPUID_EXT_XTPR     (1 << 14)
 353 #define CPUID_EXT_PDCM     (1 << 15)
 354 #define CPUID_EXT_DCA      (1 << 18)
 355 #define CPUID_EXT_SSE41    (1 << 19)
 356 #define CPUID_EXT_SSE42    (1 << 20)
 357 #define CPUID_EXT_X2APIC   (1 << 21)
 358 #define CPUID_EXT_MOVBE    (1 << 22)
 359 #define CPUID_EXT_POPCNT   (1 << 23)
 360 #define CPUID_EXT_XSAVE    (1 << 26)
 361 #define CPUID_EXT_OSXSAVE  (1 << 27)
 362
 363 #define CPUID_EXT2_SYSCALL (1 << 11)
 364 #define CPUID_EXT2_MP      (1 << 19)
 365 #define CPUID_EXT2_NX      (1 << 20)
 366 #define CPUID_EXT2_MMXEXT  (1 << 22)
 367 #define CPUID_EXT2_FFXSR   (1 << 25)
 368 #define CPUID_EXT2_PDPE1GB (1 << 26)
 369 #define CPUID_EXT2_RDTSCP  (1 << 27)
 370 #define CPUID_EXT2_LM      (1 << 29)
 371 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 372 #define CPUID_EXT2_3DNOW   (1 << 31)
 373
 374 #define CPUID_EXT3_LAHF_LM (1 << 0)
 375 #define CPUID_EXT3_CMP_LEG (1 << 1)
 376 #define CPUID_EXT3_SVM     (1 << 2)
 377 #define CPUID_EXT3_EXTAPIC (1 << 3)
 378 #define CPUID_EXT3_CR8LEG  (1 << 4)
 379 #define CPUID_EXT3_ABM     (1 << 5)
 380 #define CPUID_EXT3_SSE4A   (1 << 6)
 381 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 382 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 383 #define CPUID_EXT3_OSVW    (1 << 9)
 384 #define CPUID_EXT3_IBS     (1 << 10)
 385 #define CPUID_EXT3_SKINIT  (1 << 12)
 386
 387 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 388 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 389 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 390
 391 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 392 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 393 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 394
 395 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 396 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 397
 398 #define EXCP00_DIVZ     0
 399 #define EXCP01_DB       1
 400 #define EXCP02_NMI      2
 401 #define EXCP03_INT3     3
 402 #define EXCP04_INTO     4
 403 #define EXCP05_BOUND    5
 404 #define EXCP06_ILLOP    6
 405 #define EXCP07_PREX     7
 406 #define EXCP08_DBLE     8
 407 #define EXCP09_XERR     9
 408 #define EXCP0A_TSS      10
 409 #define EXCP0B_NOSEG    11
 410 #define EXCP0C_STACK    12
 411 #define EXCP0D_GPF      13
 412 #define EXCP0E_PAGE     14
 413 #define EXCP10_COPR     16
 414 #define EXCP11_ALGN     17
 415 #define EXCP12_MCHK     18
 416
 417 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 418                                  for syscall instruction */
 419
 420 enum {
 421     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 422     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 423
 424     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 425     CC_OP_MULW,
 426     CC_OP_MULL,
 427     CC_OP_MULQ,
 428
 429     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 430     CC_OP_ADDW,
 431     CC_OP_ADDL,
 432     CC_OP_ADDQ,
 433
 434     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 435     CC_OP_ADCW,
 436     CC_OP_ADCL,
 437     CC_OP_ADCQ,
 438
 439     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 440     CC_OP_SUBW,
 441     CC_OP_SUBL,
 442     CC_OP_SUBQ,
 443
 444     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 445     CC_OP_SBBW,
 446     CC_OP_SBBL,
 447     CC_OP_SBBQ,
 448
 449     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 450     CC_OP_LOGICW,
 451     CC_OP_LOGICL,
 452     CC_OP_LOGICQ,
 453
 454     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 455     CC_OP_INCW,
 456     CC_OP_INCL,
 457     CC_OP_INCQ,
 458
 459     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 460     CC_OP_DECW,
 461     CC_OP_DECL,
 462     CC_OP_DECQ,
 463
 464     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 465     CC_OP_SHLW,
 466     CC_OP_SHLL,
 467     CC_OP_SHLQ,
 468
 469     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 470     CC_OP_SARW,
 471     CC_OP_SARL,
 472     CC_OP_SARQ,
 473
 474     CC_OP_NB,
 475 };
 476
 477 #ifdef FLOATX80
 478 #define USE_X86LDOUBLE
 479 #endif
 480
 481 #ifdef USE_X86LDOUBLE
 482 typedef floatx80 CPU86_LDouble;
 483 #else
 484 typedef float64 CPU86_LDouble;
 485 #endif
 486
 487 typedef struct SegmentCache {
 488     uint32_t selector;
 489     target_ulong base;
 490     uint32_t limit;
 491     uint32_t flags;
 492 } SegmentCache;
 493
 494 typedef union {
 495     uint8_t _b[16];
 496     uint16_t _w[8];
 497     uint32_t _l[4];
 498     uint64_t _q[2];
 499     float32 _s[4];
 500     float64 _d[2];
 501 } XMMReg;
 502
 503 typedef union {
 504     uint8_t _b[8];
 505     uint16_t _w[4];
 506     uint32_t _l[2];
 507     float32 _s[2];
 508     uint64_t q;
 509 } MMXReg;
 510
 511 #ifdef WORDS_BIGENDIAN
 512 #define XMM_B(n) _b[15 - (n)]
 513 #define XMM_W(n) _w[7 - (n)]
 514 #define XMM_L(n) _l[3 - (n)]
 515 #define XMM_S(n) _s[3 - (n)]
 516 #define XMM_Q(n) _q[1 - (n)]
 517 #define XMM_D(n) _d[1 - (n)]
 518
 519 #define MMX_B(n) _b[7 - (n)]
 520 #define MMX_W(n) _w[3 - (n)]
 521 #define MMX_L(n) _l[1 - (n)]
 522 #define MMX_S(n) _s[1 - (n)]
 523 #else
 524 #define XMM_B(n) _b[n]
 525 #define XMM_W(n) _w[n]
 526 #define XMM_L(n) _l[n]
 527 #define XMM_S(n) _s[n]
 528 #define XMM_Q(n) _q[n]
 529 #define XMM_D(n) _d[n]
 530
 531 #define MMX_B(n) _b[n]
 532 #define MMX_W(n) _w[n]
 533 #define MMX_L(n) _l[n]
 534 #define MMX_S(n) _s[n]
 535 #endif
 536 #define MMX_Q(n) q
 537
 538 #ifdef TARGET_X86_64
 539 #define CPU_NB_REGS 16
 540 #else
 541 #define CPU_NB_REGS 8
 542 #endif
 543
 544 #define NB_MMU_MODES 2
 545
 546 typedef struct CPUX86State {
 547     /* standard registers */
 548     target_ulong regs[CPU_NB_REGS];
 549     target_ulong eip;
 550     target_ulong eflags; /* eflags register. During CPU emulation, CC
 551                         flags and DF are set to zero because they are
 552                         stored elsewhere */
 553
 554     /* emulator internal eflags handling */
 555     target_ulong cc_src;
 556     target_ulong cc_dst;
 557     uint32_t cc_op;
 558     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 559     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 560                         are known at translation time. */
 561     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 562
 563     /* segments */
 564     SegmentCache segs[6]; /* selector values */
 565     SegmentCache ldt;
 566     SegmentCache tr;
 567     SegmentCache gdt; /* only base and limit are used */
 568     SegmentCache idt; /* only base and limit are used */
 569
 570     target_ulong cr[5]; /* NOTE: cr1 is unused */
 571     uint64_t a20_mask;
 572
 573     /* FPU state */
 574     unsigned int fpstt; /* top of stack index */
 575     unsigned int fpus;
 576     unsigned int fpuc;
 577     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 578     union {
 579 #ifdef USE_X86LDOUBLE
 580         CPU86_LDouble d __attribute__((aligned(16)));
 581 #else
 582         CPU86_LDouble d;
 583 #endif
 584         MMXReg mmx;
 585     } fpregs[8];
 586
 587     /* emulator internal variables */
 588     float_status fp_status;
 589     CPU86_LDouble ft0;
 590
 591     float_status mmx_status; /* for 3DNow! float ops */
 592     float_status sse_status;
 593     uint32_t mxcsr;
 594     XMMReg xmm_regs[CPU_NB_REGS];
 595     XMMReg xmm_t0;
 596     MMXReg mmx_t0;
 597     target_ulong cc_tmp; /* temporary for rcr/rcl */
 598
 599     /* sysenter registers */
 600     uint32_t sysenter_cs;
 601     target_ulong sysenter_esp;
 602     target_ulong sysenter_eip;
 603     uint64_t efer;
 604     uint64_t star;
 605
 606     uint64_t vm_hsave;
 607     uint64_t vm_vmcb;
 608     uint64_t tsc_offset;
 609     uint64_t intercept;
 610     uint16_t intercept_cr_read;
 611     uint16_t intercept_cr_write;
 612     uint16_t intercept_dr_read;
 613     uint16_t intercept_dr_write;
 614     uint32_t intercept_exceptions;
 615     uint8_t v_tpr;
 616
 617 #ifdef TARGET_X86_64
 618     target_ulong lstar;
 619     target_ulong cstar;
 620     target_ulong fmask;
 621     target_ulong kernelgsbase;
 622 #endif
 623
 624     uint64_t tsc;
 625
 626     uint64_t pat;
 627
 628     /* exception/interrupt handling */
 629     int error_code;
 630     int exception_is_int;
 631     target_ulong exception_next_eip;
 632     target_ulong dr[8]; /* debug registers */
 633     union {
 634         CPUBreakpoint *cpu_breakpoint[4];
 635         CPUWatchpoint *cpu_watchpoint[4];
 636     }; /* break/watchpoints for dr[0..3] */
 637     uint32_t smbase;
 638     int old_exception;  /* exception in flight */
 639
 640     CPU_COMMON
 641
 642     /* processor features (e.g. for CPUID insn) */
 643     uint32_t cpuid_level;
 644     uint32_t cpuid_vendor1;
 645     uint32_t cpuid_vendor2;
 646     uint32_t cpuid_vendor3;
 647     uint32_t cpuid_version;
 648     uint32_t cpuid_features;
 649     uint32_t cpuid_ext_features;
 650     uint32_t cpuid_xlevel;
 651     uint32_t cpuid_model[12];
 652     uint32_t cpuid_ext2_features;
 653     uint32_t cpuid_ext3_features;
 654     uint32_t cpuid_apic_id;
 655
 656     /* MTRRs */
 657     uint64_t mtrr_fixed[11];
 658     uint64_t mtrr_deftype;
 659     struct {
 660         uint64_t base;
 661         uint64_t mask;
 662     } mtrr_var[8];
 663
 664 #ifdef USE_KQEMU
 665     int kqemu_enabled;
 666     int last_io_time;
 667 #endif
 668
 669     /* For KVM */
 670     uint64_t interrupt_bitmap[256 / 64];
 671
 672     /* in order to simplify APIC support, we leave this pointer to the
 673        user */
 674     struct APICState *apic_state;
 675 } CPUX86State;
 676
 677 CPUX86State *cpu_x86_init(const char *cpu_model);
 678 int cpu_x86_exec(CPUX86State *s);
 679 void cpu_x86_close(CPUX86State *s);
 680 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 681                                                  ...));
 682 int cpu_get_pic_interrupt(CPUX86State *s);
 683 /* MSDOS compatibility mode FPU exception support */
 684 void cpu_set_ferr(CPUX86State *s);
 685
 686 /* this function must always be used to load data in the segment
 687    cache: it synchronizes the hflags with the segment cache values */
 688 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 689                                           int seg_reg, unsigned int selector,
 690                                           target_ulong base,
 691                                           unsigned int limit,
 692                                           unsigned int flags)
 693 {
 694     SegmentCache *sc;
 695     unsigned int new_hflags;
 696
 697     sc = &env->segs[seg_reg];
 698     sc->selector = selector;
 699     sc->base = base;
 700     sc->limit = limit;
 701     sc->flags = flags;
 702
 703     /* update the hidden flags */
 704     {
 705         if (seg_reg == R_CS) {
 706 #ifdef TARGET_X86_64
 707             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 708                 /* long mode */
 709                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 710                 env->hflags &= ~(HF_ADDSEG_MASK);
 711             } else
 712 #endif
 713             {
 714                 /* legacy / compatibility case */
 715                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 716                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 717                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 718                     new_hflags;
 719             }
 720         }
 721         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 722             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 723         if (env->hflags & HF_CS64_MASK) {
 724             /* zero base assumed for DS, ES and SS in long mode */
 725         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 726                    (env->eflags & VM_MASK) ||
 727                    !(env->hflags & HF_CS32_MASK)) {
 728             /* XXX: try to avoid this test. The problem comes from the
 729                fact that is real mode or vm86 mode we only modify the
 730                'base' and 'selector' fields of the segment cache to go
 731                faster. A solution may be to force addseg to one in
 732                translate-i386.c. */
 733             new_hflags |= HF_ADDSEG_MASK;
 734         } else {
 735             new_hflags |= ((env->segs[R_DS].base |
 736                             env->segs[R_ES].base |
 737                             env->segs[R_SS].base) != 0) <<
 738                 HF_ADDSEG_SHIFT;
 739         }
 740         env->hflags = (env->hflags &
 741                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 742     }
 743 }
 744
 745 /* wrapper, just in case memory mappings must be changed */
 746 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 747 {
 748 #if HF_CPL_MASK == 3
 749     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 750 #else
 751 #error HF_CPL_MASK is hardcoded
 752 #endif
 753 }
 754
 755 /* op_helper.c */
 756 /* used for debug or cpu save/restore */
 757 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 758 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 759
 760 /* cpu-exec.c */
 761 /* the following helpers are only usable in user mode simulation as
 762    they can trigger unexpected exceptions */
 763 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 764 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
 765 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
 766
 767 /* you can call this signal handler from your SIGBUS and SIGSEGV
 768    signal handlers to inform the virtual CPU of exceptions. non zero
 769    is returned if the signal was handled by the virtual CPU.  */
 770 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 771                            void *puc);
 772
 773 /* helper.c */
 774 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
 775                              int is_write, int mmu_idx, int is_softmmu);
 776 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 777 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
 778                    uint32_t *eax, uint32_t *ebx,
 779                    uint32_t *ecx, uint32_t *edx);
 780
 781 static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
 782 {
 783     return (dr7 >> (index * 2)) & 3;
 784 }
 785
 786 static inline int hw_breakpoint_type(unsigned long dr7, int index)
 787 {
 788     return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3;
 789 }
 790
 791 static inline int hw_breakpoint_len(unsigned long dr7, int index)
 792 {
 793     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3);
 794     return (len == 2) ? 8 : len + 1;
 795 }
 796
 797 void hw_breakpoint_insert(CPUX86State *env, int index);
 798 void hw_breakpoint_remove(CPUX86State *env, int index);
 799 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
 800
 801 /* will be suppressed */
 802 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 803 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
 804 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
 805
 806 /* hw/apic.c */
 807 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 808 uint64_t cpu_get_apic_base(CPUX86State *env);
 809 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 810 #ifndef NO_CPU_IO_DEFS
 811 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 812 #endif
 813
 814 /* hw/pc.c */
 815 void cpu_smm_update(CPUX86State *env);
 816 uint64_t cpu_get_tsc(CPUX86State *env);
 817
 818 /* used to debug */
 819 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 820 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 821
 822 #ifdef USE_KQEMU
 823 static inline int cpu_get_time_fast(void)
 824 {
 825     int low, high;
 826     asm volatile("rdtsc" : "=a" (low), "=d" (high));
 827     return low;
 828 }
 829 #endif
 830
 831 #define TARGET_PAGE_BITS 12
 832
 833 #define cpu_init cpu_x86_init
 834 #define cpu_exec cpu_x86_exec
 835 #define cpu_gen_code cpu_x86_gen_code
 836 #define cpu_signal_handler cpu_x86_signal_handler
 837 #define cpu_list x86_cpu_list
 838
 839 #define CPU_SAVE_VERSION 8
 840
 841 /* MMU modes definitions */
 842 #define MMU_MODE0_SUFFIX _kernel
 843 #define MMU_MODE1_SUFFIX _user
 844 #define MMU_USER_IDX 1
 845 static inline int cpu_mmu_index (CPUState *env)
 846 {
 847     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
 848 }
 849
 850 /* translate.c */
 851 void optimize_flags_init(void);
 852
 853 typedef struct CCTable {
 854     int (*compute_all)(void); /* return all the flags */
 855     int (*compute_c)(void);  /* return the C flag */
 856 } CCTable;
 857
 858 #if defined(CONFIG_USER_ONLY)
 859 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 860 {
 861     if (newsp)
 862         env->regs[R_ESP] = newsp;
 863     env->regs[R_EAX] = 0;
 864 }
 865 #endif
 866
 867 #include "cpu-all.h"
 868 #include "exec-all.h"
 869
 870 #include "svm.h"
 871
 872 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 873 {
 874     env->eip = tb->pc - tb->cs_base;
 875 }
 876
 877 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 878                                         target_ulong *cs_base, int *flags)
 879 {
 880     *cs_base = env->segs[R_CS].base;
 881     *pc = *cs_base + env->eip;
 882     *flags = env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
 883 }
 884
 885 #endif /* CPU_I386_H */