hw/grackle_pci.c

   1 /*
   2  * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
   3  *
   4  * Copyright (c) 2006-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "ppc_mac.h"
  28 #include "pci.h"
  29
  30 /* debug Grackle */
  31 //#define DEBUG_GRACKLE
  32
  33 #ifdef DEBUG_GRACKLE
  34 #define GRACKLE_DPRINTF(fmt, args...) \
  35 do { printf("GRACKLE: " fmt , ##args); } while (0)
  36 #else
  37 #define GRACKLE_DPRINTF(fmt, args...)
  38 #endif
  39
  40 typedef target_phys_addr_t pci_addr_t;
  41 #include "pci_host.h"
  42
  43 typedef PCIHostState GrackleState;
  44
  45 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
  46                                        uint32_t val)
  47 {
  48     GrackleState *s = opaque;
  49
  50     GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
  51                     val);
  52 #ifdef TARGET_WORDS_BIGENDIAN
  53     val = bswap32(val);
  54 #endif
  55     s->config_reg = val;
  56 }
  57
  58 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
  59 {
  60     GrackleState *s = opaque;
  61     uint32_t val;
  62
  63     val = s->config_reg;
  64 #ifdef TARGET_WORDS_BIGENDIAN
  65     val = bswap32(val);
  66 #endif
  67     GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
  68                     val);
  69     return val;
  70 }
  71
  72 static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
  73     &pci_grackle_config_writel,
  74     &pci_grackle_config_writel,
  75     &pci_grackle_config_writel,
  76 };
  77
  78 static CPUReadMemoryFunc *pci_grackle_config_read[] = {
  79     &pci_grackle_config_readl,
  80     &pci_grackle_config_readl,
  81     &pci_grackle_config_readl,
  82 };
  83
  84 static CPUWriteMemoryFunc *pci_grackle_write[] = {
  85     &pci_host_data_writeb,
  86     &pci_host_data_writew,
  87     &pci_host_data_writel,
  88 };
  89
  90 static CPUReadMemoryFunc *pci_grackle_read[] = {
  91     &pci_host_data_readb,
  92     &pci_host_data_readw,
  93     &pci_host_data_readl,
  94 };
  95
  96 /* Don't know if this matches real hardware, but it agrees with OHW.  */
  97 static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
  98 {
  99     return (irq_num + (pci_dev->devfn >> 3)) & 3;
 100 }
 101
 102 static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
 103 {
 104     GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
 105     qemu_set_irq(pic[irq_num + 0x15], level);
 106 }
 107
 108 static void pci_grackle_save(QEMUFile* f, void *opaque)
 109 {
 110     PCIDevice *d = opaque;
 111
 112     pci_device_save(d, f);
 113 }
 114
 115 static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id)
 116 {
 117     PCIDevice *d = opaque;
 118
 119     if (version_id != 1)
 120         return -EINVAL;
 121
 122     return pci_device_load(d, f);
 123 }
 124
 125 static void pci_grackle_reset(void *opaque)
 126 {
 127 }
 128
 129 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
 130 {
 131     GrackleState *s;
 132     PCIDevice *d;
 133     int pci_mem_config, pci_mem_data;
 134
 135     s = qemu_mallocz(sizeof(GrackleState));
 136     s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq,
 137                               pic, 0, 4);
 138
 139     pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
 140                                             pci_grackle_config_write, s);
 141     pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
 142                                           pci_grackle_write, s);
 143     cpu_register_physical_memory(base, 0x1000, pci_mem_config);
 144     cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
 145     d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
 146                             0, NULL, NULL);
 147     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 148     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
 149     d->config[0x08] = 0x00; // revision
 150     d->config[0x09] = 0x01;
 151     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 152     d->config[0x0e] = 0x00; // header_type
 153
 154 #if 0
 155     /* PCI2PCI bridge same values as PearPC - check this */
 156     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
 157     pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
 158     d->config[0x08] = 0x02; // revision
 159     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
 160     d->config[0x0e] = 0x01; // header_type
 161
 162     d->config[0x18] = 0x0;  // primary_bus
 163     d->config[0x19] = 0x1;  // secondary_bus
 164     d->config[0x1a] = 0x1;  // subordinate_bus
 165     d->config[0x1c] = 0x10; // io_base
 166     d->config[0x1d] = 0x20; // io_limit
 167
 168     d->config[0x20] = 0x80; // memory_base
 169     d->config[0x21] = 0x80;
 170     d->config[0x22] = 0x90; // memory_limit
 171     d->config[0x23] = 0x80;
 172
 173     d->config[0x24] = 0x00; // prefetchable_memory_base
 174     d->config[0x25] = 0x84;
 175     d->config[0x26] = 0x00; // prefetchable_memory_limit
 176     d->config[0x27] = 0x85;
 177 #endif
 178     register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
 179     qemu_register_reset(pci_grackle_reset, d);
 180     pci_grackle_reset(d);
 181
 182     return s->bus;
 183 }