hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 struct kvm_irq_routing_entry;
  10
  11 /* PCI includes legacy ISA access.  */
  12 #include "isa.h"
  13
  14 #include "pcie.h"
  15
  16 /* PCI bus */
  17
  18 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67
  68 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  69 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  70 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  71 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  72
  73 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  74 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  75 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  76 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  77
  78 #define FMT_PCIBUS                      PRIx64
  79
  80 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  81                                 uint32_t address, uint32_t data, int len);
  82 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  83                                    uint32_t address, int len);
  84 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  85                                 pcibus_t addr, pcibus_t size, int type);
  86 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  87
  88 typedef struct PCIIORegion {
  89     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  90 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  91     pcibus_t size;
  92     pcibus_t filtered_size;
  93     uint8_t type;
  94     PCIMapIORegionFunc *map_func;
  95 } PCIIORegion;
  96
  97 #define PCI_ROM_SLOT 6
  98 #define PCI_NUM_REGIONS 7
  99
 100 #include "pci_regs.h"
 101
 102 /* PCI HEADER_TYPE */
 103 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 104
 105 /* Size of the standard PCI config header */
 106 #define PCI_CONFIG_HEADER_SIZE 0x40
 107 /* Size of the standard PCI config space */
 108 #define PCI_CONFIG_SPACE_SIZE 0x100
 109 /* Size of the standart PCIe config space: 4KB */
 110 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 111
 112 #define PCI_NUM_PINS 4 /* A-D */
 113
 114 /* Bits in cap_present field. */
 115 enum {
 116     QEMU_PCI_CAP_MSI = 0x1,
 117     QEMU_PCI_CAP_MSIX = 0x2,
 118     QEMU_PCI_CAP_EXPRESS = 0x4,
 119
 120     /* multifunction capable device */
 121 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 122     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 123 };
 124
 125 #define PCI_CAPABILITY_CONFIG_MAX_LENGTH 0x60
 126 #define PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR 0x40
 127 #define PCI_CAPABILITY_CONFIG_MSI_LENGTH 0x10
 128 #define PCI_CAPABILITY_CONFIG_MSIX_LENGTH 0x10
 129
 130 typedef int (*msix_mask_notifier_func)(PCIDevice *, unsigned vector,
 131                                        int masked);
 132
 133 struct kvm_msix_message {
 134     uint32_t gsi;
 135     uint32_t addr_lo;
 136     uint32_t addr_hi;
 137     uint32_t data;
 138 };
 139
 140 struct PCIDevice {
 141     DeviceState qdev;
 142     /* PCI config space */
 143     uint8_t *config;
 144
 145     /* Used to enable config checks on load. Note that writeable bits are
 146      * never checked even if set in cmask. */
 147     uint8_t *cmask;
 148
 149     /* Used to implement R/W bytes */
 150     uint8_t *wmask;
 151
 152     /* Used to implement RW1C(Write 1 to Clear) bytes */
 153     uint8_t *w1cmask;
 154
 155     /* Used to allocate config space and track capabilities. */
 156     uint8_t *config_map;
 157
 158     /* the following fields are read only */
 159     PCIBus *bus;
 160     uint32_t devfn;
 161     char name[64];
 162     PCIIORegion io_regions[PCI_NUM_REGIONS];
 163
 164     /* do not access the following fields */
 165     PCIConfigReadFunc *config_read;
 166     PCIConfigWriteFunc *config_write;
 167
 168     /* IRQ objects for the INTA-INTD pins.  */
 169     qemu_irq *irq;
 170
 171     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 172     uint8_t irq_state;
 173
 174     /* Capability bits */
 175     uint32_t cap_present;
 176
 177     /* Offset of MSI-X capability in config space */
 178     uint8_t msix_cap;
 179
 180     /* MSI-X entries */
 181     int msix_entries_nr;
 182
 183     /* Space to store MSIX table */
 184     uint8_t *msix_table_page;
 185     /* MMIO index used to map MSIX table and pending bit entries. */
 186     int msix_mmio_index;
 187     /* Reference-count for entries actually in use by driver. */
 188     unsigned *msix_entry_used;
 189     /* Region including the MSI-X table */
 190     uint32_t msix_bar_size;
 191     /* Version id needed for VMState */
 192     int32_t version_id;
 193
 194     /* Offset of MSI capability in config space */
 195     uint8_t msi_cap;
 196
 197     /* PCI Express */
 198     PCIExpressDevice exp;
 199
 200     /* Location of option rom */
 201     char *romfile;
 202     ram_addr_t rom_offset;
 203     uint32_t rom_bar;
 204
 205     /* How much space does an MSIX table need. */
 206     /* The spec requires giving the table structure
 207      * a 4K aligned region all by itself. Align it to
 208      * target pages so that drivers can do passthrough
 209      * on the rest of the region. */
 210     target_phys_addr_t msix_page_size;
 211
 212     struct kvm_msix_message *msix_irq_entries;
 213
 214     msix_mask_notifier_func msix_mask_notifier;
 215 };
 216
 217 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 218                                int instance_size, int devfn,
 219                                PCIConfigReadFunc *config_read,
 220                                PCIConfigWriteFunc *config_write);
 221
 222 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 223                             pcibus_t size, uint8_t type,
 224                             PCIMapIORegionFunc *map_func);
 225
 226 void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr,
 227                         pcibus_t size, int type);
 228
 229 int pci_map_irq(PCIDevice *pci_dev, int pin);
 230
 231 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 232                        uint8_t offset, uint8_t size);
 233
 234 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 235
 236 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 237
 238 uint32_t pci_default_read_config(PCIDevice *d,
 239                                  uint32_t address, int len);
 240 void pci_default_write_config(PCIDevice *d,
 241                               uint32_t address, uint32_t val, int len);
 242 void pci_device_save(PCIDevice *s, QEMUFile *f);
 243 int pci_device_load(PCIDevice *s, QEMUFile *f);
 244 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 245 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 246 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
 247 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 248                          const char *name, int devfn_min);
 249 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 250 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 251                   void *irq_opaque, int nirq);
 252 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 253 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 254                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 255                          void *irq_opaque, int devfn_min, int nirq);
 256
 257 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 258
 259 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 260                         const char *default_devaddr);
 261 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 262                                const char *default_devaddr);
 263 int pci_bus_num(PCIBus *s);
 264 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 265 PCIBus *pci_find_root_bus(int domain);
 266 int pci_find_domain(const PCIBus *bus);
 267 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 268 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 269 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 270
 271 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 272                       unsigned int *slotp, unsigned int *funcp);
 273 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 274                      unsigned *slotp);
 275
 276 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
 277                            int *slotp, int *funcp);
 278
 279 void do_pci_info_print(Monitor *mon, const QObject *data);
 280 void do_pci_info(Monitor *mon, QObject **ret_data);
 281 void pci_bridge_update_mappings(PCIBus *b);
 282
 283 bool pci_msi_enabled(PCIDevice *dev);
 284 void pci_msi_notify(PCIDevice *dev, unsigned int vector);
 285
 286 static inline void
 287 pci_set_byte(uint8_t *config, uint8_t val)
 288 {
 289     *config = val;
 290 }
 291
 292 static inline uint8_t
 293 pci_get_byte(const uint8_t *config)
 294 {
 295     return *config;
 296 }
 297
 298 static inline void
 299 pci_set_word(uint8_t *config, uint16_t val)
 300 {
 301     cpu_to_le16wu((uint16_t *)config, val);
 302 }
 303
 304 static inline uint16_t
 305 pci_get_word(const uint8_t *config)
 306 {
 307     return le16_to_cpupu((const uint16_t *)config);
 308 }
 309
 310 static inline void
 311 pci_set_long(uint8_t *config, uint32_t val)
 312 {
 313     cpu_to_le32wu((uint32_t *)config, val);
 314 }
 315
 316 static inline uint32_t
 317 pci_get_long(const uint8_t *config)
 318 {
 319     return le32_to_cpupu((const uint32_t *)config);
 320 }
 321
 322 static inline void
 323 pci_set_quad(uint8_t *config, uint64_t val)
 324 {
 325     cpu_to_le64w((uint64_t *)config, val);
 326 }
 327
 328 static inline uint64_t
 329 pci_get_quad(const uint8_t *config)
 330 {
 331     return le64_to_cpup((const uint64_t *)config);
 332 }
 333
 334 static inline void
 335 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 336 {
 337     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 338 }
 339
 340 static inline void
 341 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 342 {
 343     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 344 }
 345
 346 static inline void
 347 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 348 {
 349     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 350 }
 351
 352 static inline void
 353 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 354 {
 355     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 356 }
 357
 358 static inline void
 359 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 360 {
 361     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 362 }
 363
 364 static inline void
 365 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 366 {
 367     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 368 }
 369
 370 /*
 371  * helper functions to do bit mask operation on configuration space.
 372  * Just to set bit, use test-and-set and discard returned value.
 373  * Just to clear bit, use test-and-clear and discard returned value.
 374  * NOTE: They aren't atomic.
 375  */
 376 static inline uint8_t
 377 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 378 {
 379     uint8_t val = pci_get_byte(config);
 380     pci_set_byte(config, val & ~mask);
 381     return val & mask;
 382 }
 383
 384 static inline uint8_t
 385 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 386 {
 387     uint8_t val = pci_get_byte(config);
 388     pci_set_byte(config, val | mask);
 389     return val & mask;
 390 }
 391
 392 static inline uint16_t
 393 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 394 {
 395     uint16_t val = pci_get_word(config);
 396     pci_set_word(config, val & ~mask);
 397     return val & mask;
 398 }
 399
 400 static inline uint16_t
 401 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 402 {
 403     uint16_t val = pci_get_word(config);
 404     pci_set_word(config, val | mask);
 405     return val & mask;
 406 }
 407
 408 static inline uint32_t
 409 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 410 {
 411     uint32_t val = pci_get_long(config);
 412     pci_set_long(config, val & ~mask);
 413     return val & mask;
 414 }
 415
 416 static inline uint32_t
 417 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 418 {
 419     uint32_t val = pci_get_long(config);
 420     pci_set_long(config, val | mask);
 421     return val & mask;
 422 }
 423
 424 static inline uint64_t
 425 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 426 {
 427     uint64_t val = pci_get_quad(config);
 428     pci_set_quad(config, val & ~mask);
 429     return val & mask;
 430 }
 431
 432 static inline uint64_t
 433 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 434 {
 435     uint64_t val = pci_get_quad(config);
 436     pci_set_quad(config, val | mask);
 437     return val & mask;
 438 }
 439
 440 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 441 typedef struct {
 442     DeviceInfo qdev;
 443     pci_qdev_initfn init;
 444     PCIUnregisterFunc *exit;
 445     PCIConfigReadFunc *config_read;
 446     PCIConfigWriteFunc *config_write;
 447
 448     /*
 449      * pci-to-pci bridge or normal device.
 450      * This doesn't mean pci host switch.
 451      * When card bus bridge is supported, this would be enhanced.
 452      */
 453     int is_bridge;
 454
 455     /* pcie stuff */
 456     int is_express;   /* is this device pci express? */
 457
 458     /* rom bar */
 459     const char *romfile;
 460 } PCIDeviceInfo;
 461
 462 void pci_qdev_register(PCIDeviceInfo *info);
 463 void pci_qdev_register_many(PCIDeviceInfo *info);
 464
 465 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 466                                     const char *name);
 467 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 468                                            bool multifunction,
 469                                            const char *name);
 470 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 471 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 472
 473 static inline int pci_is_express(const PCIDevice *d)
 474 {
 475     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 476 }
 477
 478 static inline uint32_t pci_config_size(const PCIDevice *d)
 479 {
 480     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 481 }
 482
 483 #endif