hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "sysemu.h"
  26 #include "apic.h"
  27 #include "ioapic.h"
  28 #include "qemu-timer.h"
  29 #include "host-utils.h"
  30 #include "sysbus.h"
  31
  32 #include "kvm.h"
  33
  34 //#define DEBUG_IOAPIC
  35
  36 #ifdef DEBUG_IOAPIC
  37 #define DPRINTF(fmt, ...)                                       \
  38     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...)
  41 #endif
  42
  43 #define MAX_IOAPICS                     1
  44
  45 #define IOAPIC_VERSION                  0x11
  46
  47 #define IOAPIC_LVT_DEST_SHIFT           56
  48 #define IOAPIC_LVT_MASKED_SHIFT         16
  49 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT   15
  50 #define IOAPIC_LVT_REMOTE_IRR_SHIFT     14
  51 #define IOAPIC_LVT_POLARITY_SHIFT       13
  52 #define IOAPIC_LVT_DELIV_STATUS_SHIFT   12
  53 #define IOAPIC_LVT_DEST_MODE_SHIFT      11
  54 #define IOAPIC_LVT_DELIV_MODE_SHIFT     8
  55
  56 #define IOAPIC_LVT_MASKED               (1 << IOAPIC_LVT_MASKED_SHIFT)
  57 #define IOAPIC_LVT_REMOTE_IRR           (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
  58
  59 #define IOAPIC_TRIGGER_EDGE             0
  60 #define IOAPIC_TRIGGER_LEVEL            1
  61
  62 /*io{apic,sapic} delivery mode*/
  63 #define IOAPIC_DM_FIXED                 0x0
  64 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  65 #define IOAPIC_DM_PMI                   0x2
  66 #define IOAPIC_DM_NMI                   0x4
  67 #define IOAPIC_DM_INIT                  0x5
  68 #define IOAPIC_DM_SIPI                  0x6
  69 #define IOAPIC_DM_EXTINT                0x7
  70 #define IOAPIC_DM_MASK                  0x7
  71
  72 #define IOAPIC_VECTOR_MASK              0xff
  73
  74 #define IOAPIC_IOREGSEL                 0x00
  75 #define IOAPIC_IOWIN                    0x10
  76
  77 #define IOAPIC_REG_ID                   0x00
  78 #define IOAPIC_REG_VER                  0x01
  79 #define IOAPIC_REG_ARB                  0x02
  80 #define IOAPIC_REG_REDTBL_BASE          0x10
  81 #define IOAPIC_ID                       0x00
  82
  83 #define IOAPIC_ID_SHIFT                 24
  84 #define IOAPIC_ID_MASK                  0xf
  85
  86 #define IOAPIC_VER_ENTRIES_SHIFT        16
  87
  88 typedef struct IOAPICState IOAPICState;
  89
  90 struct IOAPICState {
  91     SysBusDevice busdev;
  92     uint8_t id;
  93     uint8_t ioregsel;
  94     uint32_t irr;
  95     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  96 };
  97
  98 static IOAPICState *ioapics[MAX_IOAPICS];
  99
 100 static void ioapic_service(IOAPICState *s)
 101 {
 102     uint8_t i;
 103     uint8_t trig_mode;
 104     uint8_t vector;
 105     uint8_t delivery_mode;
 106     uint32_t mask;
 107     uint64_t entry;
 108     uint8_t dest;
 109     uint8_t dest_mode;
 110     uint8_t polarity;
 111
 112     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 113         mask = 1 << i;
 114         if (s->irr & mask) {
 115             entry = s->ioredtbl[i];
 116             if (!(entry & IOAPIC_LVT_MASKED)) {
 117                 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
 118                 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
 119                 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
 120                 delivery_mode =
 121                     (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
 122                 polarity = (entry >> IOAPIC_LVT_POLARITY_SHIFT) & 1;
 123                 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
 124                     s->irr &= ~mask;
 125                 } else {
 126                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
 127                 }
 128                 if (delivery_mode == IOAPIC_DM_EXTINT) {
 129                     vector = pic_read_irq(isa_pic);
 130                 } else {
 131                     vector = entry & IOAPIC_VECTOR_MASK;
 132                 }
 133                 apic_deliver_irq(dest, dest_mode, delivery_mode,
 134                                  vector, polarity, trig_mode);
 135             }
 136         }
 137     }
 138 }
 139
 140 static void ioapic_set_irq(void *opaque, int vector, int level)
 141 {
 142     IOAPICState *s = opaque;
 143
 144     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 145      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 146      * the cleanest way of doing it but it should work. */
 147
 148     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
 149     if (vector == 0 && irq0override) {
 150         vector = 2;
 151     }
 152     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 153         uint32_t mask = 1 << vector;
 154         uint64_t entry = s->ioredtbl[vector];
 155
 156         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 157             IOAPIC_TRIGGER_LEVEL) {
 158             /* level triggered */
 159             if (level) {
 160                 s->irr |= mask;
 161                 ioapic_service(s);
 162             } else {
 163                 s->irr &= ~mask;
 164             }
 165         } else {
 166             /* According to the 82093AA manual, we must ignore edge requests
 167              * if the input pin is masked. */
 168             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 169                 s->irr |= mask;
 170                 ioapic_service(s);
 171             }
 172         }
 173     }
 174 }
 175
 176 void ioapic_eoi_broadcast(int vector)
 177 {
 178     IOAPICState *s;
 179     uint64_t entry;
 180     int i, n;
 181
 182     for (i = 0; i < MAX_IOAPICS; i++) {
 183         s = ioapics[i];
 184         if (!s) {
 185             continue;
 186         }
 187         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 188             entry = s->ioredtbl[n];
 189             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 190                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 191                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 192                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 193                     ioapic_service(s);
 194                 }
 195             }
 196         }
 197     }
 198 }
 199
 200 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 201 {
 202     IOAPICState *s = opaque;
 203     int index;
 204     uint32_t val = 0;
 205
 206     switch (addr & 0xff) {
 207     case IOAPIC_IOREGSEL:
 208         val = s->ioregsel;
 209         break;
 210     case IOAPIC_IOWIN:
 211         switch (s->ioregsel) {
 212         case IOAPIC_REG_ID:
 213             val = s->id << IOAPIC_ID_SHIFT;
 214             break;
 215         case IOAPIC_REG_VER:
 216             val = IOAPIC_VERSION |
 217                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 218             break;
 219         case IOAPIC_REG_ARB:
 220             val = 0;
 221             break;
 222         default:
 223             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 224             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 225                 if (s->ioregsel & 1) {
 226                     val = s->ioredtbl[index] >> 32;
 227                 } else {
 228                     val = s->ioredtbl[index] & 0xffffffff;
 229                 }
 230             }
 231         }
 232         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 233         break;
 234     }
 235     return val;
 236 }
 237
 238 static void
 239 ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 240 {
 241     IOAPICState *s = opaque;
 242     int index;
 243
 244     switch (addr & 0xff) {
 245     case IOAPIC_IOREGSEL:
 246         s->ioregsel = val;
 247         break;
 248     case IOAPIC_IOWIN:
 249         DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
 250         switch (s->ioregsel) {
 251         case IOAPIC_REG_ID:
 252             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 253             break;
 254         case IOAPIC_REG_VER:
 255         case IOAPIC_REG_ARB:
 256             break;
 257         default:
 258             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 259             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 260                 if (s->ioregsel & 1) {
 261                     s->ioredtbl[index] &= 0xffffffff;
 262                     s->ioredtbl[index] |= (uint64_t)val << 32;
 263                 } else {
 264                     s->ioredtbl[index] &= ~0xffffffffULL;
 265                     s->ioredtbl[index] |= val;
 266                 }
 267                 ioapic_service(s);
 268             }
 269         }
 270         break;
 271     }
 272 }
 273
 274 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
 275 {
 276 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 277     struct kvm_irqchip chip;
 278     struct kvm_ioapic_state *kioapic;
 279     int i;
 280
 281     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 282     kvm_get_irqchip(kvm_context, &chip);
 283     kioapic = &chip.chip.ioapic;
 284
 285     s->id = kioapic->id;
 286     s->ioregsel = kioapic->ioregsel;
 287     s->irr = kioapic->irr;
 288     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 289         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
 290     }
 291 #endif
 292 }
 293
 294 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
 295 {
 296 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 297     struct kvm_irqchip chip;
 298     struct kvm_ioapic_state *kioapic;
 299     int i;
 300
 301     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 302     kioapic = &chip.chip.ioapic;
 303
 304     kioapic->id = s->id;
 305     kioapic->ioregsel = s->ioregsel;
 306     kioapic->base_address = s->busdev.mmio[0].addr;
 307     kioapic->irr = s->irr;
 308     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 309         kioapic->redirtbl[i].bits = s->ioredtbl[i];
 310     }
 311
 312     kvm_set_irqchip(kvm_context, &chip);
 313 #endif
 314 }
 315
 316 static void ioapic_pre_save(void *opaque)
 317 {
 318     IOAPICState *s = (void *)opaque;
 319
 320     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 321         kvm_kernel_ioapic_save_to_user(s);
 322     }
 323 }
 324
 325 static int ioapic_post_load(void *opaque, int version_id)
 326 {
 327     IOAPICState *s = opaque;
 328
 329     if (version_id == 1) {
 330         /* set sane value */
 331         s->irr = 0;
 332     }
 333
 334     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 335         kvm_kernel_ioapic_load_from_user(s);
 336     }
 337
 338     return 0;
 339 }
 340
 341 static const VMStateDescription vmstate_ioapic = {
 342     .name = "ioapic",
 343     .version_id = 3,
 344     .minimum_version_id = 1,
 345     .minimum_version_id_old = 1,
 346     .post_load = ioapic_post_load,
 347     .pre_save = ioapic_pre_save,
 348     .fields = (VMStateField[]) {
 349         VMSTATE_UINT8(id, IOAPICState),
 350         VMSTATE_UINT8(ioregsel, IOAPICState),
 351         VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */
 352         VMSTATE_UINT32_V(irr, IOAPICState, 2),
 353         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
 354         VMSTATE_END_OF_LIST()
 355     }
 356 };
 357
 358 static void ioapic_reset(DeviceState *d)
 359 {
 360     IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
 361     int i;
 362
 363     s->id = 0;
 364     s->ioregsel = 0;
 365     s->irr = 0;
 366     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 367         s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT;
 368     }
 369 #ifdef KVM_CAP_IRQCHIP
 370     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 371         kvm_kernel_ioapic_load_from_user(s);
 372     }
 373 #endif
 374 }
 375
 376 static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
 377     ioapic_mem_readl,
 378     ioapic_mem_readl,
 379     ioapic_mem_readl,
 380 };
 381
 382 static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
 383     ioapic_mem_writel,
 384     ioapic_mem_writel,
 385     ioapic_mem_writel,
 386 };
 387
 388 static int ioapic_init1(SysBusDevice *dev)
 389 {
 390     IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
 391     int io_memory;
 392     static int ioapic_no;
 393
 394     if (ioapic_no >= MAX_IOAPICS) {
 395         return -1;
 396     }
 397
 398     io_memory = cpu_register_io_memory(ioapic_mem_read,
 399                                        ioapic_mem_write, s,
 400                                        DEVICE_NATIVE_ENDIAN);
 401     sysbus_init_mmio(dev, 0x1000, io_memory);
 402
 403     qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
 404
 405     ioapics[ioapic_no++] = s;
 406
 407     return 0;
 408 }
 409
 410 static SysBusDeviceInfo ioapic_info = {
 411     .init = ioapic_init1,
 412     .qdev.name = "ioapic",
 413     .qdev.size = sizeof(IOAPICState),
 414     .qdev.vmsd = &vmstate_ioapic,
 415     .qdev.reset = ioapic_reset,
 416     .qdev.no_user = 1,
 417 };
 418
 419 static void ioapic_register_devices(void)
 420 {
 421     sysbus_register_withprop(&ioapic_info);
 422 }
 423
 424 device_init(ioapic_register_devices)