hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33 #include "mc146818rtc.h"
  34
  35 //#define HPET_DEBUG
  36 #ifdef HPET_DEBUG
  37 #define DPRINTF printf
  38 #else
  39 #define DPRINTF(...)
  40 #endif
  41
  42 #define HPET_MSI_SUPPORT        0
  43
  44 struct HPETState;
  45 typedef struct HPETTimer {  /* timers */
  46     uint8_t tn;             /*timer number*/
  47     QEMUTimer *qemu_timer;
  48     struct HPETState *state;
  49     /* Memory-mapped, software visible timer registers */
  50     uint64_t config;        /* configuration/cap */
  51     uint64_t cmp;           /* comparator */
  52     uint64_t fsb;           /* FSB route */
  53     /* Hidden register state */
  54     uint64_t period;        /* Last value written to comparator */
  55     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  56                              * mode. Next pop will be actual timer expiration.
  57                              */
  58 } HPETTimer;
  59
  60 typedef struct HPETState {
  61     SysBusDevice busdev;
  62     uint64_t hpet_offset;
  63     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  64     uint32_t flags;
  65     uint8_t rtc_irq_level;
  66     uint8_t num_timers;
  67     HPETTimer timer[HPET_MAX_TIMERS];
  68
  69     /* Memory-mapped, software visible registers */
  70     uint64_t capability;        /* capabilities */
  71     uint64_t config;            /* configuration */
  72     uint64_t isr;               /* interrupt status reg */
  73     uint64_t hpet_counter;      /* main counter */
  74     uint8_t  hpet_id;           /* instance id */
  75 } HPETState;
  76
  77 static uint32_t hpet_in_legacy_mode(HPETState *s)
  78 {
  79     return s->config & HPET_CFG_LEGACY;
  80 }
  81
  82 static uint32_t timer_int_route(struct HPETTimer *timer)
  83 {
  84     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  85 }
  86
  87 static uint32_t timer_fsb_route(HPETTimer *t)
  88 {
  89     return t->config & HPET_TN_FSB_ENABLE;
  90 }
  91
  92 static uint32_t hpet_enabled(HPETState *s)
  93 {
  94     return s->config & HPET_CFG_ENABLE;
  95 }
  96
  97 static uint32_t timer_is_periodic(HPETTimer *t)
  98 {
  99     return t->config & HPET_TN_PERIODIC;
 100 }
 101
 102 static uint32_t timer_enabled(HPETTimer *t)
 103 {
 104     return t->config & HPET_TN_ENABLE;
 105 }
 106
 107 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 108 {
 109     return ((int32_t)(b) - (int32_t)(a) < 0);
 110 }
 111
 112 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 113 {
 114     return ((int64_t)(b) - (int64_t)(a) < 0);
 115 }
 116
 117 static uint64_t ticks_to_ns(uint64_t value)
 118 {
 119     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 120 }
 121
 122 static uint64_t ns_to_ticks(uint64_t value)
 123 {
 124     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 125 }
 126
 127 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 128 {
 129     new &= mask;
 130     new |= old & ~mask;
 131     return new;
 132 }
 133
 134 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 135 {
 136     return (!(old & mask) && (new & mask));
 137 }
 138
 139 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 140 {
 141     return ((old & mask) && !(new & mask));
 142 }
 143
 144 static uint64_t hpet_get_ticks(HPETState *s)
 145 {
 146     return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
 147 }
 148
 149 /*
 150  * calculate diff between comparator value and current ticks
 151  */
 152 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 153 {
 154
 155     if (t->config & HPET_TN_32BIT) {
 156         uint32_t diff, cmp;
 157
 158         cmp = (uint32_t)t->cmp;
 159         diff = cmp - (uint32_t)current;
 160         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 161         return (uint64_t)diff;
 162     } else {
 163         uint64_t diff, cmp;
 164
 165         cmp = t->cmp;
 166         diff = cmp - current;
 167         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 168         return diff;
 169     }
 170 }
 171
 172 static void update_irq(struct HPETTimer *timer, int set)
 173 {
 174     uint64_t mask;
 175     HPETState *s;
 176     int route;
 177
 178     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 179         /* if LegacyReplacementRoute bit is set, HPET specification requires
 180          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 181          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 182          */
 183         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 184     } else {
 185         route = timer_int_route(timer);
 186     }
 187     s = timer->state;
 188     mask = 1 << timer->tn;
 189     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 190         s->isr &= ~mask;
 191         if (!timer_fsb_route(timer)) {
 192             qemu_irq_lower(s->irqs[route]);
 193         }
 194     } else if (timer_fsb_route(timer)) {
 195         stl_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
 196     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 197         s->isr |= mask;
 198         qemu_irq_raise(s->irqs[route]);
 199     } else {
 200         s->isr &= ~mask;
 201         qemu_irq_pulse(s->irqs[route]);
 202     }
 203 }
 204
 205 static void hpet_pre_save(void *opaque)
 206 {
 207     HPETState *s = opaque;
 208
 209     /* save current counter value */
 210     s->hpet_counter = hpet_get_ticks(s);
 211 }
 212
 213 static int hpet_pre_load(void *opaque)
 214 {
 215     HPETState *s = opaque;
 216
 217     /* version 1 only supports 3, later versions will load the actual value */
 218     s->num_timers = HPET_MIN_TIMERS;
 219     return 0;
 220 }
 221
 222 static int hpet_post_load(void *opaque, int version_id)
 223 {
 224     HPETState *s = opaque;
 225
 226     /* Recalculate the offset between the main counter and guest time */
 227     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
 228
 229     /* Push number of timers into capability returned via HPET_ID */
 230     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 231     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 232     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 233
 234     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 235     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 236     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 237         s->flags |= 1 << HPET_MSI_SUPPORT;
 238     }
 239
 240     if (hpet_in_legacy_mode(s)) {
 241         hpet_pit_disable();
 242     }
 243
 244     return 0;
 245 }
 246
 247 static const VMStateDescription vmstate_hpet_timer = {
 248     .name = "hpet_timer",
 249     .version_id = 1,
 250     .minimum_version_id = 1,
 251     .minimum_version_id_old = 1,
 252     .fields      = (VMStateField []) {
 253         VMSTATE_UINT8(tn, HPETTimer),
 254         VMSTATE_UINT64(config, HPETTimer),
 255         VMSTATE_UINT64(cmp, HPETTimer),
 256         VMSTATE_UINT64(fsb, HPETTimer),
 257         VMSTATE_UINT64(period, HPETTimer),
 258         VMSTATE_UINT8(wrap_flag, HPETTimer),
 259         VMSTATE_TIMER(qemu_timer, HPETTimer),
 260         VMSTATE_END_OF_LIST()
 261     }
 262 };
 263
 264 static const VMStateDescription vmstate_hpet = {
 265     .name = "hpet",
 266     .version_id = 2,
 267     .minimum_version_id = 1,
 268     .minimum_version_id_old = 1,
 269     .pre_save = hpet_pre_save,
 270     .pre_load = hpet_pre_load,
 271     .post_load = hpet_post_load,
 272     .fields      = (VMStateField []) {
 273         VMSTATE_UINT64(config, HPETState),
 274         VMSTATE_UINT64(isr, HPETState),
 275         VMSTATE_UINT64(hpet_counter, HPETState),
 276         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 277         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 278                                     vmstate_hpet_timer, HPETTimer),
 279         VMSTATE_END_OF_LIST()
 280     }
 281 };
 282
 283 /*
 284  * timer expiration callback
 285  */
 286 static void hpet_timer(void *opaque)
 287 {
 288     HPETTimer *t = opaque;
 289     uint64_t diff;
 290
 291     uint64_t period = t->period;
 292     uint64_t cur_tick = hpet_get_ticks(t->state);
 293
 294     if (timer_is_periodic(t) && period != 0) {
 295         if (t->config & HPET_TN_32BIT) {
 296             while (hpet_time_after(cur_tick, t->cmp)) {
 297                 t->cmp = (uint32_t)(t->cmp + t->period);
 298             }
 299         } else {
 300             while (hpet_time_after64(cur_tick, t->cmp)) {
 301                 t->cmp += period;
 302             }
 303         }
 304         diff = hpet_calculate_diff(t, cur_tick);
 305         qemu_mod_timer(t->qemu_timer,
 306                        qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
 307     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 308         if (t->wrap_flag) {
 309             diff = hpet_calculate_diff(t, cur_tick);
 310             qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
 311                            (int64_t)ticks_to_ns(diff));
 312             t->wrap_flag = 0;
 313         }
 314     }
 315     update_irq(t, 1);
 316 }
 317
 318 static void hpet_set_timer(HPETTimer *t)
 319 {
 320     uint64_t diff;
 321     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 322     uint64_t cur_tick = hpet_get_ticks(t->state);
 323
 324     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 325     t->wrap_flag = 0;
 326     diff = hpet_calculate_diff(t, cur_tick);
 327
 328     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 329      * counter wraps in addition to an interrupt with comparator match.
 330      */
 331     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 332         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 333         if (wrap_diff < (uint32_t)diff) {
 334             diff = wrap_diff;
 335             t->wrap_flag = 1;
 336         }
 337     }
 338     qemu_mod_timer(t->qemu_timer,
 339                    qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
 340 }
 341
 342 static void hpet_del_timer(HPETTimer *t)
 343 {
 344     qemu_del_timer(t->qemu_timer);
 345     update_irq(t, 0);
 346 }
 347
 348 #ifdef HPET_DEBUG
 349 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 350 {
 351     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 352     return 0;
 353 }
 354
 355 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 356 {
 357     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 358     return 0;
 359 }
 360 #endif
 361
 362 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 363 {
 364     HPETState *s = opaque;
 365     uint64_t cur_tick, index;
 366
 367     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 368     index = addr;
 369     /*address range of all TN regs*/
 370     if (index >= 0x100 && index <= 0x3ff) {
 371         uint8_t timer_id = (addr - 0x100) / 0x20;
 372         HPETTimer *timer = &s->timer[timer_id];
 373
 374         if (timer_id > s->num_timers) {
 375             DPRINTF("qemu: timer id out of range\n");
 376             return 0;
 377         }
 378
 379         switch ((addr - 0x100) % 0x20) {
 380         case HPET_TN_CFG:
 381             return timer->config;
 382         case HPET_TN_CFG + 4: // Interrupt capabilities
 383             return timer->config >> 32;
 384         case HPET_TN_CMP: // comparator register
 385             return timer->cmp;
 386         case HPET_TN_CMP + 4:
 387             return timer->cmp >> 32;
 388         case HPET_TN_ROUTE:
 389             return timer->fsb;
 390         case HPET_TN_ROUTE + 4:
 391             return timer->fsb >> 32;
 392         default:
 393             DPRINTF("qemu: invalid hpet_ram_readl\n");
 394             break;
 395         }
 396     } else {
 397         switch (index) {
 398         case HPET_ID:
 399             return s->capability;
 400         case HPET_PERIOD:
 401             return s->capability >> 32;
 402         case HPET_CFG:
 403             return s->config;
 404         case HPET_CFG + 4:
 405             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 406             return 0;
 407         case HPET_COUNTER:
 408             if (hpet_enabled(s)) {
 409                 cur_tick = hpet_get_ticks(s);
 410             } else {
 411                 cur_tick = s->hpet_counter;
 412             }
 413             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 414             return cur_tick;
 415         case HPET_COUNTER + 4:
 416             if (hpet_enabled(s)) {
 417                 cur_tick = hpet_get_ticks(s);
 418             } else {
 419                 cur_tick = s->hpet_counter;
 420             }
 421             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 422             return cur_tick >> 32;
 423         case HPET_STATUS:
 424             return s->isr;
 425         default:
 426             DPRINTF("qemu: invalid hpet_ram_readl\n");
 427             break;
 428         }
 429     }
 430     return 0;
 431 }
 432
 433 #ifdef HPET_DEBUG
 434 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 435                             uint32_t value)
 436 {
 437     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 438            addr, value);
 439 }
 440
 441 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 442                             uint32_t value)
 443 {
 444     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 445            addr, value);
 446 }
 447 #endif
 448
 449 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 450                             uint32_t value)
 451 {
 452     int i;
 453     HPETState *s = opaque;
 454     uint64_t old_val, new_val, val, index;
 455
 456     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 457     index = addr;
 458     old_val = hpet_ram_readl(opaque, addr);
 459     new_val = value;
 460
 461     /*address range of all TN regs*/
 462     if (index >= 0x100 && index <= 0x3ff) {
 463         uint8_t timer_id = (addr - 0x100) / 0x20;
 464         HPETTimer *timer = &s->timer[timer_id];
 465
 466         DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 467         if (timer_id > s->num_timers) {
 468             DPRINTF("qemu: timer id out of range\n");
 469             return;
 470         }
 471         switch ((addr - 0x100) % 0x20) {
 472         case HPET_TN_CFG:
 473             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 474             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 475                 update_irq(timer, 0);
 476             }
 477             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 478             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 479             if (new_val & HPET_TN_32BIT) {
 480                 timer->cmp = (uint32_t)timer->cmp;
 481                 timer->period = (uint32_t)timer->period;
 482             }
 483             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 484                 hpet_set_timer(timer);
 485             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 486                 hpet_del_timer(timer);
 487             }
 488             break;
 489         case HPET_TN_CFG + 4: // Interrupt capabilities
 490             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 491             break;
 492         case HPET_TN_CMP: // comparator register
 493             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
 494             if (timer->config & HPET_TN_32BIT) {
 495                 new_val = (uint32_t)new_val;
 496             }
 497             if (!timer_is_periodic(timer)
 498                 || (timer->config & HPET_TN_SETVAL)) {
 499                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 500             }
 501             if (timer_is_periodic(timer)) {
 502                 /*
 503                  * FIXME: Clamp period to reasonable min value?
 504                  * Clamp period to reasonable max value
 505                  */
 506                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 507                 timer->period =
 508                     (timer->period & 0xffffffff00000000ULL) | new_val;
 509             }
 510             timer->config &= ~HPET_TN_SETVAL;
 511             if (hpet_enabled(s)) {
 512                 hpet_set_timer(timer);
 513             }
 514             break;
 515         case HPET_TN_CMP + 4: // comparator register high order
 516             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 517             if (!timer_is_periodic(timer)
 518                 || (timer->config & HPET_TN_SETVAL)) {
 519                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 520             } else {
 521                 /*
 522                  * FIXME: Clamp period to reasonable min value?
 523                  * Clamp period to reasonable max value
 524                  */
 525                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 526                 timer->period =
 527                     (timer->period & 0xffffffffULL) | new_val << 32;
 528                 }
 529                 timer->config &= ~HPET_TN_SETVAL;
 530                 if (hpet_enabled(s)) {
 531                     hpet_set_timer(timer);
 532                 }
 533                 break;
 534         case HPET_TN_ROUTE:
 535             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 536             break;
 537         case HPET_TN_ROUTE + 4:
 538             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 539             break;
 540         default:
 541             DPRINTF("qemu: invalid hpet_ram_writel\n");
 542             break;
 543         }
 544         return;
 545     } else {
 546         switch (index) {
 547         case HPET_ID:
 548             return;
 549         case HPET_CFG:
 550             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 551             s->config = (s->config & 0xffffffff00000000ULL) | val;
 552             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 553                 /* Enable main counter and interrupt generation. */
 554                 s->hpet_offset =
 555                     ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
 556                 for (i = 0; i < s->num_timers; i++) {
 557                     if ((&s->timer[i])->cmp != ~0ULL) {
 558                         hpet_set_timer(&s->timer[i]);
 559                     }
 560                 }
 561             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 562                 /* Halt main counter and disable interrupt generation. */
 563                 s->hpet_counter = hpet_get_ticks(s);
 564                 for (i = 0; i < s->num_timers; i++) {
 565                     hpet_del_timer(&s->timer[i]);
 566                 }
 567             }
 568             /* i8254 and RTC are disabled when HPET is in legacy mode */
 569             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 570                 hpet_pit_disable();
 571                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 572             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 573                 hpet_pit_enable();
 574                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 575             }
 576             break;
 577         case HPET_CFG + 4:
 578             DPRINTF("qemu: invalid HPET_CFG+4 write \n");
 579             break;
 580         case HPET_STATUS:
 581             val = new_val & s->isr;
 582             for (i = 0; i < s->num_timers; i++) {
 583                 if (val & (1 << i)) {
 584                     update_irq(&s->timer[i], 0);
 585                 }
 586             }
 587             break;
 588         case HPET_COUNTER:
 589             if (hpet_enabled(s)) {
 590                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 591             }
 592             s->hpet_counter =
 593                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 594             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 595                     value, s->hpet_counter);
 596             break;
 597         case HPET_COUNTER + 4:
 598             if (hpet_enabled(s)) {
 599                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 600             }
 601             s->hpet_counter =
 602                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 603             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 604                     value, s->hpet_counter);
 605             break;
 606         default:
 607             DPRINTF("qemu: invalid hpet_ram_writel\n");
 608             break;
 609         }
 610     }
 611 }
 612
 613 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 614 #ifdef HPET_DEBUG
 615     hpet_ram_readb,
 616     hpet_ram_readw,
 617 #else
 618     NULL,
 619     NULL,
 620 #endif
 621     hpet_ram_readl,
 622 };
 623
 624 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 625 #ifdef HPET_DEBUG
 626     hpet_ram_writeb,
 627     hpet_ram_writew,
 628 #else
 629     NULL,
 630     NULL,
 631 #endif
 632     hpet_ram_writel,
 633 };
 634
 635 static void hpet_reset(DeviceState *d)
 636 {
 637     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 638     int i;
 639     static int count = 0;
 640
 641     for (i = 0; i < s->num_timers; i++) {
 642         HPETTimer *timer = &s->timer[i];
 643
 644         hpet_del_timer(timer);
 645         timer->cmp = ~0ULL;
 646         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 647         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 648             timer->config |= HPET_TN_FSB_CAP;
 649         }
 650         /* advertise availability of ioapic inti2 */
 651         timer->config |=  0x00000004ULL << 32;
 652         timer->period = 0ULL;
 653         timer->wrap_flag = 0;
 654     }
 655
 656     s->hpet_counter = 0ULL;
 657     s->hpet_offset = 0ULL;
 658     s->config = 0ULL;
 659     if (count > 0) {
 660         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 661          * because hpet is taking over for pit here. On subsequent invocations,
 662          * hpet_reset is called due to system reset. At this point control must
 663          * be returned to pit until SW reenables hpet.
 664          */
 665         hpet_pit_enable();
 666     }
 667     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 668     hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
 669     count = 1;
 670 }
 671
 672 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
 673 {
 674     HPETState *s = FROM_SYSBUS(HPETState, opaque);
 675
 676     s->rtc_irq_level = level;
 677     if (!hpet_in_legacy_mode(s)) {
 678         qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 679     }
 680 }
 681
 682 static int hpet_init(SysBusDevice *dev)
 683 {
 684     HPETState *s = FROM_SYSBUS(HPETState, dev);
 685     int i, iomemtype;
 686     HPETTimer *timer;
 687
 688     if (hpet_cfg.count == UINT8_MAX) {
 689         /* first instance */
 690         hpet_cfg.count = 0;
 691     }
 692
 693     if (hpet_cfg.count == 8) {
 694         fprintf(stderr, "Only 8 instances of HPET is allowed\n");
 695         return -1;
 696     }
 697
 698     s->hpet_id = hpet_cfg.count++;
 699
 700     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 701         sysbus_init_irq(dev, &s->irqs[i]);
 702     }
 703
 704     if (s->num_timers < HPET_MIN_TIMERS) {
 705         s->num_timers = HPET_MIN_TIMERS;
 706     } else if (s->num_timers > HPET_MAX_TIMERS) {
 707         s->num_timers = HPET_MAX_TIMERS;
 708     }
 709     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 710         timer = &s->timer[i];
 711         timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
 712         timer->tn = i;
 713         timer->state = s;
 714     }
 715
 716     /* 64-bit main counter; LegacyReplacementRoute. */
 717     s->capability = 0x8086a001ULL;
 718     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 719     s->capability |= ((HPET_CLK_PERIOD) << 32);
 720
 721     qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
 722
 723     /* HPET Area */
 724     iomemtype = cpu_register_io_memory(hpet_ram_read,
 725                                        hpet_ram_write, s,
 726                                        DEVICE_NATIVE_ENDIAN);
 727     sysbus_init_mmio(dev, 0x400, iomemtype);
 728     return 0;
 729 }
 730
 731 static SysBusDeviceInfo hpet_device_info = {
 732     .qdev.name    = "hpet",
 733     .qdev.size    = sizeof(HPETState),
 734     .qdev.no_user = 1,
 735     .qdev.vmsd    = &vmstate_hpet,
 736     .qdev.reset   = hpet_reset,
 737     .init         = hpet_init,
 738     .qdev.props = (Property[]) {
 739         DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 740         DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 741         DEFINE_PROP_END_OF_LIST(),
 742     },
 743 };
 744
 745 static void hpet_register_device(void)
 746 {
 747     sysbus_register_withprop(&hpet_device_info);
 748 }
 749
 750 device_init(hpet_register_device)