hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 struct kvm_irq_routing_entry;
  10
  11 /* PCI includes legacy ISA access.  */
  12 #include "isa.h"
  13
  14 /* PCI bus */
  15
  16 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  18 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  19
  20 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  21 #include "pci_ids.h"
  22
  23 /* QEMU-specific Vendor and Device ID definitions */
  24
  25 /* IBM (0x1014) */
  26 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  27 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  28
  29 /* Hitachi (0x1054) */
  30 #define PCI_VENDOR_ID_HITACHI            0x1054
  31 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  32
  33 /* Apple (0x106b) */
  34 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  35 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  37 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  38 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  39
  40 /* Realtek (0x10ec) */
  41 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  42
  43 /* Xilinx (0x10ee) */
  44 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  45
  46 /* Marvell (0x11ab) */
  47 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  48
  49 /* QEMU/Bochs VGA (0x1234) */
  50 #define PCI_VENDOR_ID_QEMU               0x1234
  51 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  52
  53 /* VMWare (0x15ad) */
  54 #define PCI_VENDOR_ID_VMWARE             0x15ad
  55 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  56 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  57 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  58 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  59 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  60
  61 /* Intel (0x8086) */
  62 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  63 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  64
  65 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  66 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  67 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  68 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  69
  70 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  71 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  72 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  73 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  74
  75 #define FMT_PCIBUS                      PRIx64
  76
  77 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  78                                 uint32_t address, uint32_t data, int len);
  79 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  80                                    uint32_t address, int len);
  81 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  82                                 pcibus_t addr, pcibus_t size, int type);
  83 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  84
  85 typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev,
  86                                    uint32_t address, uint32_t val, int len);
  87 typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev,
  88                                       uint32_t address, int len);
  89 typedef int PCICapConfigInitFunc(PCIDevice *pci_dev);
  90
  91 typedef struct PCIIORegion {
  92     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  93 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  94     pcibus_t size;
  95     pcibus_t filtered_size;
  96     uint8_t type;
  97     PCIMapIORegionFunc *map_func;
  98 } PCIIORegion;
  99
 100 #define PCI_ROM_SLOT 6
 101 #define PCI_NUM_REGIONS 7
 102
 103 #include "pci_regs.h"
 104
 105 /* PCI HEADER_TYPE */
 106 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 107
 108 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 109                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 110                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 111
 112 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 113
 114 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 115 #define PCI_COMMAND_RESERVED    0xf800
 116
 117 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 118
 119 /* Size of the standard PCI config header */
 120 #define PCI_CONFIG_HEADER_SIZE 0x40
 121 /* Size of the standard PCI config space */
 122 #define PCI_CONFIG_SPACE_SIZE 0x100
 123 /* Size of the standart PCIe config space: 4KB */
 124 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 125
 126 #define PCI_NUM_PINS 4 /* A-D */
 127
 128 /* Bits in cap_present field. */
 129 enum {
 130     QEMU_PCI_CAP_MSIX = 0x1,
 131     QEMU_PCI_CAP_EXPRESS = 0x2,
 132 };
 133
 134 #define PCI_CAPABILITY_CONFIG_MAX_LENGTH 0x60
 135 #define PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR 0x40
 136 #define PCI_CAPABILITY_CONFIG_MSI_LENGTH 0x10
 137 #define PCI_CAPABILITY_CONFIG_MSIX_LENGTH 0x10
 138
 139 typedef int (*msix_mask_notifier_func)(PCIDevice *, unsigned vector,
 140                                        void *opaque, int masked);
 141
 142 struct PCIDevice {
 143     DeviceState qdev;
 144     /* PCI config space */
 145     uint8_t *config;
 146
 147     /* Used to enable config checks on load. Note that writeable bits are
 148      * never checked even if set in cmask. */
 149     uint8_t *cmask;
 150
 151     /* Used to implement R/W bytes */
 152     uint8_t *wmask;
 153
 154     /* Used to allocate config space for capabilities. */
 155     uint8_t *used;
 156
 157     /* the following fields are read only */
 158     PCIBus *bus;
 159     uint32_t devfn;
 160     char name[64];
 161     PCIIORegion io_regions[PCI_NUM_REGIONS];
 162
 163     /* do not access the following fields */
 164     PCIConfigReadFunc *config_read;
 165     PCIConfigWriteFunc *config_write;
 166
 167     /* IRQ objects for the INTA-INTD pins.  */
 168     qemu_irq *irq;
 169
 170     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 171     uint8_t irq_state;
 172
 173     /* Capability bits */
 174     uint32_t cap_present;
 175
 176     /* Offset of MSI-X capability in config space */
 177     uint8_t msix_cap;
 178
 179     /* MSI-X entries */
 180     int msix_entries_nr;
 181
 182     /* Space to store MSIX table */
 183     uint8_t *msix_table_page;
 184     /* MMIO index used to map MSIX table and pending bit entries. */
 185     int msix_mmio_index;
 186     /* Reference-count for entries actually in use by driver. */
 187     unsigned *msix_entry_used;
 188     /* Region including the MSI-X table */
 189     uint32_t msix_bar_size;
 190     /* Version id needed for VMState */
 191     int32_t version_id;
 192
 193     /* Location of option rom */
 194     char *romfile;
 195     ram_addr_t rom_offset;
 196     uint32_t rom_bar;
 197
 198     /* How much space does an MSIX table need. */
 199     /* The spec requires giving the table structure
 200      * a 4K aligned region all by itself. Align it to
 201      * target pages so that drivers can do passthrough
 202      * on the rest of the region. */
 203     target_phys_addr_t msix_page_size;
 204
 205     struct kvm_irq_routing_entry *msix_irq_entries;
 206
 207     void **msix_mask_notifier_opaque;
 208     msix_mask_notifier_func msix_mask_notifier;
 209
 210     /* Device capability configuration space */
 211     struct {
 212         int supported;
 213         unsigned int start, length;
 214         PCICapConfigReadFunc *config_read;
 215         PCICapConfigWriteFunc *config_write;
 216     } cap;
 217 };
 218
 219 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 220                                int instance_size, int devfn,
 221                                PCIConfigReadFunc *config_read,
 222                                PCIConfigWriteFunc *config_write);
 223
 224 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 225                             pcibus_t size, int type,
 226                             PCIMapIORegionFunc *map_func);
 227
 228 int pci_enable_capability_support(PCIDevice *pci_dev,
 229                                   uint32_t config_start,
 230                                   PCICapConfigReadFunc *config_read,
 231                                   PCICapConfigWriteFunc *config_write,
 232                                   PCICapConfigInitFunc *config_init);
 233
 234 int pci_map_irq(PCIDevice *pci_dev, int pin);
 235
 236 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 237 int pci_add_capability_at_offset(PCIDevice *pci_dev, uint8_t cap_id,
 238                                  uint8_t cap_offset, uint8_t cap_size);
 239
 240 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 241
 242 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 243
 244 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 245
 246 uint32_t pci_default_read_config(PCIDevice *d,
 247                                  uint32_t address, int len);
 248 void pci_default_write_config(PCIDevice *d,
 249                               uint32_t address, uint32_t val, int len);
 250 void pci_device_save(PCIDevice *s, QEMUFile *f);
 251 int pci_device_load(PCIDevice *s, QEMUFile *f);
 252 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 253                                      uint32_t address, int len);
 254 void pci_default_cap_write_config(PCIDevice *pci_dev,
 255                                   uint32_t address, uint32_t val, int len);
 256 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len);
 257
 258 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 259 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 260 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
 261 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 262                          const char *name, int devfn_min);
 263 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 264 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 265                   void *irq_opaque, int nirq);
 266 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 267 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 268                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 269                          void *irq_opaque, int devfn_min, int nirq);
 270
 271 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 272
 273 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 274                         const char *default_devaddr);
 275 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 276                                const char *default_devaddr);
 277 int pci_bus_num(PCIBus *s);
 278 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 279 PCIBus *pci_find_root_bus(int domain);
 280 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 281 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 282 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 283
 284 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 285                      unsigned *slotp);
 286
 287 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
 288                            int *slotp, int *funcp);
 289
 290 void do_pci_info_print(Monitor *mon, const QObject *data);
 291 void do_pci_info(Monitor *mon, QObject **ret_data);
 292 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 293                         pci_map_irq_fn map_irq, const char *name);
 294 PCIDevice *pci_bridge_get_device(PCIBus *bus);
 295
 296 static inline void
 297 pci_set_byte(uint8_t *config, uint8_t val)
 298 {
 299     *config = val;
 300 }
 301
 302 static inline uint8_t
 303 pci_get_byte(const uint8_t *config)
 304 {
 305     return *config;
 306 }
 307
 308 static inline void
 309 pci_set_word(uint8_t *config, uint16_t val)
 310 {
 311     cpu_to_le16wu((uint16_t *)config, val);
 312 }
 313
 314 static inline uint16_t
 315 pci_get_word(const uint8_t *config)
 316 {
 317     return le16_to_cpupu((const uint16_t *)config);
 318 }
 319
 320 static inline void
 321 pci_set_long(uint8_t *config, uint32_t val)
 322 {
 323     cpu_to_le32wu((uint32_t *)config, val);
 324 }
 325
 326 static inline uint32_t
 327 pci_get_long(const uint8_t *config)
 328 {
 329     return le32_to_cpupu((const uint32_t *)config);
 330 }
 331
 332 static inline void
 333 pci_set_quad(uint8_t *config, uint64_t val)
 334 {
 335     cpu_to_le64w((uint64_t *)config, val);
 336 }
 337
 338 static inline uint64_t
 339 pci_get_quad(const uint8_t *config)
 340 {
 341     return le64_to_cpup((const uint64_t *)config);
 342 }
 343
 344 static inline void
 345 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 346 {
 347     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 348 }
 349
 350 static inline void
 351 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 352 {
 353     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 354 }
 355
 356 static inline void
 357 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 358 {
 359     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 360 }
 361
 362 static inline void
 363 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 364 {
 365     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 366 }
 367
 368 static inline void
 369 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 370 {
 371     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 372 }
 373
 374 static inline void
 375 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 376 {
 377     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 378 }
 379
 380 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 381 typedef struct {
 382     DeviceInfo qdev;
 383     pci_qdev_initfn init;
 384     PCIUnregisterFunc *exit;
 385     PCIConfigReadFunc *config_read;
 386     PCIConfigWriteFunc *config_write;
 387
 388     /* pci config header type */
 389     uint8_t header_type;
 390
 391     /* pcie stuff */
 392     int is_express;   /* is this device pci express? */
 393
 394     /* rom bar */
 395     const char *romfile;
 396 } PCIDeviceInfo;
 397
 398 void pci_qdev_register(PCIDeviceInfo *info);
 399 void pci_qdev_register_many(PCIDeviceInfo *info);
 400
 401 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 402 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 403
 404 static inline int pci_is_express(PCIDevice *d)
 405 {
 406     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 407 }
 408
 409 static inline uint32_t pci_config_size(PCIDevice *d)
 410 {
 411     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 412 }
 413
 414 /* These are not pci specific. Should move into a separate header.
 415  * Only pci.c uses them, so keep them here for now.
 416  */
 417
 418 /* Get last byte of a range from offset + length.
 419  * Undefined for ranges that wrap around 0. */
 420 static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
 421 {
 422     return offset + len - 1;
 423 }
 424
 425 /* Check whether a given range covers a given byte. */
 426 static inline int range_covers_byte(uint64_t offset, uint64_t len,
 427                                     uint64_t byte)
 428 {
 429     return offset <= byte && byte <= range_get_last(offset, len);
 430 }
 431
 432 /* Check whether 2 given ranges overlap.
 433  * Undefined if ranges that wrap around 0. */
 434 static inline int ranges_overlap(uint64_t first1, uint64_t len1,
 435                                  uint64_t first2, uint64_t len2)
 436 {
 437     uint64_t last1 = range_get_last(first1, len1);
 438     uint64_t last2 = range_get_last(first2, len2);
 439
 440     return !(last2 < first1 || last1 < first2);
 441 }
 442
 443 #endif