hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "acpi.h"
  24
  25 //#define DEBUG
  26
  27 #ifdef DEBUG
  28 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  29 #else
  30 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  31 #endif
  32
  33 #define ACPI_DBG_IO_ADDR  0xb044
  34
  35 #define GPE_BASE 0xafe0
  36 #define PROC_BASE 0xaf00
  37 #define PCI_BASE 0xae00
  38 #define PCI_EJ_BASE 0xae08
  39
  40 struct gpe_regs {
  41     uint16_t sts; /* status */
  42     uint16_t en;  /* enabled */
  43     uint8_t cpus_sts[32];
  44 };
  45
  46 struct pci_status {
  47     uint32_t up;
  48     uint32_t down;
  49 };
  50
  51 typedef struct PIIX4PMState {
  52     PCIDevice dev;
  53     uint16_t pmsts;
  54     uint16_t pmen;
  55     uint16_t pmcntrl;
  56
  57     APMState apm;
  58
  59     QEMUTimer *tmr_timer;
  60     int64_t tmr_overflow_time;
  61
  62     PMSMBus smb;
  63     uint32_t smb_io_base;
  64
  65     qemu_irq irq;
  66     qemu_irq cmos_s3;
  67     qemu_irq smi_irq;
  68     int kvm_enabled;
  69
  70     /* for pci hotplug */
  71     struct gpe_regs gpe;
  72     struct pci_status pci0_status;
  73 } PIIX4PMState;
  74
  75 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  76
  77 #define ACPI_ENABLE 0xf1
  78 #define ACPI_DISABLE 0xf0
  79
  80 static uint32_t get_pmtmr(PIIX4PMState *s)
  81 {
  82     uint32_t d;
  83     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
  84     return d & 0xffffff;
  85 }
  86
  87 static int get_pmsts(PIIX4PMState *s)
  88 {
  89     int64_t d;
  90
  91     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
  92                  get_ticks_per_sec());
  93     if (d >= s->tmr_overflow_time)
  94         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
  95     return s->pmsts;
  96 }
  97
  98 static void pm_update_sci(PIIX4PMState *s)
  99 {
 100     int sci_level, pmsts;
 101     int64_t expire_time;
 102
 103     pmsts = get_pmsts(s);
 104     sci_level = (((pmsts & s->pmen) &
 105                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 106                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 107                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 108                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
 109     qemu_set_irq(s->irq, sci_level);
 110     /* schedule a timer interruption if needed */
 111     if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
 112         !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
 113         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
 114                                PM_TIMER_FREQUENCY);
 115         qemu_mod_timer(s->tmr_timer, expire_time);
 116     } else {
 117         qemu_del_timer(s->tmr_timer);
 118     }
 119 }
 120
 121 static void pm_tmr_timer(void *opaque)
 122 {
 123     PIIX4PMState *s = opaque;
 124     pm_update_sci(s);
 125 }
 126
 127 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 128 {
 129     PIIX4PMState *s = opaque;
 130     addr &= 0x3f;
 131     switch(addr) {
 132     case 0x00:
 133         {
 134             int64_t d;
 135             int pmsts;
 136             pmsts = get_pmsts(s);
 137             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
 138                 /* if TMRSTS is reset, then compute the new overflow time */
 139                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
 140                              get_ticks_per_sec());
 141                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 142             }
 143             s->pmsts &= ~val;
 144             pm_update_sci(s);
 145         }
 146         break;
 147     case 0x02:
 148         s->pmen = val;
 149         pm_update_sci(s);
 150         break;
 151     case 0x04:
 152         {
 153             int sus_typ;
 154             s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
 155             if (val & ACPI_BITMASK_SLEEP_ENABLE) {
 156                 /* change suspend type */
 157                 sus_typ = (val >> 10) & 7;
 158                 switch(sus_typ) {
 159                 case 0: /* soft power off */
 160                     qemu_system_shutdown_request();
 161                     break;
 162                 case 1:
 163                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
 164                        Pretend that resume was caused by power button */
 165                     s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
 166                                  ACPI_BITMASK_POWER_BUTTON_STATUS);
 167                     qemu_system_reset_request();
 168                     if (s->cmos_s3) {
 169                         qemu_irq_raise(s->cmos_s3);
 170                     }
 171                 default:
 172                     break;
 173                 }
 174             }
 175         }
 176         break;
 177     default:
 178         break;
 179     }
 180     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
 181 }
 182
 183 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 184 {
 185     PIIX4PMState *s = opaque;
 186     uint32_t val;
 187
 188     addr &= 0x3f;
 189     switch(addr) {
 190     case 0x00:
 191         val = get_pmsts(s);
 192         break;
 193     case 0x02:
 194         val = s->pmen;
 195         break;
 196     case 0x04:
 197         val = s->pmcntrl;
 198         break;
 199     default:
 200         val = 0;
 201         break;
 202     }
 203     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
 204     return val;
 205 }
 206
 207 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 208 {
 209     //    PIIX4PMState *s = opaque;
 210     PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
 211 }
 212
 213 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 214 {
 215     PIIX4PMState *s = opaque;
 216     uint32_t val;
 217
 218     addr &= 0x3f;
 219     switch(addr) {
 220     case 0x08:
 221         val = get_pmtmr(s);
 222         break;
 223     default:
 224         val = 0;
 225         break;
 226     }
 227     PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
 228     return val;
 229 }
 230
 231 static void apm_ctrl_changed(uint32_t val, void *arg)
 232 {
 233     PIIX4PMState *s = arg;
 234
 235     /* ACPI specs 3.0, 4.7.2.5 */
 236     if (val == ACPI_ENABLE) {
 237         s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
 238     } else if (val == ACPI_DISABLE) {
 239         s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
 240     }
 241
 242     if (s->dev.config[0x5b] & (1 << 1)) {
 243         if (s->smi_irq) {
 244             qemu_irq_raise(s->smi_irq);
 245         }
 246     }
 247 }
 248
 249 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 250 {
 251     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 252 }
 253
 254 static void pm_io_space_update(PIIX4PMState *s)
 255 {
 256     uint32_t pm_io_base;
 257
 258     if (s->dev.config[0x80] & 1) {
 259         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 260         pm_io_base &= 0xffc0;
 261
 262         /* XXX: need to improve memory and ioport allocation */
 263         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 264         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 265         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 266         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 267         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 268     }
 269 }
 270
 271 static void pm_write_config(PCIDevice *d,
 272                             uint32_t address, uint32_t val, int len)
 273 {
 274     pci_default_write_config(d, address, val, len);
 275     if (range_covers_byte(address, len, 0x80))
 276         pm_io_space_update((PIIX4PMState *)d);
 277 }
 278
 279 static int vmstate_acpi_post_load(void *opaque, int version_id)
 280 {
 281     PIIX4PMState *s = opaque;
 282
 283     pm_io_space_update(s);
 284     return 0;
 285 }
 286
 287 static const VMStateDescription vmstate_acpi = {
 288     .name = "piix4_pm",
 289     .version_id = 1,
 290     .minimum_version_id = 1,
 291     .minimum_version_id_old = 1,
 292     .post_load = vmstate_acpi_post_load,
 293     .fields      = (VMStateField []) {
 294         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 295         VMSTATE_UINT16(pmsts, PIIX4PMState),
 296         VMSTATE_UINT16(pmen, PIIX4PMState),
 297         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 298         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 299         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 300         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 301         VMSTATE_END_OF_LIST()
 302     }
 303 };
 304
 305 static void piix4_reset(void *opaque)
 306 {
 307     PIIX4PMState *s = opaque;
 308     uint8_t *pci_conf = s->dev.config;
 309
 310     pci_conf[0x58] = 0;
 311     pci_conf[0x59] = 0;
 312     pci_conf[0x5a] = 0;
 313     pci_conf[0x5b] = 0;
 314
 315     if (s->kvm_enabled) {
 316         /* Mark SMM as already inited (until KVM supports SMM). */
 317         pci_conf[0x5B] = 0x02;
 318     }
 319 }
 320
 321 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 322 {
 323     PIIX4PMState *s = opaque;
 324
 325     if (!s) {
 326         qemu_system_shutdown_request();
 327     } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
 328         s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
 329         pm_update_sci(s);
 330     }
 331 }
 332
 333 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
 334
 335 static int piix4_pm_initfn(PCIDevice *dev)
 336 {
 337     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 338     uint8_t *pci_conf;
 339
 340     /* for cpu hotadd */
 341     global_piix4_pm_state = s;
 342
 343     pci_conf = s->dev.config;
 344     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 345     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 346     pci_conf[0x06] = 0x80;
 347     pci_conf[0x07] = 0x02;
 348     pci_conf[0x08] = 0x03; // revision number
 349     pci_conf[0x09] = 0x00;
 350     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 351     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 352     pci_conf[0x3d] = 0x01; // interrupt pin 1
 353
 354     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 355
 356 #if defined(TARGET_IA64)
 357     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 358     pci_conf[0x41] = 0x1f;
 359     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 360     s->pmcntrl = SCI_EN;
 361 #endif
 362
 363     /* APM */
 364     apm_init(&s->apm, apm_ctrl_changed, s);
 365
 366     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 367
 368     if (s->kvm_enabled) {
 369         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 370          * support SMM mode. */
 371         pci_conf[0x5B] = 0x02;
 372     }
 373
 374     /* XXX: which specification is used ? The i82731AB has different
 375        mappings */
 376     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 377     pci_conf[0x63] = 0x60;
 378     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 379         (serial_hds[1] != NULL ? 0x90 : 0);
 380
 381     pci_conf[0x90] = s->smb_io_base | 1;
 382     pci_conf[0x91] = s->smb_io_base >> 8;
 383     pci_conf[0xd2] = 0x09;
 384     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 385     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 386
 387     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 388
 389     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 390
 391     pm_smbus_init(&s->dev.qdev, &s->smb);
 392     qemu_register_reset(piix4_reset, s);
 393     piix4_acpi_system_hot_add_init(dev->bus, s);
 394
 395     return 0;
 396 }
 397
 398 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 399                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 400                        int kvm_enabled)
 401 {
 402     PCIDevice *dev;
 403     PIIX4PMState *s;
 404
 405     dev = pci_create(bus, devfn, "PIIX4_PM");
 406     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 407
 408     s = DO_UPCAST(PIIX4PMState, dev, dev);
 409     s->irq = sci_irq;
 410     s->cmos_s3 = cmos_s3;
 411     s->smi_irq = smi_irq;
 412     s->kvm_enabled = kvm_enabled;
 413
 414     qdev_init_nofail(&dev->qdev);
 415
 416     return s->smb.smbus;
 417 }
 418
 419 static PCIDeviceInfo piix4_pm_info = {
 420     .qdev.name          = "PIIX4_PM",
 421     .qdev.desc          = "PM",
 422     .qdev.size          = sizeof(PIIX4PMState),
 423     .qdev.vmsd          = &vmstate_acpi,
 424     .init               = piix4_pm_initfn,
 425     .config_write       = pm_write_config,
 426     .qdev.props         = (Property[]) {
 427         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 428         DEFINE_PROP_END_OF_LIST(),
 429     }
 430 };
 431
 432 static void piix4_pm_register(void)
 433 {
 434     pci_qdev_register(&piix4_pm_info);
 435 }
 436
 437 device_init(piix4_pm_register);
 438
 439 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 440 {
 441     if (addr & 1)
 442         return (val >> 8) & 0xff;
 443     return val & 0xff;
 444 }
 445
 446 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 447 {
 448     uint32_t val = 0;
 449     struct gpe_regs *g = opaque;
 450     switch (addr) {
 451         case PROC_BASE ... PROC_BASE+31:
 452             val = g->cpus_sts[addr - PROC_BASE];
 453             break;
 454
 455         case GPE_BASE:
 456         case GPE_BASE + 1:
 457             val = gpe_read_val(g->sts, addr);
 458             break;
 459         case GPE_BASE + 2:
 460         case GPE_BASE + 3:
 461             val = gpe_read_val(g->en, addr);
 462             break;
 463         default:
 464             break;
 465     }
 466
 467     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 468     return val;
 469 }
 470
 471 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 472 {
 473     if (addr & 1)
 474         *cur = (*cur & 0xff) | (val << 8);
 475     else
 476         *cur = (*cur & 0xff00) | (val & 0xff);
 477 }
 478
 479 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 480 {
 481     uint16_t x1, x0 = val & 0xff;
 482     int shift = (addr & 1) ? 8 : 0;
 483
 484     x1 = (*cur >> shift) & 0xff;
 485
 486     x1 = x1 & ~x0;
 487
 488     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 489 }
 490
 491 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 492 {
 493     struct gpe_regs *g = opaque;
 494     switch (addr) {
 495         case GPE_BASE:
 496         case GPE_BASE + 1:
 497             gpe_reset_val(&g->sts, addr, val);
 498             break;
 499         case GPE_BASE + 2:
 500         case GPE_BASE + 3:
 501             gpe_write_val(&g->en, addr, val);
 502             break;
 503         default:
 504             break;
 505    }
 506
 507     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 508 }
 509
 510 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 511 {
 512     uint32_t val = 0;
 513     struct pci_status *g = opaque;
 514     switch (addr) {
 515         case PCI_BASE:
 516             val = g->up;
 517             break;
 518         case PCI_BASE + 4:
 519             val = g->down;
 520             break;
 521         default:
 522             break;
 523     }
 524
 525     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 526     return val;
 527 }
 528
 529 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 530 {
 531     struct pci_status *g = opaque;
 532     switch (addr) {
 533         case PCI_BASE:
 534             g->up = val;
 535             break;
 536         case PCI_BASE + 4:
 537             g->down = val;
 538             break;
 539    }
 540
 541     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 542 }
 543
 544 static uint32_t pciej_read(void *opaque, uint32_t addr)
 545 {
 546     PIIX4_DPRINTF("pciej read %x\n", addr);
 547     return 0;
 548 }
 549
 550 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 551 {
 552     BusState *bus = opaque;
 553     DeviceState *qdev, *next;
 554     PCIDevice *dev;
 555     int slot = ffs(val) - 1;
 556
 557     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 558         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 559         if (PCI_SLOT(dev->devfn) == slot) {
 560             qdev_free(qdev);
 561         }
 562     }
 563
 564
 565     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 566 }
 567
 568 extern const char *global_cpu_model;
 569
 570 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state);
 571
 572 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 573 {
 574     struct gpe_regs *gpe = &s->gpe;
 575     struct pci_status *pci0_status = &s->pci0_status;
 576     int i = 0, cpus = smp_cpus;
 577
 578     while (cpus > 0) {
 579         gpe->cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 580         cpus -= 8;
 581     }
 582
 583     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe);
 584     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, gpe);
 585
 586     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, gpe);
 587     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, gpe);
 588
 589     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 590     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 591
 592     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 593     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 594
 595     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 596 }
 597
 598 #if defined(TARGET_I386)
 599 static void enable_processor(struct gpe_regs *g, int cpu)
 600 {
 601     g->sts |= 4;
 602     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 603 }
 604
 605 static void disable_processor(struct gpe_regs *g, int cpu)
 606 {
 607     g->sts |= 4;
 608     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 609 }
 610
 611 void qemu_system_cpu_hot_add(int cpu, int state)
 612 {
 613     CPUState *env;
 614     PIIX4PMState *s = global_piix4_pm_state;
 615
 616     if (state && !qemu_get_cpu(cpu)) {
 617         env = pc_new_cpu(global_cpu_model);
 618         if (!env) {
 619             fprintf(stderr, "cpu %d creation failed\n", cpu);
 620             return;
 621         }
 622         env->cpuid_apic_id = cpu;
 623     }
 624
 625     if (state)
 626         enable_processor(&s->gpe, cpu);
 627     else
 628         disable_processor(&s->gpe, cpu);
 629     if (s->gpe.en & 4) {
 630         qemu_set_irq(s->irq, 1);
 631         qemu_set_irq(s->irq, 0);
 632     }
 633 }
 634 #endif
 635
 636 static void enable_device(PIIX4PMState *s, int slot)
 637 {
 638     s->gpe.sts |= 2;
 639     s->pci0_status.up |= (1 << slot);
 640 }
 641
 642 static void disable_device(PIIX4PMState *s, int slot)
 643 {
 644     s->gpe.sts |= 2;
 645     s->pci0_status.down |= (1 << slot);
 646 }
 647
 648 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state)
 649 {
 650     int slot = PCI_SLOT(dev->devfn);
 651     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 652                                 DO_UPCAST(PCIDevice, qdev, qdev));
 653
 654     s->pci0_status.up = 0;
 655     s->pci0_status.down = 0;
 656     if (state) {
 657         enable_device(s, slot);
 658     } else {
 659         disable_device(s, slot);
 660     }
 661     if (s->gpe.en & 2) {
 662         qemu_set_irq(s->irq, 1);
 663         qemu_set_irq(s->irq, 0);
 664     }
 665     return 0;
 666 }