target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "ioport.h"
  29
  30 #ifdef CONFIG_KVM_PARA
  31 #include <linux/kvm_para.h>
  32 #endif
  33 //
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define dprintf(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define dprintf(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifdef KVM_CAP_EXT_CPUID
  48
  49 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  50 {
  51     struct kvm_cpuid2 *cpuid;
  52     int r, size;
  53
  54     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  55     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  56     cpuid->nent = max;
  57     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  58     if (r == 0 && cpuid->nent >= max) {
  59         r = -E2BIG;
  60     }
  61     if (r < 0) {
  62         if (r == -E2BIG) {
  63             qemu_free(cpuid);
  64             return NULL;
  65         } else {
  66             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  67                     strerror(-r));
  68             exit(1);
  69         }
  70     }
  71     return cpuid;
  72 }
  73
  74 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  75 {
  76     struct kvm_cpuid2 *cpuid;
  77     int i, max;
  78     uint32_t ret = 0;
  79     uint32_t cpuid_1_edx;
  80
  81     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  82         return -1U;
  83     }
  84
  85     max = 1;
  86     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  87         max *= 2;
  88     }
  89
  90     for (i = 0; i < cpuid->nent; ++i) {
  91         if (cpuid->entries[i].function == function) {
  92             switch (reg) {
  93             case R_EAX:
  94                 ret = cpuid->entries[i].eax;
  95                 break;
  96             case R_EBX:
  97                 ret = cpuid->entries[i].ebx;
  98                 break;
  99             case R_ECX:
 100                 ret = cpuid->entries[i].ecx;
 101                 break;
 102             case R_EDX:
 103                 ret = cpuid->entries[i].edx;
 104                 switch (function) {
 105                 case 1:
 106                     /* KVM before 2.6.30 misreports the following features */
 107                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 108                     break;
 109                 case 0x80000001:
 110                     /* On Intel, kvm returns cpuid according to the Intel spec,
 111                      * so add missing bits according to the AMD spec:
 112                      */
 113                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 114                     ret |= cpuid_1_edx & 0xdfeff7ff;
 115                     break;
 116                 }
 117                 break;
 118             }
 119         }
 120     }
 121
 122     qemu_free(cpuid);
 123
 124     return ret;
 125 }
 126
 127 #else
 128
 129 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 130 {
 131     return -1U;
 132 }
 133
 134 #endif
 135
 136 #ifdef KVM_UPSTREAM
 137
 138 #ifdef CONFIG_KVM_PARA
 139 struct kvm_para_features {
 140         int cap;
 141         int feature;
 142 } para_features[] = {
 143 #ifdef KVM_CAP_CLOCKSOURCE
 144         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 145 #endif
 146 #ifdef KVM_CAP_NOP_IO_DELAY
 147         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 148 #endif
 149 #ifdef KVM_CAP_PV_MMU
 150         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 151 #endif
 152         { -1, -1 }
 153 };
 154
 155 static int get_para_features(CPUState *env)
 156 {
 157         int i, features = 0;
 158
 159         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 160                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 161                         features |= (1 << para_features[i].feature);
 162         }
 163
 164         return features;
 165 }
 166 #endif
 167
 168 int kvm_arch_init_vcpu(CPUState *env)
 169 {
 170     struct {
 171         struct kvm_cpuid2 cpuid;
 172         struct kvm_cpuid_entry2 entries[100];
 173     } __attribute__((packed)) cpuid_data;
 174     uint32_t limit, i, j, cpuid_i;
 175     uint32_t unused;
 176     struct kvm_cpuid_entry2 *c;
 177 #ifdef KVM_CPUID_SIGNATURE
 178     uint32_t signature[3];
 179 #endif
 180
 181     env->mp_state = KVM_MP_STATE_RUNNABLE;
 182
 183     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 184
 185     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 186     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, R_ECX);
 187     env->cpuid_ext_features |= i;
 188
 189     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 190                                                              R_EDX);
 191     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 192                                                              R_ECX);
 193
 194     cpuid_i = 0;
 195
 196 #ifdef CONFIG_KVM_PARA
 197     /* Paravirtualization CPUIDs */
 198     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 199     c = &cpuid_data.entries[cpuid_i++];
 200     memset(c, 0, sizeof(*c));
 201     c->function = KVM_CPUID_SIGNATURE;
 202     c->eax = 0;
 203     c->ebx = signature[0];
 204     c->ecx = signature[1];
 205     c->edx = signature[2];
 206
 207     c = &cpuid_data.entries[cpuid_i++];
 208     memset(c, 0, sizeof(*c));
 209     c->function = KVM_CPUID_FEATURES;
 210     c->eax = env->cpuid_kvm_features & get_para_features(env);
 211 #endif
 212
 213     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 214
 215     for (i = 0; i <= limit; i++) {
 216         c = &cpuid_data.entries[cpuid_i++];
 217
 218         switch (i) {
 219         case 2: {
 220             /* Keep reading function 2 till all the input is received */
 221             int times;
 222
 223             c->function = i;
 224             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 225                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 226             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 227             times = c->eax & 0xff;
 228
 229             for (j = 1; j < times; ++j) {
 230                 c = &cpuid_data.entries[cpuid_i++];
 231                 c->function = i;
 232                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 233                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 234             }
 235             break;
 236         }
 237         case 4:
 238         case 0xb:
 239         case 0xd:
 240             for (j = 0; ; j++) {
 241                 c->function = i;
 242                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 243                 c->index = j;
 244                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 245
 246                 if (i == 4 && c->eax == 0)
 247                     break;
 248                 if (i == 0xb && !(c->ecx & 0xff00))
 249                     break;
 250                 if (i == 0xd && c->eax == 0)
 251                     break;
 252
 253                 c = &cpuid_data.entries[cpuid_i++];
 254             }
 255             break;
 256         default:
 257             c->function = i;
 258             c->flags = 0;
 259             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 260             break;
 261         }
 262     }
 263     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 264
 265     for (i = 0x80000000; i <= limit; i++) {
 266         c = &cpuid_data.entries[cpuid_i++];
 267
 268         c->function = i;
 269         c->flags = 0;
 270         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 271     }
 272
 273     cpuid_data.cpuid.nent = cpuid_i;
 274
 275     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 276 }
 277
 278 #endif
 279 void kvm_arch_reset_vcpu(CPUState *env)
 280 {
 281     env->exception_injected = -1;
 282     env->interrupt_injected = -1;
 283     env->nmi_injected = 0;
 284     env->nmi_pending = 0;
 285 }
 286 #ifdef KVM_UPSTREAM
 287
 288 static int kvm_has_msr_star(CPUState *env)
 289 {
 290     static int has_msr_star;
 291     int ret;
 292
 293     /* first time */
 294     if (has_msr_star == 0) {
 295         struct kvm_msr_list msr_list, *kvm_msr_list;
 296
 297         has_msr_star = -1;
 298
 299         /* Obtain MSR list from KVM.  These are the MSRs that we must
 300          * save/restore */
 301         msr_list.nmsrs = 0;
 302         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 303         if (ret < 0 && ret != -E2BIG) {
 304             return 0;
 305         }
 306         /* Old kernel modules had a bug and could write beyond the provided
 307            memory. Allocate at least a safe amount of 1K. */
 308         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 309                                               msr_list.nmsrs *
 310                                               sizeof(msr_list.indices[0])));
 311
 312         kvm_msr_list->nmsrs = msr_list.nmsrs;
 313         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 314         if (ret >= 0) {
 315             int i;
 316
 317             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 318                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 319                     has_msr_star = 1;
 320                     break;
 321                 }
 322             }
 323         }
 324
 325         free(kvm_msr_list);
 326     }
 327
 328     if (has_msr_star == 1)
 329         return 1;
 330     return 0;
 331 }
 332
 333 int kvm_arch_init(KVMState *s, int smp_cpus)
 334 {
 335     int ret;
 336
 337     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 338      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 339      * must be part of guest physical memory, we need to allocate it.  Older
 340      * versions of KVM just assumed that it would be at the end of physical
 341      * memory but that doesn't work with more than 4GB of memory.  We simply
 342      * refuse to work with those older versions of KVM. */
 343     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 344     if (ret <= 0) {
 345         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 346         return ret;
 347     }
 348
 349     /* this address is 3 pages before the bios, and the bios should present
 350      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 351      * this?
 352      */
 353     /*
 354      * Tell fw_cfg to notify the BIOS to reserve the range.
 355      */
 356     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 357         perror("e820_add_entry() table is full");
 358         exit(1);
 359     }
 360     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 361 }
 362
 363 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 364 {
 365     lhs->selector = rhs->selector;
 366     lhs->base = rhs->base;
 367     lhs->limit = rhs->limit;
 368     lhs->type = 3;
 369     lhs->present = 1;
 370     lhs->dpl = 3;
 371     lhs->db = 0;
 372     lhs->s = 1;
 373     lhs->l = 0;
 374     lhs->g = 0;
 375     lhs->avl = 0;
 376     lhs->unusable = 0;
 377 }
 378
 379 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 380 {
 381     unsigned flags = rhs->flags;
 382     lhs->selector = rhs->selector;
 383     lhs->base = rhs->base;
 384     lhs->limit = rhs->limit;
 385     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 386     lhs->present = (flags & DESC_P_MASK) != 0;
 387     lhs->dpl = rhs->selector & 3;
 388     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 389     lhs->s = (flags & DESC_S_MASK) != 0;
 390     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 391     lhs->g = (flags & DESC_G_MASK) != 0;
 392     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 393     lhs->unusable = 0;
 394 }
 395
 396 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 397 {
 398     lhs->selector = rhs->selector;
 399     lhs->base = rhs->base;
 400     lhs->limit = rhs->limit;
 401     lhs->flags =
 402         (rhs->type << DESC_TYPE_SHIFT)
 403         | (rhs->present * DESC_P_MASK)
 404         | (rhs->dpl << DESC_DPL_SHIFT)
 405         | (rhs->db << DESC_B_SHIFT)
 406         | (rhs->s * DESC_S_MASK)
 407         | (rhs->l << DESC_L_SHIFT)
 408         | (rhs->g * DESC_G_MASK)
 409         | (rhs->avl * DESC_AVL_MASK);
 410 }
 411
 412 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 413 {
 414     if (set)
 415         *kvm_reg = *qemu_reg;
 416     else
 417         *qemu_reg = *kvm_reg;
 418 }
 419
 420 static int kvm_getput_regs(CPUState *env, int set)
 421 {
 422     struct kvm_regs regs;
 423     int ret = 0;
 424
 425     if (!set) {
 426         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 427         if (ret < 0)
 428             return ret;
 429     }
 430
 431     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 432     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 433     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 434     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 435     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 436     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 437     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 438     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 439 #ifdef TARGET_X86_64
 440     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 441     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 442     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 443     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 444     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 445     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 446     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 447     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 448 #endif
 449
 450     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 451     kvm_getput_reg(&regs.rip, &env->eip, set);
 452
 453     if (set)
 454         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 455
 456     return ret;
 457 }
 458
 459 static int kvm_put_fpu(CPUState *env)
 460 {
 461     struct kvm_fpu fpu;
 462     int i;
 463
 464     memset(&fpu, 0, sizeof fpu);
 465     fpu.fsw = env->fpus & ~(7 << 11);
 466     fpu.fsw |= (env->fpstt & 7) << 11;
 467     fpu.fcw = env->fpuc;
 468     for (i = 0; i < 8; ++i)
 469         fpu.ftwx |= (!env->fptags[i]) << i;
 470     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 471     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 472     fpu.mxcsr = env->mxcsr;
 473
 474     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 475 }
 476
 477 static int kvm_put_sregs(CPUState *env)
 478 {
 479     struct kvm_sregs sregs;
 480
 481     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 482     if (env->interrupt_injected >= 0) {
 483         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 484                 (uint64_t)1 << (env->interrupt_injected % 64);
 485     }
 486
 487     if ((env->eflags & VM_MASK)) {
 488             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 489             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 490             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 491             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 492             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 493             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 494     } else {
 495             set_seg(&sregs.cs, &env->segs[R_CS]);
 496             set_seg(&sregs.ds, &env->segs[R_DS]);
 497             set_seg(&sregs.es, &env->segs[R_ES]);
 498             set_seg(&sregs.fs, &env->segs[R_FS]);
 499             set_seg(&sregs.gs, &env->segs[R_GS]);
 500             set_seg(&sregs.ss, &env->segs[R_SS]);
 501
 502             if (env->cr[0] & CR0_PE_MASK) {
 503                 /* force ss cpl to cs cpl */
 504                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 505                         (sregs.cs.selector & 3);
 506                 sregs.ss.dpl = sregs.ss.selector & 3;
 507             }
 508     }
 509
 510     set_seg(&sregs.tr, &env->tr);
 511     set_seg(&sregs.ldt, &env->ldt);
 512
 513     sregs.idt.limit = env->idt.limit;
 514     sregs.idt.base = env->idt.base;
 515     sregs.gdt.limit = env->gdt.limit;
 516     sregs.gdt.base = env->gdt.base;
 517
 518     sregs.cr0 = env->cr[0];
 519     sregs.cr2 = env->cr[2];
 520     sregs.cr3 = env->cr[3];
 521     sregs.cr4 = env->cr[4];
 522
 523     sregs.cr8 = cpu_get_apic_tpr(env);
 524     sregs.apic_base = cpu_get_apic_base(env);
 525
 526     sregs.efer = env->efer;
 527
 528     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 529 }
 530
 531 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 532                               uint32_t index, uint64_t value)
 533 {
 534     entry->index = index;
 535     entry->data = value;
 536 }
 537
 538 static int kvm_put_msrs(CPUState *env, int level)
 539 {
 540     struct {
 541         struct kvm_msrs info;
 542         struct kvm_msr_entry entries[100];
 543     } msr_data;
 544     struct kvm_msr_entry *msrs = msr_data.entries;
 545     int n = 0;
 546
 547     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 548     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 549     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 550     if (kvm_has_msr_star(env))
 551         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 552     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 553 #ifdef TARGET_X86_64
 554     /* FIXME if lm capable */
 555     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 556     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 557     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 558     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 559 #endif
 560     if (level == KVM_PUT_FULL_STATE) {
 561         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 562         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 563                           env->system_time_msr);
 564         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 565     }
 566
 567     msr_data.info.nmsrs = n;
 568
 569     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 570
 571 }
 572
 573
 574 static int kvm_get_fpu(CPUState *env)
 575 {
 576     struct kvm_fpu fpu;
 577     int i, ret;
 578
 579     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 580     if (ret < 0)
 581         return ret;
 582
 583     env->fpstt = (fpu.fsw >> 11) & 7;
 584     env->fpus = fpu.fsw;
 585     env->fpuc = fpu.fcw;
 586     for (i = 0; i < 8; ++i)
 587         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 588     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 589     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 590     env->mxcsr = fpu.mxcsr;
 591
 592     return 0;
 593 }
 594
 595 static int kvm_get_sregs(CPUState *env)
 596 {
 597     struct kvm_sregs sregs;
 598     uint32_t hflags;
 599     int bit, i, ret;
 600
 601     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 602     if (ret < 0)
 603         return ret;
 604
 605     /* There can only be one pending IRQ set in the bitmap at a time, so try
 606        to find it and save its number instead (-1 for none). */
 607     env->interrupt_injected = -1;
 608     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 609         if (sregs.interrupt_bitmap[i]) {
 610             bit = ctz64(sregs.interrupt_bitmap[i]);
 611             env->interrupt_injected = i * 64 + bit;
 612             break;
 613         }
 614     }
 615
 616     get_seg(&env->segs[R_CS], &sregs.cs);
 617     get_seg(&env->segs[R_DS], &sregs.ds);
 618     get_seg(&env->segs[R_ES], &sregs.es);
 619     get_seg(&env->segs[R_FS], &sregs.fs);
 620     get_seg(&env->segs[R_GS], &sregs.gs);
 621     get_seg(&env->segs[R_SS], &sregs.ss);
 622
 623     get_seg(&env->tr, &sregs.tr);
 624     get_seg(&env->ldt, &sregs.ldt);
 625
 626     env->idt.limit = sregs.idt.limit;
 627     env->idt.base = sregs.idt.base;
 628     env->gdt.limit = sregs.gdt.limit;
 629     env->gdt.base = sregs.gdt.base;
 630
 631     env->cr[0] = sregs.cr0;
 632     env->cr[2] = sregs.cr2;
 633     env->cr[3] = sregs.cr3;
 634     env->cr[4] = sregs.cr4;
 635
 636     cpu_set_apic_base(env, sregs.apic_base);
 637
 638     env->efer = sregs.efer;
 639     //cpu_set_apic_tpr(env, sregs.cr8);
 640
 641 #define HFLAG_COPY_MASK ~( \
 642                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 643                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 644                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 645                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 646
 647
 648
 649     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 650     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 651     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 652             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 653     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 654     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 655             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 656
 657     if (env->efer & MSR_EFER_LMA) {
 658         hflags |= HF_LMA_MASK;
 659     }
 660
 661     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 662         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 663     } else {
 664         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 665                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 666         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 667                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 668         if (!(env->cr[0] & CR0_PE_MASK) ||
 669                    (env->eflags & VM_MASK) ||
 670                    !(hflags & HF_CS32_MASK)) {
 671                 hflags |= HF_ADDSEG_MASK;
 672             } else {
 673                 hflags |= ((env->segs[R_DS].base |
 674                                 env->segs[R_ES].base |
 675                                 env->segs[R_SS].base) != 0) <<
 676                     HF_ADDSEG_SHIFT;
 677             }
 678     }
 679     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 680
 681     return 0;
 682 }
 683
 684 static int kvm_get_msrs(CPUState *env)
 685 {
 686     struct {
 687         struct kvm_msrs info;
 688         struct kvm_msr_entry entries[100];
 689     } msr_data;
 690     struct kvm_msr_entry *msrs = msr_data.entries;
 691     int ret, i, n;
 692
 693     n = 0;
 694     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 695     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 696     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 697     if (kvm_has_msr_star(env))
 698         msrs[n++].index = MSR_STAR;
 699     msrs[n++].index = MSR_IA32_TSC;
 700     msrs[n++].index = MSR_VM_HSAVE_PA;
 701 #ifdef TARGET_X86_64
 702     /* FIXME lm_capable_kernel */
 703     msrs[n++].index = MSR_CSTAR;
 704     msrs[n++].index = MSR_KERNELGSBASE;
 705     msrs[n++].index = MSR_FMASK;
 706     msrs[n++].index = MSR_LSTAR;
 707 #endif
 708     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 709     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 710
 711     msr_data.info.nmsrs = n;
 712     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 713     if (ret < 0)
 714         return ret;
 715
 716     for (i = 0; i < ret; i++) {
 717         switch (msrs[i].index) {
 718         case MSR_IA32_SYSENTER_CS:
 719             env->sysenter_cs = msrs[i].data;
 720             break;
 721         case MSR_IA32_SYSENTER_ESP:
 722             env->sysenter_esp = msrs[i].data;
 723             break;
 724         case MSR_IA32_SYSENTER_EIP:
 725             env->sysenter_eip = msrs[i].data;
 726             break;
 727         case MSR_STAR:
 728             env->star = msrs[i].data;
 729             break;
 730 #ifdef TARGET_X86_64
 731         case MSR_CSTAR:
 732             env->cstar = msrs[i].data;
 733             break;
 734         case MSR_KERNELGSBASE:
 735             env->kernelgsbase = msrs[i].data;
 736             break;
 737         case MSR_FMASK:
 738             env->fmask = msrs[i].data;
 739             break;
 740         case MSR_LSTAR:
 741             env->lstar = msrs[i].data;
 742             break;
 743 #endif
 744         case MSR_IA32_TSC:
 745             env->tsc = msrs[i].data;
 746             break;
 747         case MSR_KVM_SYSTEM_TIME:
 748             env->system_time_msr = msrs[i].data;
 749             break;
 750         case MSR_KVM_WALL_CLOCK:
 751             env->wall_clock_msr = msrs[i].data;
 752             break;
 753         case MSR_VM_HSAVE_PA:
 754             env->vm_hsave = msrs[i].data;
 755             break;
 756         }
 757     }
 758
 759     return 0;
 760 }
 761
 762 static int kvm_put_mp_state(CPUState *env)
 763 {
 764     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 765
 766     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 767 }
 768
 769 static int kvm_get_mp_state(CPUState *env)
 770 {
 771     struct kvm_mp_state mp_state;
 772     int ret;
 773
 774     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 775     if (ret < 0) {
 776         return ret;
 777     }
 778     env->mp_state = mp_state.mp_state;
 779     return 0;
 780 }
 781 #endif
 782
 783 static int kvm_put_vcpu_events(CPUState *env, int level)
 784 {
 785 #ifdef KVM_CAP_VCPU_EVENTS
 786     struct kvm_vcpu_events events;
 787
 788     if (!kvm_has_vcpu_events()) {
 789         return 0;
 790     }
 791
 792     events.exception.injected = (env->exception_injected >= 0);
 793     events.exception.nr = env->exception_injected;
 794     events.exception.has_error_code = env->has_error_code;
 795     events.exception.error_code = env->error_code;
 796
 797     events.interrupt.injected = (env->interrupt_injected >= 0);
 798     events.interrupt.nr = env->interrupt_injected;
 799     events.interrupt.soft = env->soft_interrupt;
 800
 801     events.nmi.injected = env->nmi_injected;
 802     events.nmi.pending = env->nmi_pending;
 803     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 804
 805     events.sipi_vector = env->sipi_vector;
 806
 807     events.flags = 0;
 808     if (level >= KVM_PUT_RESET_STATE) {
 809         events.flags |=
 810             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 811     }
 812
 813     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 814 #else
 815     return 0;
 816 #endif
 817 }
 818
 819 static int kvm_get_vcpu_events(CPUState *env)
 820 {
 821 #ifdef KVM_CAP_VCPU_EVENTS
 822     struct kvm_vcpu_events events;
 823     int ret;
 824
 825     if (!kvm_has_vcpu_events()) {
 826         return 0;
 827     }
 828
 829     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 830     if (ret < 0) {
 831        return ret;
 832     }
 833     env->exception_injected =
 834        events.exception.injected ? events.exception.nr : -1;
 835     env->has_error_code = events.exception.has_error_code;
 836     env->error_code = events.exception.error_code;
 837
 838     env->interrupt_injected =
 839         events.interrupt.injected ? events.interrupt.nr : -1;
 840     env->soft_interrupt = events.interrupt.soft;
 841
 842     env->nmi_injected = events.nmi.injected;
 843     env->nmi_pending = events.nmi.pending;
 844     if (events.nmi.masked) {
 845         env->hflags2 |= HF2_NMI_MASK;
 846     } else {
 847         env->hflags2 &= ~HF2_NMI_MASK;
 848     }
 849
 850     env->sipi_vector = events.sipi_vector;
 851 #endif
 852
 853     return 0;
 854 }
 855
 856 static int kvm_guest_debug_workarounds(CPUState *env)
 857 {
 858     int ret = 0;
 859 #ifdef KVM_CAP_SET_GUEST_DEBUG
 860     unsigned long reinject_trap = 0;
 861
 862     if (!kvm_has_vcpu_events()) {
 863         if (env->exception_injected == 1) {
 864             reinject_trap = KVM_GUESTDBG_INJECT_DB;
 865         } else if (env->exception_injected == 3) {
 866             reinject_trap = KVM_GUESTDBG_INJECT_BP;
 867         }
 868         env->exception_injected = -1;
 869     }
 870
 871     /*
 872      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
 873      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
 874      * by updating the debug state once again if single-stepping is on.
 875      * Another reason to call kvm_update_guest_debug here is a pending debug
 876      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
 877      * reinject them via SET_GUEST_DEBUG.
 878      */
 879     if (reinject_trap ||
 880         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
 881         ret = kvm_update_guest_debug(env, reinject_trap);
 882     }
 883 #endif /* KVM_CAP_SET_GUEST_DEBUG */
 884     return ret;
 885 }
 886
 887 #ifdef KVM_UPSTREAM
 888 static int kvm_put_debugregs(CPUState *env)
 889 {
 890 #ifdef KVM_CAP_DEBUGREGS
 891     struct kvm_debugregs dbgregs;
 892     int i;
 893
 894     if (!kvm_has_debugregs()) {
 895         return 0;
 896     }
 897
 898     for (i = 0; i < 4; i++) {
 899         dbgregs.db[i] = env->dr[i];
 900     }
 901     dbgregs.dr6 = env->dr[6];
 902     dbgregs.dr7 = env->dr[7];
 903     dbgregs.flags = 0;
 904
 905     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
 906 #else
 907     return 0;
 908 #endif
 909 }
 910
 911 static int kvm_get_debugregs(CPUState *env)
 912 {
 913 #ifdef KVM_CAP_DEBUGREGS
 914     struct kvm_debugregs dbgregs;
 915     int i, ret;
 916
 917     if (!kvm_has_debugregs()) {
 918         return 0;
 919     }
 920
 921     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
 922     if (ret < 0) {
 923        return ret;
 924     }
 925     for (i = 0; i < 4; i++) {
 926         env->dr[i] = dbgregs.db[i];
 927     }
 928     env->dr[4] = env->dr[6] = dbgregs.dr6;
 929     env->dr[5] = env->dr[7] = dbgregs.dr7;
 930 #endif
 931
 932     return 0;
 933 }
 934
 935 int kvm_arch_put_registers(CPUState *env, int level)
 936 {
 937     int ret;
 938
 939     ret = kvm_getput_regs(env, 1);
 940     if (ret < 0)
 941         return ret;
 942
 943     ret = kvm_put_fpu(env);
 944     if (ret < 0)
 945         return ret;
 946
 947     ret = kvm_put_sregs(env);
 948     if (ret < 0)
 949         return ret;
 950
 951     ret = kvm_put_msrs(env, level);
 952     if (ret < 0)
 953         return ret;
 954
 955     if (level >= KVM_PUT_RESET_STATE) {
 956         ret = kvm_put_mp_state(env);
 957         if (ret < 0)
 958             return ret;
 959     }
 960
 961     ret = kvm_put_vcpu_events(env, level);
 962     if (ret < 0)
 963         return ret;
 964
 965     /* must be last */
 966     ret = kvm_guest_debug_workarounds(env);
 967     if (ret < 0)
 968         return ret;
 969
 970     return 0;
 971 }
 972
 973 int kvm_arch_get_registers(CPUState *env)
 974 {
 975     int ret;
 976
 977     ret = kvm_getput_regs(env, 0);
 978     if (ret < 0)
 979         return ret;
 980
 981     ret = kvm_get_fpu(env);
 982     if (ret < 0)
 983         return ret;
 984
 985     ret = kvm_get_sregs(env);
 986     if (ret < 0)
 987         return ret;
 988
 989     ret = kvm_get_msrs(env);
 990     if (ret < 0)
 991         return ret;
 992
 993     ret = kvm_get_mp_state(env);
 994     if (ret < 0)
 995         return ret;
 996
 997     ret = kvm_get_vcpu_events(env);
 998     if (ret < 0)
 999         return ret;
1000
1001     ret = kvm_put_debugregs(env);
1002     if (ret < 0)
1003         return ret;
1004
1005     ret = kvm_get_debugregs(env);
1006     if (ret < 0)
1007         return ret;
1008
1009     return 0;
1010 }
1011
1012 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1013 {
1014     /* Try to inject an interrupt if the guest can accept it */
1015     if (run->ready_for_interrupt_injection &&
1016         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1017         (env->eflags & IF_MASK)) {
1018         int irq;
1019
1020         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1021         irq = cpu_get_pic_interrupt(env);
1022         if (irq >= 0) {
1023             struct kvm_interrupt intr;
1024             intr.irq = irq;
1025             /* FIXME: errors */
1026             dprintf("injected interrupt %d\n", irq);
1027             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1028         }
1029     }
1030
1031     /* If we have an interrupt but the guest is not ready to receive an
1032      * interrupt, request an interrupt window exit.  This will
1033      * cause a return to userspace as soon as the guest is ready to
1034      * receive interrupts. */
1035     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1036         run->request_interrupt_window = 1;
1037     else
1038         run->request_interrupt_window = 0;
1039
1040     dprintf("setting tpr\n");
1041     run->cr8 = cpu_get_apic_tpr(env);
1042
1043     return 0;
1044 }
1045 #endif
1046
1047 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1048 {
1049     if (run->if_flag)
1050         env->eflags |= IF_MASK;
1051     else
1052         env->eflags &= ~IF_MASK;
1053
1054     cpu_set_apic_tpr(env, run->cr8);
1055     cpu_set_apic_base(env, run->apic_base);
1056
1057     return 0;
1058 }
1059
1060 #ifdef KVM_UPSTREAM
1061 static int kvm_handle_halt(CPUState *env)
1062 {
1063     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1064           (env->eflags & IF_MASK)) &&
1065         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1066         env->halted = 1;
1067         env->exception_index = EXCP_HLT;
1068         return 0;
1069     }
1070
1071     return 1;
1072 }
1073
1074 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1075 {
1076     int ret = 0;
1077
1078     switch (run->exit_reason) {
1079     case KVM_EXIT_HLT:
1080         dprintf("handle_hlt\n");
1081         ret = kvm_handle_halt(env);
1082         break;
1083     }
1084
1085     return ret;
1086 }
1087 #endif
1088
1089 #ifdef KVM_CAP_SET_GUEST_DEBUG
1090 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1091 {
1092     static const uint8_t int3 = 0xcc;
1093
1094     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1095         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1096         return -EINVAL;
1097     return 0;
1098 }
1099
1100 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1101 {
1102     uint8_t int3;
1103
1104     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1105         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1106         return -EINVAL;
1107     return 0;
1108 }
1109
1110 static struct {
1111     target_ulong addr;
1112     int len;
1113     int type;
1114 } hw_breakpoint[4];
1115
1116 static int nb_hw_breakpoint;
1117
1118 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1119 {
1120     int n;
1121
1122     for (n = 0; n < nb_hw_breakpoint; n++)
1123         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1124             (hw_breakpoint[n].len == len || len == -1))
1125             return n;
1126     return -1;
1127 }
1128
1129 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1130                                   target_ulong len, int type)
1131 {
1132     switch (type) {
1133     case GDB_BREAKPOINT_HW:
1134         len = 1;
1135         break;
1136     case GDB_WATCHPOINT_WRITE:
1137     case GDB_WATCHPOINT_ACCESS:
1138         switch (len) {
1139         case 1:
1140             break;
1141         case 2:
1142         case 4:
1143         case 8:
1144             if (addr & (len - 1))
1145                 return -EINVAL;
1146             break;
1147         default:
1148             return -EINVAL;
1149         }
1150         break;
1151     default:
1152         return -ENOSYS;
1153     }
1154
1155     if (nb_hw_breakpoint == 4)
1156         return -ENOBUFS;
1157
1158     if (find_hw_breakpoint(addr, len, type) >= 0)
1159         return -EEXIST;
1160
1161     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1162     hw_breakpoint[nb_hw_breakpoint].len = len;
1163     hw_breakpoint[nb_hw_breakpoint].type = type;
1164     nb_hw_breakpoint++;
1165
1166     return 0;
1167 }
1168
1169 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1170                                   target_ulong len, int type)
1171 {
1172     int n;
1173
1174     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1175     if (n < 0)
1176         return -ENOENT;
1177
1178     nb_hw_breakpoint--;
1179     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1180
1181     return 0;
1182 }
1183
1184 void kvm_arch_remove_all_hw_breakpoints(void)
1185 {
1186     nb_hw_breakpoint = 0;
1187 }
1188
1189 static CPUWatchpoint hw_watchpoint;
1190
1191 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1192 {
1193     int handle = 0;
1194     int n;
1195
1196     if (arch_info->exception == 1) {
1197         if (arch_info->dr6 & (1 << 14)) {
1198             if (cpu_single_env->singlestep_enabled)
1199                 handle = 1;
1200         } else {
1201             for (n = 0; n < 4; n++)
1202                 if (arch_info->dr6 & (1 << n))
1203                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1204                     case 0x0:
1205                         handle = 1;
1206                         break;
1207                     case 0x1:
1208                         handle = 1;
1209                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1210                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1211                         hw_watchpoint.flags = BP_MEM_WRITE;
1212                         break;
1213                     case 0x3:
1214                         handle = 1;
1215                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1216                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1217                         hw_watchpoint.flags = BP_MEM_ACCESS;
1218                         break;
1219                     }
1220         }
1221     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1222         handle = 1;
1223
1224     if (!handle) {
1225         cpu_synchronize_state(cpu_single_env);
1226         assert(cpu_single_env->exception_injected == -1);
1227
1228         cpu_single_env->exception_injected = arch_info->exception;
1229         cpu_single_env->has_error_code = 0;
1230     }
1231
1232     return handle;
1233 }
1234
1235 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1236 {
1237     const uint8_t type_code[] = {
1238         [GDB_BREAKPOINT_HW] = 0x0,
1239         [GDB_WATCHPOINT_WRITE] = 0x1,
1240         [GDB_WATCHPOINT_ACCESS] = 0x3
1241     };
1242     const uint8_t len_code[] = {
1243         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1244     };
1245     int n;
1246
1247     if (kvm_sw_breakpoints_active(env))
1248         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1249
1250     if (nb_hw_breakpoint > 0) {
1251         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1252         dbg->arch.debugreg[7] = 0x0600;
1253         for (n = 0; n < nb_hw_breakpoint; n++) {
1254             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1255             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1256                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1257                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1258         }
1259     }
1260 }
1261 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1262
1263 #include "qemu-kvm-x86.c"