2 * qemu/kvm integration, x86 specific code
4 * Copyright (C) 2006-2008 Qumranet Technologies
6 * Licensed under the terms of the GNU GPL version 2 or higher.
10 #include "config-host.h"
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
27 #define MSR_IA32_TSC 0x10
29 static struct kvm_msr_list
*kvm_msr_list
;
30 extern unsigned int kvm_shadow_memory
;
31 static int kvm_has_msr_star
;
32 static int kvm_has_vm_hsave_pa
;
34 static int _lm_capable_kernel
;
36 int kvm_set_tss_addr(kvm_context_t kvm
, unsigned long addr
)
40 * Tell fw_cfg to notify the BIOS to reserve the range.
42 if (e820_add_entry(addr
, 0x4000, E820_RESERVED
) < 0) {
43 perror("e820_add_entry() table is full");
47 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_TSS_ADDR
, addr
);
49 fprintf(stderr
, "kvm_set_tss_addr: %m\n");
55 static int kvm_init_tss(kvm_context_t kvm
)
59 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_TSS_ADDR
);
62 * this address is 3 pages before the bios, and the bios should present
65 r
= kvm_set_tss_addr(kvm
, 0xfeffd000);
67 fprintf(stderr
, "kvm_init_tss: unable to set tss addr\n");
71 fprintf(stderr
, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
76 static int kvm_set_identity_map_addr(kvm_context_t kvm
, uint64_t addr
)
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
81 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_IDENTITY_MAP_ADDR
);
83 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_IDENTITY_MAP_ADDR
, &addr
);
85 fprintf(stderr
, "kvm_set_identity_map_addr: %m\n");
94 static int kvm_init_identity_map_page(kvm_context_t kvm
)
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
99 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_IDENTITY_MAP_ADDR
);
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
105 r
= kvm_set_identity_map_addr(kvm
, 0xfeffc000);
107 fprintf(stderr
, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
116 static int kvm_create_pit(kvm_context_t kvm
)
121 kvm_state
->pit_in_kernel
= 0;
122 if (!kvm
->no_pit_creation
) {
123 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_PIT
);
125 r
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_PIT
);
127 kvm_state
->pit_in_kernel
= 1;
129 fprintf(stderr
, "Create kernel PIC irqchip failed\n");
138 int kvm_arch_create(kvm_context_t kvm
, unsigned long phys_mem_bytes
,
143 r
= kvm_init_tss(kvm
);
148 r
= kvm_init_identity_map_page(kvm
);
153 r
= kvm_create_pit(kvm
);
158 r
= kvm_init_coalesced_mmio(kvm
);
166 #ifdef KVM_EXIT_TPR_ACCESS
168 static int kvm_handle_tpr_access(CPUState
*env
)
170 struct kvm_run
*run
= env
->kvm_run
;
171 kvm_tpr_access_report(env
,
173 run
->tpr_access
.is_write
);
178 int kvm_enable_vapic(CPUState
*env
, uint64_t vapic
)
180 struct kvm_vapic_addr va
= {
184 return kvm_vcpu_ioctl(env
, KVM_SET_VAPIC_ADDR
, &va
);
189 int kvm_arch_run(CPUState
*env
)
192 struct kvm_run
*run
= env
->kvm_run
;
194 switch (run
->exit_reason
) {
195 #ifdef KVM_EXIT_SET_TPR
196 case KVM_EXIT_SET_TPR
:
199 #ifdef KVM_EXIT_TPR_ACCESS
200 case KVM_EXIT_TPR_ACCESS
:
201 r
= kvm_handle_tpr_access(env
);
212 #ifdef KVM_CAP_IRQCHIP
214 int kvm_get_lapic(CPUState
*env
, struct kvm_lapic_state
*s
)
218 if (!kvm_irqchip_in_kernel()) {
222 r
= kvm_vcpu_ioctl(env
, KVM_GET_LAPIC
, s
);
224 fprintf(stderr
, "KVM_GET_LAPIC failed\n");
229 int kvm_set_lapic(CPUState
*env
, struct kvm_lapic_state
*s
)
233 if (!kvm_irqchip_in_kernel()) {
237 r
= kvm_vcpu_ioctl(env
, KVM_SET_LAPIC
, s
);
240 fprintf(stderr
, "KVM_SET_LAPIC failed\n");
249 int kvm_get_pit(kvm_context_t kvm
, struct kvm_pit_state
*s
)
251 if (!kvm_pit_in_kernel()) {
254 return kvm_vm_ioctl(kvm_state
, KVM_GET_PIT
, s
);
257 int kvm_set_pit(kvm_context_t kvm
, struct kvm_pit_state
*s
)
259 if (!kvm_pit_in_kernel()) {
262 return kvm_vm_ioctl(kvm_state
, KVM_SET_PIT
, s
);
265 #ifdef KVM_CAP_PIT_STATE2
266 int kvm_get_pit2(kvm_context_t kvm
, struct kvm_pit_state2
*ps2
)
268 if (!kvm_pit_in_kernel()) {
271 return kvm_vm_ioctl(kvm_state
, KVM_GET_PIT2
, ps2
);
274 int kvm_set_pit2(kvm_context_t kvm
, struct kvm_pit_state2
*ps2
)
276 if (!kvm_pit_in_kernel()) {
279 return kvm_vm_ioctl(kvm_state
, KVM_SET_PIT2
, ps2
);
285 int kvm_has_pit_state2(kvm_context_t kvm
)
289 #ifdef KVM_CAP_PIT_STATE2
290 r
= kvm_check_extension(kvm_state
, KVM_CAP_PIT_STATE2
);
295 void kvm_show_code(CPUState
*env
)
297 #define SHOW_CODE_LEN 50
298 struct kvm_regs regs
;
299 struct kvm_sregs sregs
;
303 char code_str
[SHOW_CODE_LEN
* 3 + 1];
306 r
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
308 perror("KVM_GET_SREGS");
311 r
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
313 perror("KVM_GET_REGS");
316 rip
= sregs
.cs
.base
+ regs
.rip
;
317 back_offset
= regs
.rip
;
318 if (back_offset
> 20) {
322 for (n
= -back_offset
; n
< SHOW_CODE_LEN
-back_offset
; ++n
) {
324 strcat(code_str
, " -->");
326 cpu_physical_memory_rw(rip
+ n
, &code
, 1, 1);
327 sprintf(code_str
+ strlen(code_str
), " %02x", code
);
329 fprintf(stderr
, "code:%s\n", code_str
);
334 * Returns available msr list. User must free.
336 static struct kvm_msr_list
*kvm_get_msr_list(void)
338 struct kvm_msr_list sizer
, *msrs
;
342 r
= kvm_ioctl(kvm_state
, KVM_GET_MSR_INDEX_LIST
, &sizer
);
343 if (r
< 0 && r
!= -E2BIG
) {
346 /* Old kernel modules had a bug and could write beyond the provided
347 memory. Allocate at least a safe amount of 1K. */
348 msrs
= qemu_malloc(MAX(1024, sizeof(*msrs
) +
349 sizer
.nmsrs
* sizeof(*msrs
->indices
)));
351 msrs
->nmsrs
= sizer
.nmsrs
;
352 r
= kvm_ioctl(kvm_state
, KVM_GET_MSR_INDEX_LIST
, msrs
);
361 int kvm_get_msrs(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
363 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
367 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
368 r
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, kmsrs
);
369 memcpy(msrs
, kmsrs
->entries
, n
* sizeof *msrs
);
374 int kvm_set_msrs(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
376 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
380 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
381 r
= kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, kmsrs
);
386 static void print_seg(FILE *file
, const char *name
, struct kvm_segment
*seg
)
389 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
391 name
, seg
->selector
, seg
->base
, seg
->limit
, seg
->present
,
392 seg
->dpl
, seg
->db
, seg
->s
, seg
->type
, seg
->l
, seg
->g
,
396 static void print_dt(FILE *file
, const char *name
, struct kvm_dtable
*dt
)
398 fprintf(stderr
, "%s %llx/%x\n", name
, dt
->base
, dt
->limit
);
401 void kvm_show_regs(CPUState
*env
)
403 struct kvm_regs regs
;
404 struct kvm_sregs sregs
;
407 r
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
409 perror("KVM_GET_REGS");
413 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
414 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
415 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
416 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
417 "rip %016llx rflags %08llx\n",
418 regs
.rax
, regs
.rbx
, regs
.rcx
, regs
.rdx
,
419 regs
.rsi
, regs
.rdi
, regs
.rsp
, regs
.rbp
,
420 regs
.r8
, regs
.r9
, regs
.r10
, regs
.r11
,
421 regs
.r12
, regs
.r13
, regs
.r14
, regs
.r15
,
422 regs
.rip
, regs
.rflags
);
423 r
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
425 perror("KVM_GET_SREGS");
428 print_seg(stderr
, "cs", &sregs
.cs
);
429 print_seg(stderr
, "ds", &sregs
.ds
);
430 print_seg(stderr
, "es", &sregs
.es
);
431 print_seg(stderr
, "ss", &sregs
.ss
);
432 print_seg(stderr
, "fs", &sregs
.fs
);
433 print_seg(stderr
, "gs", &sregs
.gs
);
434 print_seg(stderr
, "tr", &sregs
.tr
);
435 print_seg(stderr
, "ldt", &sregs
.ldt
);
436 print_dt(stderr
, "gdt", &sregs
.gdt
);
437 print_dt(stderr
, "idt", &sregs
.idt
);
438 fprintf(stderr
, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
440 sregs
.cr0
, sregs
.cr2
, sregs
.cr3
, sregs
.cr4
, sregs
.cr8
,
444 static void kvm_set_cr8(CPUState
*env
, uint64_t cr8
)
446 env
->kvm_run
->cr8
= cr8
;
449 int kvm_setup_cpuid(CPUState
*env
, int nent
,
450 struct kvm_cpuid_entry
*entries
)
452 struct kvm_cpuid
*cpuid
;
455 cpuid
= qemu_malloc(sizeof(*cpuid
) + nent
* sizeof(*entries
));
458 memcpy(cpuid
->entries
, entries
, nent
* sizeof(*entries
));
459 r
= kvm_vcpu_ioctl(env
, KVM_SET_CPUID
, cpuid
);
465 int kvm_setup_cpuid2(CPUState
*env
, int nent
,
466 struct kvm_cpuid_entry2
*entries
)
468 struct kvm_cpuid2
*cpuid
;
471 cpuid
= qemu_malloc(sizeof(*cpuid
) + nent
* sizeof(*entries
));
474 memcpy(cpuid
->entries
, entries
, nent
* sizeof(*entries
));
475 r
= kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, cpuid
);
480 int kvm_set_shadow_pages(kvm_context_t kvm
, unsigned int nrshadow_pages
)
482 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
485 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
,
486 KVM_CAP_MMU_SHADOW_CACHE_CONTROL
);
488 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_NR_MMU_PAGES
, nrshadow_pages
);
490 fprintf(stderr
, "kvm_set_shadow_pages: %m\n");
499 int kvm_get_shadow_pages(kvm_context_t kvm
, unsigned int *nrshadow_pages
)
501 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
504 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
,
505 KVM_CAP_MMU_SHADOW_CACHE_CONTROL
);
507 *nrshadow_pages
= kvm_vm_ioctl(kvm_state
, KVM_GET_NR_MMU_PAGES
);
515 static int kvm_enable_tpr_access_reporting(CPUState
*env
)
518 struct kvm_tpr_access_ctl tac
= { .enabled
= 1 };
520 r
= kvm_ioctl(env
->kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_VAPIC
);
524 return kvm_vcpu_ioctl(env
, KVM_TPR_ACCESS_REPORTING
, &tac
);
528 #ifdef KVM_CAP_ADJUST_CLOCK
529 static struct kvm_clock_data kvmclock_data
;
531 static void kvmclock_pre_save(void *opaque
)
533 struct kvm_clock_data
*cl
= opaque
;
535 kvm_vm_ioctl(kvm_state
, KVM_GET_CLOCK
, cl
);
538 static int kvmclock_post_load(void *opaque
, int version_id
)
540 struct kvm_clock_data
*cl
= opaque
;
542 return kvm_vm_ioctl(kvm_state
, KVM_SET_CLOCK
, cl
);
545 static const VMStateDescription vmstate_kvmclock
= {
548 .minimum_version_id
= 1,
549 .minimum_version_id_old
= 1,
550 .pre_save
= kvmclock_pre_save
,
551 .post_load
= kvmclock_post_load
,
552 .fields
= (VMStateField
[]) {
553 VMSTATE_U64(clock
, struct kvm_clock_data
),
554 VMSTATE_END_OF_LIST()
559 int kvm_arch_qemu_create_context(void)
562 struct utsname utsname
;
565 _lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
567 if (kvm_shadow_memory
) {
568 kvm_set_shadow_pages(kvm_context
, kvm_shadow_memory
);
571 kvm_msr_list
= kvm_get_msr_list();
575 for (i
= 0; i
< kvm_msr_list
->nmsrs
; ++i
) {
576 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
577 kvm_has_msr_star
= 1;
579 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
580 kvm_has_vm_hsave_pa
= 1;
584 #ifdef KVM_CAP_ADJUST_CLOCK
585 if (kvm_check_extension(kvm_state
, KVM_CAP_ADJUST_CLOCK
)) {
586 vmstate_register(NULL
, 0, &vmstate_kvmclock
, &kvmclock_data
);
590 r
= kvm_set_boot_cpu_id(0);
591 if (r
< 0 && r
!= -ENOSYS
) {
598 /* returns 0 on success, non-0 on failure */
599 static int get_msr_entry(struct kvm_msr_entry
*entry
, CPUState
*env
)
601 switch (entry
->index
) {
602 case MSR_IA32_SYSENTER_CS
:
603 env
->sysenter_cs
= entry
->data
;
605 case MSR_IA32_SYSENTER_ESP
:
606 env
->sysenter_esp
= entry
->data
;
608 case MSR_IA32_SYSENTER_EIP
:
609 env
->sysenter_eip
= entry
->data
;
612 env
->star
= entry
->data
;
616 env
->cstar
= entry
->data
;
618 case MSR_KERNELGSBASE
:
619 env
->kernelgsbase
= entry
->data
;
622 env
->fmask
= entry
->data
;
625 env
->lstar
= entry
->data
;
629 env
->tsc
= entry
->data
;
631 case MSR_VM_HSAVE_PA
:
632 env
->vm_hsave
= entry
->data
;
634 case MSR_KVM_SYSTEM_TIME
:
635 env
->system_time_msr
= entry
->data
;
637 case MSR_KVM_WALL_CLOCK
:
638 env
->wall_clock_msr
= entry
->data
;
642 env
->mcg_status
= entry
->data
;
645 env
->mcg_ctl
= entry
->data
;
650 if (entry
->index
>= MSR_MC0_CTL
&&
651 entry
->index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
652 env
->mce_banks
[entry
->index
- MSR_MC0_CTL
] = entry
->data
;
656 printf("Warning unknown msr index 0x%x\n", entry
->index
);
662 static void kvm_arch_save_mpstate(CPUState
*env
)
664 #ifdef KVM_CAP_MP_STATE
666 struct kvm_mp_state mp_state
;
668 r
= kvm_get_mpstate(env
, &mp_state
);
672 env
->mp_state
= mp_state
.mp_state
;
673 if (kvm_irqchip_in_kernel()) {
674 env
->halted
= (env
->mp_state
== KVM_MP_STATE_HALTED
);
682 static void kvm_arch_load_mpstate(CPUState
*env
)
684 #ifdef KVM_CAP_MP_STATE
685 struct kvm_mp_state mp_state
;
688 * -1 indicates that the host did not support GET_MP_STATE ioctl,
691 if (env
->mp_state
!= -1) {
692 mp_state
.mp_state
= env
->mp_state
;
693 kvm_set_mpstate(env
, &mp_state
);
698 static void kvm_reset_mpstate(CPUState
*env
)
700 #ifdef KVM_CAP_MP_STATE
701 if (kvm_check_extension(kvm_state
, KVM_CAP_MP_STATE
)) {
702 if (kvm_irqchip_in_kernel()) {
703 env
->mp_state
= cpu_is_bsp(env
) ? KVM_MP_STATE_RUNNABLE
:
704 KVM_MP_STATE_UNINITIALIZED
;
706 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
712 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
714 lhs
->selector
= rhs
->selector
;
715 lhs
->base
= rhs
->base
;
716 lhs
->limit
= rhs
->limit
;
728 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
730 unsigned flags
= rhs
->flags
;
731 lhs
->selector
= rhs
->selector
;
732 lhs
->base
= rhs
->base
;
733 lhs
->limit
= rhs
->limit
;
734 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
735 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
736 lhs
->dpl
= rhs
->selector
& 3;
737 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
738 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
739 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
740 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
741 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
745 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
747 lhs
->selector
= rhs
->selector
;
748 lhs
->base
= rhs
->base
;
749 lhs
->limit
= rhs
->limit
;
751 (rhs
->type
<< DESC_TYPE_SHIFT
)
752 | (rhs
->present
* DESC_P_MASK
)
753 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
754 | (rhs
->db
<< DESC_B_SHIFT
)
755 | (rhs
->s
* DESC_S_MASK
)
756 | (rhs
->l
<< DESC_L_SHIFT
)
757 | (rhs
->g
* DESC_G_MASK
)
758 | (rhs
->avl
* DESC_AVL_MASK
);
761 #define XSAVE_CWD_RIP 2
762 #define XSAVE_CWD_RDP 4
763 #define XSAVE_MXCSR 6
764 #define XSAVE_ST_SPACE 8
765 #define XSAVE_XMM_SPACE 40
766 #define XSAVE_XSTATE_BV 128
767 #define XSAVE_YMMH_SPACE 144
769 void kvm_arch_load_regs(CPUState
*env
, int level
)
771 struct kvm_regs regs
;
773 struct kvm_sregs sregs
;
774 struct kvm_msr_entry msrs
[100];
777 assert(kvm_cpu_is_stopped(env
) || env
->thread_id
== kvm_get_thread_id());
779 regs
.rax
= env
->regs
[R_EAX
];
780 regs
.rbx
= env
->regs
[R_EBX
];
781 regs
.rcx
= env
->regs
[R_ECX
];
782 regs
.rdx
= env
->regs
[R_EDX
];
783 regs
.rsi
= env
->regs
[R_ESI
];
784 regs
.rdi
= env
->regs
[R_EDI
];
785 regs
.rsp
= env
->regs
[R_ESP
];
786 regs
.rbp
= env
->regs
[R_EBP
];
788 regs
.r8
= env
->regs
[8];
789 regs
.r9
= env
->regs
[9];
790 regs
.r10
= env
->regs
[10];
791 regs
.r11
= env
->regs
[11];
792 regs
.r12
= env
->regs
[12];
793 regs
.r13
= env
->regs
[13];
794 regs
.r14
= env
->regs
[14];
795 regs
.r15
= env
->regs
[15];
798 regs
.rflags
= env
->eflags
;
801 kvm_set_regs(env
, ®s
);
804 if (kvm_check_extension(kvm_state
, KVM_CAP_XSAVE
)) {
805 struct kvm_xsave
* xsave
;
807 uint16_t cwd
, swd
, twd
, fop
;
809 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
810 memset(xsave
, 0, sizeof(struct kvm_xsave
));
811 cwd
= swd
= twd
= fop
= 0;
812 swd
= env
->fpus
& ~(7 << 11);
813 swd
|= (env
->fpstt
& 7) << 11;
815 for (i
= 0; i
< 8; ++i
) {
816 twd
|= (!env
->fptags
[i
]) << i
;
818 xsave
->region
[0] = (uint32_t)(swd
<< 16) + cwd
;
819 xsave
->region
[1] = (uint32_t)(fop
<< 16) + twd
;
820 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
822 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
823 sizeof env
->xmm_regs
);
824 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
825 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
826 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
827 sizeof env
->ymmh_regs
);
828 kvm_set_xsave(env
, xsave
);
829 if (kvm_check_extension(kvm_state
, KVM_CAP_XCRS
)) {
830 struct kvm_xcrs xcrs
;
834 xcrs
.xcrs
[0].xcr
= 0;
835 xcrs
.xcrs
[0].value
= env
->xcr0
;
836 kvm_set_xcrs(env
, &xcrs
);
841 memset(&fpu
, 0, sizeof fpu
);
842 fpu
.fsw
= env
->fpus
& ~(7 << 11);
843 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
845 for (i
= 0; i
< 8; ++i
) {
846 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
848 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
849 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
850 fpu
.mxcsr
= env
->mxcsr
;
851 kvm_set_fpu(env
, &fpu
);
856 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
857 if (env
->interrupt_injected
>= 0) {
858 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
859 (uint64_t)1 << (env
->interrupt_injected
% 64);
862 if ((env
->eflags
& VM_MASK
)) {
863 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
864 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
865 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
866 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
867 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
868 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
870 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
871 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
872 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
873 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
874 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
875 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
877 if (env
->cr
[0] & CR0_PE_MASK
) {
878 /* force ss cpl to cs cpl */
879 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
880 (sregs
.cs
.selector
& 3);
881 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
885 set_seg(&sregs
.tr
, &env
->tr
);
886 set_seg(&sregs
.ldt
, &env
->ldt
);
888 sregs
.idt
.limit
= env
->idt
.limit
;
889 sregs
.idt
.base
= env
->idt
.base
;
890 sregs
.gdt
.limit
= env
->gdt
.limit
;
891 sregs
.gdt
.base
= env
->gdt
.base
;
893 sregs
.cr0
= env
->cr
[0];
894 sregs
.cr2
= env
->cr
[2];
895 sregs
.cr3
= env
->cr
[3];
896 sregs
.cr4
= env
->cr
[4];
898 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
899 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
901 sregs
.efer
= env
->efer
;
903 kvm_set_sregs(env
, &sregs
);
907 /* Remember to increase msrs size if you add new registers below */
908 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
909 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
910 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
911 if (kvm_has_msr_star
) {
912 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
914 if (kvm_has_vm_hsave_pa
) {
915 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
918 if (_lm_capable_kernel
) {
919 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
920 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
921 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
922 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
925 if (level
== KVM_PUT_FULL_STATE
) {
927 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
928 * writeback. Until this is fixed, we only write the offset to SMP
929 * guests after migration, desynchronizing the VCPUs, but avoiding
930 * huge jump-backs that would occur without any writeback at all.
932 if (smp_cpus
== 1 || env
->tsc
!= 0) {
933 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
935 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
936 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
940 if (level
== KVM_PUT_RESET_STATE
) {
941 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
942 } else if (level
== KVM_PUT_FULL_STATE
) {
943 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
944 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
945 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
946 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
952 rc
= kvm_set_msrs(env
, msrs
, n
);
954 perror("kvm_set_msrs FAILED");
957 if (level
>= KVM_PUT_RESET_STATE
) {
958 kvm_arch_load_mpstate(env
);
961 if (level
== KVM_PUT_FULL_STATE
) {
962 if (env
->kvm_vcpu_update_vapic
) {
963 kvm_tpr_enable_vapic(env
);
967 kvm_put_vcpu_events(env
, level
);
968 kvm_put_debugregs(env
);
971 kvm_guest_debug_workarounds(env
);
974 void kvm_arch_save_regs(CPUState
*env
)
976 struct kvm_regs regs
;
978 struct kvm_sregs sregs
;
979 struct kvm_msr_entry msrs
[100];
981 uint32_t i
, n
, rc
, bit
;
983 assert(kvm_cpu_is_stopped(env
) || env
->thread_id
== kvm_get_thread_id());
985 kvm_get_regs(env
, ®s
);
987 env
->regs
[R_EAX
] = regs
.rax
;
988 env
->regs
[R_EBX
] = regs
.rbx
;
989 env
->regs
[R_ECX
] = regs
.rcx
;
990 env
->regs
[R_EDX
] = regs
.rdx
;
991 env
->regs
[R_ESI
] = regs
.rsi
;
992 env
->regs
[R_EDI
] = regs
.rdi
;
993 env
->regs
[R_ESP
] = regs
.rsp
;
994 env
->regs
[R_EBP
] = regs
.rbp
;
996 env
->regs
[8] = regs
.r8
;
997 env
->regs
[9] = regs
.r9
;
998 env
->regs
[10] = regs
.r10
;
999 env
->regs
[11] = regs
.r11
;
1000 env
->regs
[12] = regs
.r12
;
1001 env
->regs
[13] = regs
.r13
;
1002 env
->regs
[14] = regs
.r14
;
1003 env
->regs
[15] = regs
.r15
;
1006 env
->eflags
= regs
.rflags
;
1007 env
->eip
= regs
.rip
;
1009 #ifdef KVM_CAP_XSAVE
1010 if (kvm_check_extension(kvm_state
, KVM_CAP_XSAVE
)) {
1011 struct kvm_xsave
* xsave
;
1012 uint16_t cwd
, swd
, twd
, fop
;
1013 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
1014 kvm_get_xsave(env
, xsave
);
1015 cwd
= (uint16_t)xsave
->region
[0];
1016 swd
= (uint16_t)(xsave
->region
[0] >> 16);
1017 twd
= (uint16_t)xsave
->region
[1];
1018 fop
= (uint16_t)(xsave
->region
[1] >> 16);
1019 env
->fpstt
= (swd
>> 11) & 7;
1022 for (i
= 0; i
< 8; ++i
) {
1023 env
->fptags
[i
] = !((twd
>> i
) & 1);
1025 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
1026 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
1027 sizeof env
->fpregs
);
1028 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
1029 sizeof env
->xmm_regs
);
1030 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
1031 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
1032 sizeof env
->ymmh_regs
);
1033 if (kvm_check_extension(kvm_state
, KVM_CAP_XCRS
)) {
1034 struct kvm_xcrs xcrs
;
1036 kvm_get_xcrs(env
, &xcrs
);
1037 if (xcrs
.xcrs
[0].xcr
== 0) {
1038 env
->xcr0
= xcrs
.xcrs
[0].value
;
1044 kvm_get_fpu(env
, &fpu
);
1045 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1046 env
->fpus
= fpu
.fsw
;
1047 env
->fpuc
= fpu
.fcw
;
1048 for (i
= 0; i
< 8; ++i
) {
1049 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1051 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1052 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
1053 env
->mxcsr
= fpu
.mxcsr
;
1054 #ifdef KVM_CAP_XSAVE
1058 kvm_get_sregs(env
, &sregs
);
1060 /* There can only be one pending IRQ set in the bitmap at a time, so try
1061 to find it and save its number instead (-1 for none). */
1062 env
->interrupt_injected
= -1;
1063 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1064 if (sregs
.interrupt_bitmap
[i
]) {
1065 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1066 env
->interrupt_injected
= i
* 64 + bit
;
1071 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1072 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1073 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1074 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1075 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1076 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1078 get_seg(&env
->tr
, &sregs
.tr
);
1079 get_seg(&env
->ldt
, &sregs
.ldt
);
1081 env
->idt
.limit
= sregs
.idt
.limit
;
1082 env
->idt
.base
= sregs
.idt
.base
;
1083 env
->gdt
.limit
= sregs
.gdt
.limit
;
1084 env
->gdt
.base
= sregs
.gdt
.base
;
1086 env
->cr
[0] = sregs
.cr0
;
1087 env
->cr
[2] = sregs
.cr2
;
1088 env
->cr
[3] = sregs
.cr3
;
1089 env
->cr
[4] = sregs
.cr4
;
1091 cpu_set_apic_base(env
->apic_state
, sregs
.apic_base
);
1093 env
->efer
= sregs
.efer
;
1094 //cpu_set_apic_tpr(env, sregs.cr8);
1096 #define HFLAG_COPY_MASK ~( \
1097 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1098 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1099 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1100 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1102 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1103 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1104 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1105 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1106 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1107 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1108 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1110 if (env
->efer
& MSR_EFER_LMA
) {
1111 hflags
|= HF_LMA_MASK
;
1114 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1115 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1117 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1118 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1119 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1120 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1121 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
1122 (env
->eflags
& VM_MASK
) ||
1123 !(hflags
& HF_CS32_MASK
)) {
1124 hflags
|= HF_ADDSEG_MASK
;
1126 hflags
|= ((env
->segs
[R_DS
].base
|
1127 env
->segs
[R_ES
].base
|
1128 env
->segs
[R_SS
].base
) != 0) <<
1132 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1136 /* Remember to increase msrs size if you add new registers below */
1137 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1138 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1139 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1140 if (kvm_has_msr_star
) {
1141 msrs
[n
++].index
= MSR_STAR
;
1143 msrs
[n
++].index
= MSR_IA32_TSC
;
1144 if (kvm_has_vm_hsave_pa
)
1145 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1146 #ifdef TARGET_X86_64
1147 if (_lm_capable_kernel
) {
1148 msrs
[n
++].index
= MSR_CSTAR
;
1149 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1150 msrs
[n
++].index
= MSR_FMASK
;
1151 msrs
[n
++].index
= MSR_LSTAR
;
1154 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1155 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1159 msrs
[n
++].index
= MSR_MCG_STATUS
;
1160 msrs
[n
++].index
= MSR_MCG_CTL
;
1161 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++)
1162 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1166 rc
= kvm_get_msrs(env
, msrs
, n
);
1168 perror("kvm_get_msrs FAILED");
1170 n
= rc
; /* actual number of MSRs */
1171 for (i
=0 ; i
<n
; i
++) {
1172 if (get_msr_entry(&msrs
[i
], env
)) {
1177 kvm_arch_save_mpstate(env
);
1178 kvm_save_lapic(env
);
1179 kvm_get_vcpu_events(env
);
1180 kvm_get_debugregs(env
);
1183 static int _kvm_arch_init_vcpu(CPUState
*env
)
1185 kvm_arch_reset_vcpu(env
);
1187 #ifdef KVM_EXIT_TPR_ACCESS
1188 kvm_enable_tpr_access_reporting(env
);
1190 kvm_reset_mpstate(env
);
1194 int kvm_arch_halt(CPUState
*env
)
1197 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1198 (env
->eflags
& IF_MASK
)) &&
1199 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1205 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1207 if (!kvm_irqchip_in_kernel()) {
1208 kvm_set_cr8(env
, cpu_get_apic_tpr(env
->apic_state
));
1213 int kvm_arch_has_work(CPUState
*env
)
1215 if (((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1216 (env
->eflags
& IF_MASK
)) ||
1217 (env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1223 int kvm_arch_try_push_interrupts(void *opaque
)
1225 CPUState
*env
= cpu_single_env
;
1228 if (kvm_is_ready_for_interrupt_injection(env
) &&
1229 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1230 (env
->eflags
& IF_MASK
)) {
1231 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1232 irq
= cpu_get_pic_interrupt(env
);
1234 r
= kvm_inject_irq(env
, irq
);
1236 printf("cpu %d fail inject %x\n", env
->cpu_index
, irq
);
1241 return (env
->interrupt_request
& CPU_INTERRUPT_HARD
) != 0;
1244 #ifdef KVM_CAP_USER_NMI
1245 void kvm_arch_push_nmi(void *opaque
)
1247 CPUState
*env
= cpu_single_env
;
1250 if (likely(!(env
->interrupt_request
& CPU_INTERRUPT_NMI
))) {
1254 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1255 r
= kvm_inject_nmi(env
);
1257 printf("cpu %d fail inject NMI\n", env
->cpu_index
);
1260 #endif /* KVM_CAP_USER_NMI */
1262 static int kvm_reset_msrs(CPUState
*env
)
1265 struct kvm_msrs info
;
1266 struct kvm_msr_entry entries
[100];
1269 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1273 if (!kvm_msr_list
) {
1277 for (n
= 0; n
< kvm_msr_list
->nmsrs
; n
++) {
1278 index
= kvm_msr_list
->indices
[n
];
1281 data
= 0x0007040600070406ULL
;
1286 kvm_msr_entry_set(&msrs
[n
], kvm_msr_list
->indices
[n
], data
);
1289 msr_data
.info
.nmsrs
= n
;
1291 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
1295 void kvm_arch_cpu_reset(CPUState
*env
)
1297 kvm_reset_msrs(env
);
1298 kvm_arch_reset_vcpu(env
);
1299 kvm_reset_mpstate(env
);
1302 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1303 void kvm_arch_do_ioperm(void *_data
)
1305 struct ioperm_data
*data
= _data
;
1306 ioperm(data
->start_port
, data
->num
, data
->turn_on
);
1311 * Setup x86 specific IRQ routing
1313 int kvm_arch_init_irq_routing(void)
1317 if (kvm_irqchip
&& kvm_has_gsi_routing()) {
1318 kvm_clear_gsi_routes();
1319 for (i
= 0; i
< 8; ++i
) {
1323 r
= kvm_add_irq_route(i
, KVM_IRQCHIP_PIC_MASTER
, i
);
1328 for (i
= 8; i
< 16; ++i
) {
1329 r
= kvm_add_irq_route(i
, KVM_IRQCHIP_PIC_SLAVE
, i
- 8);
1334 for (i
= 0; i
< 24; ++i
) {
1335 if (i
== 0 && irq0override
) {
1336 r
= kvm_add_irq_route(i
, KVM_IRQCHIP_IOAPIC
, 2);
1337 } else if (i
!= 2 || !irq0override
) {
1338 r
= kvm_add_irq_route(i
, KVM_IRQCHIP_IOAPIC
, i
);
1344 kvm_commit_irq_routes();
1349 void kvm_arch_process_irqchip_events(CPUState
*env
)
1351 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1352 kvm_cpu_synchronize_state(env
);
1355 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1356 kvm_cpu_synchronize_state(env
);