hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8 #include "kvm.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78
  79 #define FMT_PCIBUS                      PRIx64
  80
  81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  82                                 uint32_t address, uint32_t data, int len);
  83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  84                                    uint32_t address, int len);
  85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  86                                 pcibus_t addr, pcibus_t size, int type);
  87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  88
  89 typedef struct PCIIORegion {
  90     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  92     pcibus_t size;
  93     pcibus_t filtered_size;
  94     uint8_t type;
  95     PCIMapIORegionFunc *map_func;
  96     ram_addr_t ram_addr;
  97 } PCIIORegion;
  98
  99 #define PCI_ROM_SLOT 6
 100 #define PCI_NUM_REGIONS 7
 101
 102 #include "pci_regs.h"
 103
 104 /* PCI HEADER_TYPE */
 105 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 106
 107 /* Size of the standard PCI config header */
 108 #define PCI_CONFIG_HEADER_SIZE 0x40
 109 /* Size of the standard PCI config space */
 110 #define PCI_CONFIG_SPACE_SIZE 0x100
 111 /* Size of the standart PCIe config space: 4KB */
 112 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 113
 114 #define PCI_NUM_PINS 4 /* A-D */
 115
 116 /* Bits in cap_present field. */
 117 enum {
 118     QEMU_PCI_CAP_MSI = 0x1,
 119     QEMU_PCI_CAP_MSIX = 0x2,
 120     QEMU_PCI_CAP_EXPRESS = 0x4,
 121
 122     /* multifunction capable device */
 123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 124     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 125
 126     /* command register SERR bit enabled */
 127 #define QEMU_PCI_CAP_SERR_BITNR 4
 128     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 129 };
 130
 131 typedef int (*msix_mask_notifier_func)(PCIDevice *, unsigned vector,
 132                                        int masked);
 133
 134 struct PCIDevice {
 135     DeviceState qdev;
 136     /* PCI config space */
 137     uint8_t *config;
 138
 139     /* Used to enable config checks on load. Note that writable bits are
 140      * never checked even if set in cmask. */
 141     uint8_t *cmask;
 142
 143     /* Used to implement R/W bytes */
 144     uint8_t *wmask;
 145
 146     /* Used to implement RW1C(Write 1 to Clear) bytes */
 147     uint8_t *w1cmask;
 148
 149     /* Used to allocate config space and track capabilities. */
 150     uint8_t *config_map;
 151
 152     /* the following fields are read only */
 153     PCIBus *bus;
 154     uint32_t devfn;
 155     char name[64];
 156     PCIIORegion io_regions[PCI_NUM_REGIONS];
 157
 158     /* do not access the following fields */
 159     PCIConfigReadFunc *config_read;
 160     PCIConfigWriteFunc *config_write;
 161
 162     /* IRQ objects for the INTA-INTD pins.  */
 163     qemu_irq *irq;
 164
 165     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 166     uint8_t irq_state;
 167
 168     /* Capability bits */
 169     uint32_t cap_present;
 170
 171     /* Offset of MSI-X capability in config space */
 172     uint8_t msix_cap;
 173
 174     /* MSI-X entries */
 175     int msix_entries_nr;
 176
 177     /* Space to store MSIX table */
 178     uint8_t *msix_table_page;
 179     /* MMIO index used to map MSIX table and pending bit entries. */
 180     int msix_mmio_index;
 181     /* Reference-count for entries actually in use by driver. */
 182     unsigned *msix_entry_used;
 183     /* Region including the MSI-X table */
 184     uint32_t msix_bar_size;
 185     /* Version id needed for VMState */
 186     int32_t version_id;
 187
 188     /* Offset of MSI capability in config space */
 189     uint8_t msi_cap;
 190
 191     /* PCI Express */
 192     PCIExpressDevice exp;
 193
 194     /* Location of option rom */
 195     char *romfile;
 196     ram_addr_t rom_offset;
 197     uint32_t rom_bar;
 198
 199     /* MSI entries */
 200     int msi_entries_nr;
 201     struct KVMMsiMessage *msi_irq_entries;
 202
 203     /* How much space does an MSIX table need. */
 204     /* The spec requires giving the table structure
 205      * a 4K aligned region all by itself. Align it to
 206      * target pages so that drivers can do passthrough
 207      * on the rest of the region. */
 208     target_phys_addr_t msix_page_size;
 209
 210     KVMMsiMessage *msix_irq_entries;
 211
 212     msix_mask_notifier_func msix_mask_notifier;
 213 };
 214
 215 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 216                                int instance_size, int devfn,
 217                                PCIConfigReadFunc *config_read,
 218                                PCIConfigWriteFunc *config_write);
 219
 220 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 221                             pcibus_t size, uint8_t type,
 222                             PCIMapIORegionFunc *map_func);
 223 void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
 224                              pcibus_t size, uint8_t attr, ram_addr_t ram_addr);
 225
 226 void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr,
 227                         pcibus_t size, int type);
 228
 229 int pci_map_irq(PCIDevice *pci_dev, int pin);
 230
 231 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 232                        uint8_t offset, uint8_t size);
 233
 234 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 235
 236 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 237
 238 uint32_t pci_default_read_config(PCIDevice *d,
 239                                  uint32_t address, int len);
 240 void pci_default_write_config(PCIDevice *d,
 241                               uint32_t address, uint32_t val, int len);
 242 void pci_device_save(PCIDevice *s, QEMUFile *f);
 243 int pci_device_load(PCIDevice *s, QEMUFile *f);
 244 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 245 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 246
 247 typedef enum {
 248     PCI_HOTPLUG_DISABLED,
 249     PCI_HOTPLUG_ENABLED,
 250     PCI_COLDPLUG_ENABLED,
 251 } PCIHotplugState;
 252
 253 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 254                               PCIHotplugState state);
 255 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 256                          const char *name, uint8_t devfn_min);
 257 PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min);
 258 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 259                   void *irq_opaque, int nirq);
 260 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 261 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 262 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 263                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 264                          void *irq_opaque, uint8_t devfn_min, int nirq);
 265 void pci_device_reset(PCIDevice *dev);
 266 void pci_bus_reset(PCIBus *bus);
 267
 268 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 269
 270 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 271                         const char *default_devaddr);
 272 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 273                                const char *default_devaddr);
 274 int pci_bus_num(PCIBus *s);
 275 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 276 PCIBus *pci_find_root_bus(int domain);
 277 int pci_find_domain(const PCIBus *bus);
 278 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 279 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 280 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 281 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 282
 283 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 284                       unsigned int *slotp, unsigned int *funcp);
 285 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 286                      unsigned *slotp);
 287
 288 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
 289                            int *slotp, int *funcp);
 290
 291 void do_pci_info_print(Monitor *mon, const QObject *data);
 292 void do_pci_info(Monitor *mon, QObject **ret_data);
 293 void pci_bridge_update_mappings(PCIBus *b);
 294
 295 void pci_device_deassert_intx(PCIDevice *dev);
 296
 297 static inline void
 298 pci_set_byte(uint8_t *config, uint8_t val)
 299 {
 300     *config = val;
 301 }
 302
 303 static inline uint8_t
 304 pci_get_byte(const uint8_t *config)
 305 {
 306     return *config;
 307 }
 308
 309 static inline void
 310 pci_set_word(uint8_t *config, uint16_t val)
 311 {
 312     cpu_to_le16wu((uint16_t *)config, val);
 313 }
 314
 315 static inline uint16_t
 316 pci_get_word(const uint8_t *config)
 317 {
 318     return le16_to_cpupu((const uint16_t *)config);
 319 }
 320
 321 static inline void
 322 pci_set_long(uint8_t *config, uint32_t val)
 323 {
 324     cpu_to_le32wu((uint32_t *)config, val);
 325 }
 326
 327 static inline uint32_t
 328 pci_get_long(const uint8_t *config)
 329 {
 330     return le32_to_cpupu((const uint32_t *)config);
 331 }
 332
 333 static inline void
 334 pci_set_quad(uint8_t *config, uint64_t val)
 335 {
 336     cpu_to_le64w((uint64_t *)config, val);
 337 }
 338
 339 static inline uint64_t
 340 pci_get_quad(const uint8_t *config)
 341 {
 342     return le64_to_cpup((const uint64_t *)config);
 343 }
 344
 345 static inline void
 346 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 347 {
 348     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 349 }
 350
 351 static inline void
 352 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 353 {
 354     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 355 }
 356
 357 static inline void
 358 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 359 {
 360     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 361 }
 362
 363 static inline void
 364 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 365 {
 366     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 367 }
 368
 369 static inline void
 370 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 371 {
 372     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 373 }
 374
 375 static inline void
 376 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 377 {
 378     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 379 }
 380
 381 /*
 382  * helper functions to do bit mask operation on configuration space.
 383  * Just to set bit, use test-and-set and discard returned value.
 384  * Just to clear bit, use test-and-clear and discard returned value.
 385  * NOTE: They aren't atomic.
 386  */
 387 static inline uint8_t
 388 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 389 {
 390     uint8_t val = pci_get_byte(config);
 391     pci_set_byte(config, val & ~mask);
 392     return val & mask;
 393 }
 394
 395 static inline uint8_t
 396 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 397 {
 398     uint8_t val = pci_get_byte(config);
 399     pci_set_byte(config, val | mask);
 400     return val & mask;
 401 }
 402
 403 static inline uint16_t
 404 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 405 {
 406     uint16_t val = pci_get_word(config);
 407     pci_set_word(config, val & ~mask);
 408     return val & mask;
 409 }
 410
 411 static inline uint16_t
 412 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 413 {
 414     uint16_t val = pci_get_word(config);
 415     pci_set_word(config, val | mask);
 416     return val & mask;
 417 }
 418
 419 static inline uint32_t
 420 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 421 {
 422     uint32_t val = pci_get_long(config);
 423     pci_set_long(config, val & ~mask);
 424     return val & mask;
 425 }
 426
 427 static inline uint32_t
 428 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 429 {
 430     uint32_t val = pci_get_long(config);
 431     pci_set_long(config, val | mask);
 432     return val & mask;
 433 }
 434
 435 static inline uint64_t
 436 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 437 {
 438     uint64_t val = pci_get_quad(config);
 439     pci_set_quad(config, val & ~mask);
 440     return val & mask;
 441 }
 442
 443 static inline uint64_t
 444 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 445 {
 446     uint64_t val = pci_get_quad(config);
 447     pci_set_quad(config, val | mask);
 448     return val & mask;
 449 }
 450
 451 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 452 typedef struct {
 453     DeviceInfo qdev;
 454     pci_qdev_initfn init;
 455     PCIUnregisterFunc *exit;
 456     PCIConfigReadFunc *config_read;
 457     PCIConfigWriteFunc *config_write;
 458
 459     /*
 460      * pci-to-pci bridge or normal device.
 461      * This doesn't mean pci host switch.
 462      * When card bus bridge is supported, this would be enhanced.
 463      */
 464     int is_bridge;
 465
 466     /* pcie stuff */
 467     int is_express;   /* is this device pci express? */
 468
 469     /* device isn't hot-pluggable */
 470     int no_hotplug;
 471
 472     /* rom bar */
 473     const char *romfile;
 474 } PCIDeviceInfo;
 475
 476 void pci_qdev_register(PCIDeviceInfo *info);
 477 void pci_qdev_register_many(PCIDeviceInfo *info);
 478
 479 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 480                                     const char *name);
 481 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 482                                            bool multifunction,
 483                                            const char *name);
 484 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
 485                                         bool multifunction,
 486                                         const char *name);
 487 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 488 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 489 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
 490
 491 static inline int pci_is_express(const PCIDevice *d)
 492 {
 493     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 494 }
 495
 496 static inline uint32_t pci_config_size(const PCIDevice *d)
 497 {
 498     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 499 }
 500
 501 #endif