hw/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  */
  13
  14 #include "hw.h"
  15 #include "msix.h"
  16 #include "pci.h"
  17 #include "kvm.h"
  18
  19 /* MSI-X capability structure */
  20 #define MSIX_TABLE_OFFSET 4
  21 #define MSIX_PBA_OFFSET 8
  22 #define MSIX_CAP_LENGTH 12
  23
  24 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
  25 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
  26 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  27 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
  28
  29 /* MSI-X table format */
  30 #define MSIX_MSG_ADDR 0
  31 #define MSIX_MSG_UPPER_ADDR 4
  32 #define MSIX_MSG_DATA 8
  33 #define MSIX_VECTOR_CTRL 12
  34 #define MSIX_ENTRY_SIZE 16
  35 #define MSIX_VECTOR_MASK 0x1
  36
  37 /* How much space does an MSIX table need. */
  38 /* The spec requires giving the table structure
  39  * a 4K aligned region all by itself. */
  40 #define MSIX_PAGE_SIZE 0x1000
  41 /* Reserve second half of the page for pending bits */
  42 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
  43 #define MSIX_MAX_ENTRIES 32
  44
  45
  46 /* Flag for interrupt controller to declare MSI-X support */
  47 int msix_supported;
  48
  49 #ifdef CONFIG_KVM
  50 /* KVM specific MSIX helpers */
  51 static void kvm_msix_free(PCIDevice *dev)
  52 {
  53     int vector, changed = 0;
  54     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
  55         if (dev->msix_entry_used[vector]) {
  56             kvm_del_routing_entry(kvm_context, &dev->msix_irq_entries[vector]);
  57             changed = 1;
  58         }
  59     }
  60     if (changed) {
  61         kvm_commit_irq_routes(kvm_context);
  62     }
  63 }
  64
  65 static void kvm_msix_routing_entry(PCIDevice *dev, unsigned vector,
  66                                    struct kvm_irq_routing_entry *entry)
  67 {
  68     uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
  69     entry->type = KVM_IRQ_ROUTING_MSI;
  70     entry->flags = 0;
  71     entry->u.msi.address_lo = pci_get_long(table_entry + MSIX_MSG_ADDR);
  72     entry->u.msi.address_hi = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
  73     entry->u.msi.data = pci_get_long(table_entry + MSIX_MSG_DATA);
  74 }
  75
  76 static void kvm_msix_update(PCIDevice *dev, int vector,
  77                             int was_masked, int is_masked)
  78 {
  79     struct kvm_irq_routing_entry e = {}, *entry;
  80     int mask_cleared = was_masked && !is_masked;
  81     /* It is only legal to change an entry when it is masked. Therefore, it is
  82      * enough to update the routing in kernel when mask is being cleared. */
  83     if (!mask_cleared) {
  84         return;
  85     }
  86     if (!dev->msix_entry_used[vector]) {
  87         return;
  88     }
  89     entry = dev->msix_irq_entries + vector;
  90     e.gsi = entry->gsi;
  91     kvm_msix_routing_entry(dev, vector, &e);
  92     if (memcmp(&entry->u.msi, &e.u.msi, sizeof entry->u.msi)) {
  93         int r;
  94         r = kvm_update_routing_entry(kvm_context, entry, &e);
  95         if (r) {
  96             fprintf(stderr, "%s: kvm_update_routing_entry failed: %s\n", __func__,
  97                     strerror(-r));
  98             exit(1);
  99         }
 100         memcpy(&entry->u.msi, &e.u.msi, sizeof entry->u.msi);
 101         r = kvm_commit_irq_routes(kvm_context);
 102         if (r) {
 103             fprintf(stderr, "%s: kvm_commit_irq_routes failed: %s\n", __func__,
 104                     strerror(-r));
 105             exit(1);
 106         }
 107     }
 108 }
 109
 110 static int kvm_msix_add(PCIDevice *dev, unsigned vector)
 111 {
 112     struct kvm_irq_routing_entry *entry = dev->msix_irq_entries + vector;
 113     int r;
 114
 115     if (!kvm_has_gsi_routing(kvm_context)) {
 116         fprintf(stderr, "Warning: no MSI-X support found. "
 117                 "At least kernel 2.6.30 is required for MSI-X support.\n"
 118                );
 119         return -EOPNOTSUPP;
 120     }
 121
 122     r = kvm_get_irq_route_gsi(kvm_context);
 123     if (r < 0) {
 124         fprintf(stderr, "%s: kvm_get_irq_route_gsi failed: %s\n", __func__, strerror(-r));
 125         return r;
 126     }
 127     entry->gsi = r;
 128     kvm_msix_routing_entry(dev, vector, entry);
 129     r = kvm_add_routing_entry(kvm_context, entry);
 130     if (r < 0) {
 131         fprintf(stderr, "%s: kvm_add_routing_entry failed: %s\n", __func__, strerror(-r));
 132         return r;
 133     }
 134
 135     r = kvm_commit_irq_routes(kvm_context);
 136     if (r < 0) {
 137         fprintf(stderr, "%s: kvm_commit_irq_routes failed: %s\n", __func__, strerror(-r));
 138         return r;
 139     }
 140     return 0;
 141 }
 142
 143 static void kvm_msix_del(PCIDevice *dev, unsigned vector)
 144 {
 145     if (dev->msix_entry_used[vector]) {
 146         return;
 147     }
 148     kvm_del_routing_entry(kvm_context, &dev->msix_irq_entries[vector]);
 149     kvm_commit_irq_routes(kvm_context);
 150 }
 151 #else
 152
 153 static void kvm_msix_free(PCIDevice *dev) {}
 154 static void kvm_msix_update(PCIDevice *dev, int vector,
 155                             int was_masked, int is_masked) {}
 156 static int kvm_msix_add(PCIDevice *dev, unsigned vector) { return -1; }
 157 static void kvm_msix_del(PCIDevice *dev, unsigned vector) {}
 158 #endif
 159
 160 /* Add MSI-X capability to the config space for the device. */
 161 /* Given a bar and its size, add MSI-X table on top of it
 162  * and fill MSI-X capability in the config space.
 163  * Original bar size must be a power of 2 or 0.
 164  * New bar size is returned. */
 165 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
 166                            unsigned bar_nr, unsigned bar_size)
 167 {
 168     int config_offset;
 169     uint8_t *config;
 170     uint32_t new_size;
 171
 172     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
 173         return -EINVAL;
 174     if (bar_size > 0x80000000)
 175         return -ENOSPC;
 176
 177     /* Add space for MSI-X structures */
 178     if (!bar_size) {
 179         new_size = MSIX_PAGE_SIZE;
 180     } else if (bar_size < MSIX_PAGE_SIZE) {
 181         bar_size = MSIX_PAGE_SIZE;
 182         new_size = MSIX_PAGE_SIZE * 2;
 183     } else {
 184         new_size = bar_size * 2;
 185     }
 186
 187     pdev->msix_bar_size = new_size;
 188     config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 189     if (config_offset < 0)
 190         return config_offset;
 191     config = pdev->config + config_offset;
 192
 193     pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
 194     /* Table on top of BAR */
 195     pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
 196     /* Pending bits on top of that */
 197     pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
 198                  bar_nr);
 199     pdev->msix_cap = config_offset;
 200     /* Make flags bit writeable. */
 201     pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
 202             MSIX_MASKALL_MASK;
 203     return 0;
 204 }
 205
 206 static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
 207 {
 208     PCIDevice *dev = opaque;
 209     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 210     void *page = dev->msix_table_page;
 211
 212     return pci_get_long(page + offset);
 213 }
 214
 215 static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
 216 {
 217     fprintf(stderr, "MSI-X: only dword read is allowed!\n");
 218     return 0;
 219 }
 220
 221 static uint8_t msix_pending_mask(int vector)
 222 {
 223     return 1 << (vector % 8);
 224 }
 225
 226 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
 227 {
 228     return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
 229 }
 230
 231 static int msix_is_pending(PCIDevice *dev, int vector)
 232 {
 233     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
 234 }
 235
 236 static void msix_set_pending(PCIDevice *dev, int vector)
 237 {
 238     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 239 }
 240
 241 static void msix_clr_pending(PCIDevice *dev, int vector)
 242 {
 243     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 244 }
 245
 246 static int msix_function_masked(PCIDevice *dev)
 247 {
 248     return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
 249 }
 250
 251 static int msix_is_masked(PCIDevice *dev, int vector)
 252 {
 253     unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
 254     return msix_function_masked(dev) ||
 255            dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
 256 }
 257
 258 static void msix_handle_mask_update(PCIDevice *dev, int vector)
 259 {
 260     if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
 261         msix_clr_pending(dev, vector);
 262         msix_notify(dev, vector);
 263     }
 264 }
 265
 266 /* Handle MSI-X capability config write. */
 267 void msix_write_config(PCIDevice *dev, uint32_t addr,
 268                        uint32_t val, int len)
 269 {
 270     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
 271     int vector;
 272
 273     if (!range_covers_byte(addr, len, enable_pos)) {
 274         return;
 275     }
 276
 277     if (!msix_enabled(dev)) {
 278         return;
 279     }
 280
 281     qemu_set_irq(dev->irq[0], 0);
 282
 283     if (msix_function_masked(dev)) {
 284         return;
 285     }
 286
 287     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 288         msix_handle_mask_update(dev, vector);
 289     }
 290 }
 291
 292 static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
 293                              uint32_t val)
 294 {
 295     PCIDevice *dev = opaque;
 296     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 297     int vector = offset / MSIX_ENTRY_SIZE;
 298     int was_masked = msix_is_masked(dev, vector);
 299     pci_set_long(dev->msix_table_page + offset, val);
 300     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 301         kvm_msix_update(dev, vector, was_masked, msix_is_masked(dev, vector));
 302     }
 303     if (was_masked != msix_is_masked(dev, vector) &&
 304         dev->msix_mask_notifier && dev->msix_mask_notifier_opaque[vector]) {
 305         int r = dev->msix_mask_notifier(dev, vector,
 306                                         dev->msix_mask_notifier_opaque[vector],
 307                                         msix_is_masked(dev, vector));
 308         assert(r >= 0);
 309     }
 310     msix_handle_mask_update(dev, vector);
 311 }
 312
 313 static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
 314                                       uint32_t val)
 315 {
 316     fprintf(stderr, "MSI-X: only dword write is allowed!\n");
 317 }
 318
 319 static CPUWriteMemoryFunc * const msix_mmio_write[] = {
 320     msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
 321 };
 322
 323 static CPUReadMemoryFunc * const msix_mmio_read[] = {
 324     msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
 325 };
 326
 327 /* Should be called from device's map method. */
 328 void msix_mmio_map(PCIDevice *d, int region_num,
 329                    pcibus_t addr, pcibus_t size, int type)
 330 {
 331     uint8_t *config = d->config + d->msix_cap;
 332     uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
 333     uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
 334     /* TODO: for assigned devices, we'll want to make it possible to map
 335      * pending bits separately in case they are in a separate bar. */
 336     int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
 337
 338     if (table_bir != region_num)
 339         return;
 340     if (size <= offset)
 341         return;
 342     cpu_register_physical_memory(addr + offset, size - offset,
 343                                  d->msix_mmio_index);
 344 }
 345
 346 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
 347 {
 348     int vector, r;
 349     for (vector = 0; vector < nentries; ++vector) {
 350         unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
 351         int was_masked = msix_is_masked(dev, vector);
 352         dev->msix_table_page[offset] |= MSIX_VECTOR_MASK;
 353         if (was_masked != msix_is_masked(dev, vector) &&
 354             dev->msix_mask_notifier && dev->msix_mask_notifier_opaque[vector]) {
 355             r = dev->msix_mask_notifier(dev, vector,
 356                                         dev->msix_mask_notifier_opaque[vector],
 357                                         msix_is_masked(dev, vector));
 358             assert(r >= 0);
 359         }
 360     }
 361 }
 362
 363 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 364  * modified, it should be retrieved with msix_bar_size. */
 365 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 366               unsigned bar_nr, unsigned bar_size)
 367 {
 368     int ret;
 369     /* Nothing to do if MSI is not supported by interrupt controller */
 370     if (!msix_supported)
 371         return -ENOTSUP;
 372
 373     if (nentries > MSIX_MAX_ENTRIES)
 374         return -EINVAL;
 375
 376 #ifdef KVM_CAP_IRQCHIP
 377     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 378         dev->msix_irq_entries = qemu_malloc(nentries *
 379                                             sizeof *dev->msix_irq_entries);
 380     }
 381 #endif
 382     dev->msix_mask_notifier_opaque =
 383         qemu_mallocz(nentries * sizeof *dev->msix_mask_notifier_opaque);
 384     dev->msix_mask_notifier = NULL;
 385     dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
 386                                         sizeof *dev->msix_entry_used);
 387
 388     dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
 389     msix_mask_all(dev, nentries);
 390
 391     dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
 392                                                   msix_mmio_write, dev);
 393     if (dev->msix_mmio_index == -1) {
 394         ret = -EBUSY;
 395         goto err_index;
 396     }
 397
 398     dev->msix_entries_nr = nentries;
 399     ret = msix_add_config(dev, nentries, bar_nr, bar_size);
 400     if (ret)
 401         goto err_config;
 402
 403     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 404     return 0;
 405
 406 err_config:
 407     dev->msix_entries_nr = 0;
 408     cpu_unregister_io_memory(dev->msix_mmio_index);
 409 err_index:
 410     qemu_free(dev->msix_table_page);
 411     dev->msix_table_page = NULL;
 412     qemu_free(dev->msix_entry_used);
 413     dev->msix_entry_used = NULL;
 414     return ret;
 415 }
 416
 417 static void msix_free_irq_entries(PCIDevice *dev)
 418 {
 419     int vector;
 420
 421     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 422         kvm_msix_free(dev);
 423     }
 424
 425     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 426         dev->msix_entry_used[vector] = 0;
 427         msix_clr_pending(dev, vector);
 428     }
 429 }
 430
 431 /* Clean up resources for the device. */
 432 int msix_uninit(PCIDevice *dev)
 433 {
 434     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 435         return 0;
 436     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 437     dev->msix_cap = 0;
 438     msix_free_irq_entries(dev);
 439     dev->msix_entries_nr = 0;
 440     cpu_unregister_io_memory(dev->msix_mmio_index);
 441     qemu_free(dev->msix_table_page);
 442     dev->msix_table_page = NULL;
 443     qemu_free(dev->msix_entry_used);
 444     dev->msix_entry_used = NULL;
 445     qemu_free(dev->msix_irq_entries);
 446     dev->msix_irq_entries = NULL;
 447     qemu_free(dev->msix_mask_notifier_opaque);
 448     dev->msix_mask_notifier_opaque = NULL;
 449     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 450     return 0;
 451 }
 452
 453 void msix_save(PCIDevice *dev, QEMUFile *f)
 454 {
 455     unsigned n = dev->msix_entries_nr;
 456
 457     if (!msix_supported) {
 458         return;
 459     }
 460
 461     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 462         return;
 463     }
 464     qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
 465     qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 466 }
 467
 468 /* Should be called after restoring the config space. */
 469 void msix_load(PCIDevice *dev, QEMUFile *f)
 470 {
 471     unsigned n = dev->msix_entries_nr;
 472
 473     if (!msix_supported)
 474         return;
 475
 476     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 477         return;
 478     }
 479
 480     msix_free_irq_entries(dev);
 481     qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
 482     qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 483 }
 484
 485 /* Does device support MSI-X? */
 486 int msix_present(PCIDevice *dev)
 487 {
 488     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 489 }
 490
 491 /* Is MSI-X enabled? */
 492 int msix_enabled(PCIDevice *dev)
 493 {
 494     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 495         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 496          MSIX_ENABLE_MASK);
 497 }
 498
 499 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
 500 uint32_t msix_bar_size(PCIDevice *dev)
 501 {
 502     return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
 503         dev->msix_bar_size : 0;
 504 }
 505
 506 /* Send an MSI-X message */
 507 void msix_notify(PCIDevice *dev, unsigned vector)
 508 {
 509     uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
 510     uint64_t address;
 511     uint32_t data;
 512
 513     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 514         return;
 515     if (msix_is_masked(dev, vector)) {
 516         msix_set_pending(dev, vector);
 517         return;
 518     }
 519
 520 #ifdef KVM_CAP_IRQCHIP
 521     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 522         kvm_set_irq(dev->msix_irq_entries[vector].gsi, 1, NULL);
 523         return;
 524     }
 525 #endif
 526
 527     address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
 528     address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
 529     data = pci_get_long(table_entry + MSIX_MSG_DATA);
 530     stl_phys(address, data);
 531 }
 532
 533 void msix_reset(PCIDevice *dev)
 534 {
 535     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 536         return;
 537     msix_free_irq_entries(dev);
 538     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
 539             ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
 540     memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
 541     msix_mask_all(dev, dev->msix_entries_nr);
 542 }
 543
 544 /* PCI spec suggests that devices make it possible for software to configure
 545  * less vectors than supported by the device, but does not specify a standard
 546  * mechanism for devices to do so.
 547  *
 548  * We support this by asking devices to declare vectors software is going to
 549  * actually use, and checking this on the notification path. Devices that
 550  * don't want to follow the spec suggestion can declare all vectors as used. */
 551
 552 /* Mark vector as used. */
 553 int msix_vector_use(PCIDevice *dev, unsigned vector)
 554 {
 555     int ret;
 556     if (vector >= dev->msix_entries_nr)
 557         return -EINVAL;
 558     if (dev->msix_entry_used[vector]) {
 559         return 0;
 560     }
 561     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 562         ret = kvm_msix_add(dev, vector);
 563         if (ret) {
 564             return ret;
 565         }
 566     }
 567     ++dev->msix_entry_used[vector];
 568     return 0;
 569 }
 570
 571 /* Mark vector as unused. */
 572 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 573 {
 574     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
 575         return;
 576     }
 577     if (--dev->msix_entry_used[vector]) {
 578         return;
 579     }
 580     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 581         kvm_msix_del(dev, vector);
 582     }
 583     msix_clr_pending(dev, vector);
 584 }
 585
 586 void msix_unuse_all_vectors(PCIDevice *dev)
 587 {
 588     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 589         return;
 590     msix_free_irq_entries(dev);
 591 }
 592
 593 int msix_set_mask_notifier(PCIDevice *dev, unsigned vector, void *opaque)
 594 {
 595     int r = 0;
 596     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 597         return 0;
 598
 599     assert(dev->msix_mask_notifier);
 600     assert(opaque);
 601     assert(!dev->msix_mask_notifier_opaque[vector]);
 602
 603     /* Unmask the new notifier unless vector is masked. */
 604     if (!msix_is_masked(dev, vector)) {
 605         r = dev->msix_mask_notifier(dev, vector, opaque, false);
 606         if (r < 0) {
 607             return r;
 608         }
 609     }
 610     dev->msix_mask_notifier_opaque[vector] = opaque;
 611     return r;
 612 }
 613
 614 int msix_unset_mask_notifier(PCIDevice *dev, unsigned vector)
 615 {
 616     int r = 0;
 617     void *opaque;
 618     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 619         return 0;
 620
 621     opaque = dev->msix_mask_notifier_opaque[vector];
 622
 623     assert(dev->msix_mask_notifier);
 624     assert(opaque);
 625
 626     /* Mask the old notifier unless it is already masked. */
 627     if (!msix_is_masked(dev, vector)) {
 628         r = dev->msix_mask_notifier(dev, vector, opaque, true);
 629         if (r < 0) {
 630             return r;
 631         }
 632     }
 633     dev->msix_mask_notifier_opaque[vector] = NULL;
 634     return r;
 635 }