hw/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  */
  13
  14 #include "hw.h"
  15 #include "msix.h"
  16 #include "pci.h"
  17 #define QEMU_KVM_NO_CPU
  18 #include "qemu-kvm.h"
  19
  20 /* Declaration from linux/pci_regs.h */
  21 #define  PCI_CAP_ID_MSIX 0x11 /* MSI-X */
  22 #define  PCI_MSIX_FLAGS 2     /* Table at lower 11 bits */
  23 #define  PCI_MSIX_FLAGS_QSIZE   0x7FF
  24 #define  PCI_MSIX_FLAGS_ENABLE  (1 << 15)
  25 #define  PCI_MSIX_FLAGS_BIRMASK (7 << 0)
  26
  27 /* MSI-X capability structure */
  28 #define MSIX_TABLE_OFFSET 4
  29 #define MSIX_PBA_OFFSET 8
  30 #define MSIX_CAP_LENGTH 12
  31
  32 /* MSI enable bit is in byte 1 in FLAGS register */
  33 #define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1)
  34 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  35
  36 /* MSI-X table format */
  37 #define MSIX_MSG_ADDR 0
  38 #define MSIX_MSG_UPPER_ADDR 4
  39 #define MSIX_MSG_DATA 8
  40 #define MSIX_VECTOR_CTRL 12
  41 #define MSIX_ENTRY_SIZE 16
  42 #define MSIX_VECTOR_MASK 0x1
  43 #define MSIX_MAX_ENTRIES 32
  44
  45
  46 #ifdef MSIX_DEBUG
  47 #define DEBUG(fmt, ...)                                       \
  48     do {                                                      \
  49       fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__);    \
  50     } while (0)
  51 #else
  52 #define DEBUG(fmt, ...) do { } while(0)
  53 #endif
  54
  55 /* Flag for interrupt controller to declare MSI-X support */
  56 int msix_supported;
  57
  58 #ifdef CONFIG_KVM
  59 /* KVM specific MSIX helpers */
  60 static void kvm_msix_free(PCIDevice *dev)
  61 {
  62     int vector, changed = 0;
  63     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
  64         if (dev->msix_entry_used[vector]) {
  65             kvm_del_routing_entry(kvm_context, &dev->msix_irq_entries[vector]);
  66             changed = 1;
  67         }
  68     }
  69     if (changed) {
  70         kvm_commit_irq_routes(kvm_context);
  71     }
  72 }
  73
  74 static void kvm_msix_routing_entry(PCIDevice *dev, unsigned vector,
  75                                    struct kvm_irq_routing_entry *entry)
  76 {
  77     uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
  78     entry->type = KVM_IRQ_ROUTING_MSI;
  79     entry->flags = 0;
  80     entry->u.msi.address_lo = pci_get_long(table_entry + MSIX_MSG_ADDR);
  81     entry->u.msi.address_hi = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
  82     entry->u.msi.data = pci_get_long(table_entry + MSIX_MSG_DATA);
  83 }
  84
  85 static void kvm_msix_update(PCIDevice *dev, int vector,
  86                             int was_masked, int is_masked)
  87 {
  88     struct kvm_irq_routing_entry e = {}, *entry;
  89     int mask_cleared = was_masked && !is_masked;
  90     /* It is only legal to change an entry when it is masked. Therefore, it is
  91      * enough to update the routing in kernel when mask is being cleared. */
  92     if (!mask_cleared) {
  93         return;
  94     }
  95     if (!dev->msix_entry_used[vector]) {
  96         return;
  97     }
  98     entry = dev->msix_irq_entries + vector;
  99     e.gsi = entry->gsi;
 100     kvm_msix_routing_entry(dev, vector, &e);
 101     if (memcmp(&entry->u.msi, &e.u.msi, sizeof entry->u.msi)) {
 102         int r;
 103         r = kvm_update_routing_entry(kvm_context, entry, &e);
 104         if (r) {
 105             fprintf(stderr, "%s: kvm_update_routing_entry failed: %s\n", __func__,
 106                     strerror(-r));
 107             exit(1);
 108         }
 109         memcpy(&entry->u.msi, &e.u.msi, sizeof entry->u.msi);
 110         r = kvm_commit_irq_routes(kvm_context);
 111         if (r) {
 112             fprintf(stderr, "%s: kvm_commit_irq_routes failed: %s\n", __func__,
 113                     strerror(-r));
 114             exit(1);
 115         }
 116     }
 117 }
 118
 119 static int kvm_msix_add(PCIDevice *dev, unsigned vector)
 120 {
 121     struct kvm_irq_routing_entry *entry = dev->msix_irq_entries + vector;
 122     int r;
 123
 124     if (!kvm_has_gsi_routing(kvm_context)) {
 125         fprintf(stderr, "Warning: no MSI-X support found. "
 126                 "At least kernel 2.6.30 is required for MSI-X support.\n"
 127                );
 128         return -EOPNOTSUPP;
 129     }
 130
 131     r = kvm_get_irq_route_gsi(kvm_context);
 132     if (r < 0) {
 133         fprintf(stderr, "%s: kvm_get_irq_route_gsi failed: %s\n", __func__, strerror(-r));
 134         return r;
 135     }
 136     entry->gsi = r;
 137     kvm_msix_routing_entry(dev, vector, entry);
 138     r = kvm_add_routing_entry(kvm_context, entry);
 139     if (r < 0) {
 140         fprintf(stderr, "%s: kvm_add_routing_entry failed: %s\n", __func__, strerror(-r));
 141         return r;
 142     }
 143
 144     r = kvm_commit_irq_routes(kvm_context);
 145     if (r < 0) {
 146         fprintf(stderr, "%s: kvm_commit_irq_routes failed: %s\n", __func__, strerror(-r));
 147         return r;
 148     }
 149     return 0;
 150 }
 151
 152 static void kvm_msix_del(PCIDevice *dev, unsigned vector)
 153 {
 154     if (dev->msix_entry_used[vector]) {
 155         return;
 156     }
 157     kvm_del_routing_entry(kvm_context, &dev->msix_irq_entries[vector]);
 158     kvm_commit_irq_routes(kvm_context);
 159 }
 160 #else
 161
 162 static void kvm_msix_free(PCIDevice *dev) {}
 163 static void kvm_msix_update(PCIDevice *dev, int vector,
 164                             int was_masked, int is_masked) {}
 165 static int kvm_msix_add(PCIDevice *dev, unsigned vector) { return -1; }
 166 static void kvm_msix_del(PCIDevice *dev, unsigned vector) {}
 167 #endif
 168
 169 /* Reserve second half of the page for pending bits */
 170 static int msix_page_pending(PCIDevice *d)
 171 {
 172     return (d->msix_page_size / 2);
 173 }
 174
 175 /* Add MSI-X capability to the config space for the device. */
 176 /* Given a bar and its size, add MSI-X table on top of it
 177  * and fill MSI-X capability in the config space.
 178  * Original bar size must be a power of 2 or 0.
 179  * New bar size is returned. */
 180 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
 181                            unsigned bar_nr, unsigned bar_size)
 182 {
 183     int config_offset;
 184     uint8_t *config;
 185     uint32_t new_size;
 186
 187     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
 188         return -EINVAL;
 189     if (bar_size > 0x80000000)
 190         return -ENOSPC;
 191
 192     /* Add space for MSI-X structures */
 193     if (!bar_size) {
 194         new_size = pdev->msix_page_size;
 195     } else if (bar_size < pdev->msix_page_size) {
 196         bar_size = pdev->msix_page_size;
 197         new_size = pdev->msix_page_size * 2;
 198     } else
 199         new_size = bar_size * 2;
 200
 201     pdev->msix_bar_size = new_size;
 202     config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 203     if (config_offset < 0)
 204         return config_offset;
 205     config = pdev->config + config_offset;
 206
 207     pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
 208     /* Table on top of BAR */
 209     pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
 210     /* Pending bits on top of that */
 211     pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + msix_page_pending(pdev))
 212                  | bar_nr);
 213     pdev->msix_cap = config_offset;
 214     /* Make flags bit writeable. */
 215     pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
 216     return 0;
 217 }
 218
 219 static void msix_free_irq_entries(PCIDevice *dev)
 220 {
 221     int vector;
 222     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 223         kvm_msix_free(dev);
 224     }
 225
 226     for (vector = 0; vector < dev->msix_entries_nr; ++vector)
 227         dev->msix_entry_used[vector] = 0;
 228 }
 229
 230 /* Handle MSI-X capability config write. */
 231 void msix_write_config(PCIDevice *dev, uint32_t addr,
 232                        uint32_t val, int len)
 233 {
 234     unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
 235     if (addr + len <= enable_pos || addr > enable_pos)
 236         return;
 237
 238     if (msix_enabled(dev))
 239         qemu_set_irq(dev->irq[0], 0);
 240 }
 241
 242 static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
 243 {
 244     PCIDevice *dev = opaque;
 245     unsigned int offset = addr & (dev->msix_page_size - 1);
 246     void *page = dev->msix_table_page;
 247     uint32_t val = 0;
 248
 249     memcpy(&val, (void *)((char *)page + offset), 4);
 250
 251     return val;
 252 }
 253
 254 static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
 255 {
 256     fprintf(stderr, "MSI-X: only dword read is allowed!\n");
 257     return 0;
 258 }
 259
 260 static uint8_t msix_pending_mask(int vector)
 261 {
 262     return 1 << (vector % 8);
 263 }
 264
 265 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
 266 {
 267     return dev->msix_table_page + msix_page_pending(dev) + vector / 8;
 268 }
 269
 270 static int msix_is_pending(PCIDevice *dev, int vector)
 271 {
 272     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
 273 }
 274
 275 static void msix_set_pending(PCIDevice *dev, int vector)
 276 {
 277     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 278 }
 279
 280 static void msix_clr_pending(PCIDevice *dev, int vector)
 281 {
 282     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 283 }
 284
 285 static int msix_is_masked(PCIDevice *dev, int vector)
 286 {
 287     unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
 288     return dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
 289 }
 290
 291 static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
 292                              uint32_t val)
 293 {
 294     PCIDevice *dev = opaque;
 295     unsigned int offset = addr & (dev->msix_page_size - 1);
 296     int vector = offset / MSIX_ENTRY_SIZE;
 297     int was_masked = msix_is_masked(dev, vector);
 298     memcpy(dev->msix_table_page + offset, &val, 4);
 299     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 300         kvm_msix_update(dev, vector, was_masked, msix_is_masked(dev, vector));
 301     }
 302     if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
 303         msix_clr_pending(dev, vector);
 304         msix_notify(dev, vector);
 305     }
 306 }
 307
 308 static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
 309                                       uint32_t val)
 310 {
 311     fprintf(stderr, "MSI-X: only dword write is allowed!\n");
 312 }
 313
 314 static CPUWriteMemoryFunc * const msix_mmio_write[] = {
 315     msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
 316 };
 317
 318 static CPUReadMemoryFunc * const msix_mmio_read[] = {
 319     msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
 320 };
 321
 322 /* Should be called from device's map method. */
 323 void msix_mmio_map(PCIDevice *d, int region_num,
 324                    uint32_t addr, uint32_t size, int type)
 325 {
 326     uint8_t *config = d->config + d->msix_cap;
 327     uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
 328     uint32_t offset = table & ~(d->msix_page_size - 1);
 329     /* TODO: for assigned devices, we'll want to make it possible to map
 330      * pending bits separately in case they are in a separate bar. */
 331     int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
 332
 333     if (table_bir != region_num)
 334         return;
 335     if (size <= offset)
 336         return;
 337     cpu_register_physical_memory(addr + offset, size - offset,
 338                                  d->msix_mmio_index);
 339 }
 340
 341 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 342  * modified, it should be retrieved with msix_bar_size. */
 343 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 344               unsigned bar_nr, unsigned bar_size, target_phys_addr_t page_size)
 345 {
 346     int ret;
 347     /* Nothing to do if MSI is not supported by interrupt controller */
 348     if (!msix_supported)
 349         return -ENOTSUP;
 350
 351     if (nentries > MSIX_MAX_ENTRIES)
 352         return -EINVAL;
 353
 354 #ifdef KVM_CAP_IRQCHIP
 355     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 356         dev->msix_irq_entries = qemu_malloc(nentries *
 357                                             sizeof *dev->msix_irq_entries);
 358     }
 359 #endif
 360     dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
 361                                         sizeof *dev->msix_entry_used);
 362
 363     dev->msix_page_size = page_size;
 364     dev->msix_table_page = qemu_mallocz(dev->msix_page_size);
 365
 366     dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
 367                                                   msix_mmio_write, dev);
 368     if (dev->msix_mmio_index == -1) {
 369         ret = -EBUSY;
 370         goto err_index;
 371     }
 372
 373     dev->msix_entries_nr = nentries;
 374     ret = msix_add_config(dev, nentries, bar_nr, bar_size);
 375     if (ret)
 376         goto err_config;
 377
 378     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 379     return 0;
 380
 381 err_config:
 382     dev->msix_entries_nr = 0;
 383     cpu_unregister_io_memory(dev->msix_mmio_index);
 384 err_index:
 385     qemu_free(dev->msix_table_page);
 386     dev->msix_table_page = NULL;
 387     qemu_free(dev->msix_entry_used);
 388     dev->msix_entry_used = NULL;
 389     return ret;
 390 }
 391
 392 /* Clean up resources for the device. */
 393 int msix_uninit(PCIDevice *dev)
 394 {
 395     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 396         return 0;
 397     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 398     dev->msix_cap = 0;
 399     msix_free_irq_entries(dev);
 400     dev->msix_entries_nr = 0;
 401     cpu_unregister_io_memory(dev->msix_mmio_index);
 402     qemu_free(dev->msix_table_page);
 403     dev->msix_table_page = NULL;
 404     qemu_free(dev->msix_entry_used);
 405     dev->msix_entry_used = NULL;
 406     qemu_free(dev->msix_irq_entries);
 407     dev->msix_irq_entries = NULL;
 408     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 409     return 0;
 410 }
 411
 412 void msix_save(PCIDevice *dev, QEMUFile *f)
 413 {
 414     unsigned n = dev->msix_entries_nr;
 415
 416     if (!msix_supported) {
 417         return;
 418     }
 419
 420     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 421         return;
 422     }
 423     qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
 424     qemu_put_buffer(f, dev->msix_table_page + msix_page_pending(dev),
 425                     (n + 7) / 8);
 426 }
 427
 428 /* Should be called after restoring the config space. */
 429 void msix_load(PCIDevice *dev, QEMUFile *f)
 430 {
 431     unsigned n = dev->msix_entries_nr;
 432
 433     if (!msix_supported)
 434         return;
 435
 436     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 437         return;
 438     }
 439
 440     msix_free_irq_entries(dev);
 441     qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
 442     qemu_get_buffer(f, dev->msix_table_page + msix_page_pending(dev),
 443                     (n + 7) / 8);
 444 }
 445
 446 /* Does device support MSI-X? */
 447 int msix_present(PCIDevice *dev)
 448 {
 449     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 450 }
 451
 452 /* Is MSI-X enabled? */
 453 int msix_enabled(PCIDevice *dev)
 454 {
 455     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 456         (dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &
 457          MSIX_ENABLE_MASK);
 458 }
 459
 460 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
 461 uint32_t msix_bar_size(PCIDevice *dev)
 462 {
 463     return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
 464         dev->msix_bar_size : 0;
 465 }
 466
 467 /* Send an MSI-X message */
 468 void msix_notify(PCIDevice *dev, unsigned vector)
 469 {
 470     uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
 471     uint64_t address;
 472     uint32_t data;
 473
 474     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 475         return;
 476     if (msix_is_masked(dev, vector)) {
 477         msix_set_pending(dev, vector);
 478         return;
 479     }
 480
 481 #ifdef KVM_CAP_IRQCHIP
 482     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 483         kvm_set_irq(dev->msix_irq_entries[vector].gsi, 1, NULL);
 484         return;
 485     }
 486 #endif
 487
 488     address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
 489     address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
 490     data = pci_get_long(table_entry + MSIX_MSG_DATA);
 491     stl_phys(address, data);
 492 }
 493
 494 void msix_reset(PCIDevice *dev)
 495 {
 496     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 497         return;
 498     msix_free_irq_entries(dev);
 499     dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK;
 500     memset(dev->msix_table_page, 0, dev->msix_page_size);
 501 }
 502
 503 /* PCI spec suggests that devices make it possible for software to configure
 504  * less vectors than supported by the device, but does not specify a standard
 505  * mechanism for devices to do so.
 506  *
 507  * We support this by asking devices to declare vectors software is going to
 508  * actually use, and checking this on the notification path. Devices that
 509  * don't want to follow the spec suggestion can declare all vectors as used. */
 510
 511 /* Mark vector as used. */
 512 int msix_vector_use(PCIDevice *dev, unsigned vector)
 513 {
 514     int ret;
 515     if (vector >= dev->msix_entries_nr)
 516         return -EINVAL;
 517     if (dev->msix_entry_used[vector]) {
 518         return 0;
 519     }
 520     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 521         ret = kvm_msix_add(dev, vector);
 522         if (ret) {
 523             return ret;
 524         }
 525     }
 526     ++dev->msix_entry_used[vector];
 527     return 0;
 528 }
 529
 530 /* Mark vector as unused. */
 531 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 532 {
 533     if (vector < dev->msix_entries_nr && dev->msix_entry_used[vector]) {
 534         --dev->msix_entry_used[vector];
 535         if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 536             kvm_msix_del(dev, vector);
 537         }
 538     }
 539 }