2 * QEMU PIIX4 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 static void piix4_reset(void *opaque
)
35 PCIDevice
*d
= opaque
;
36 uint8_t *pci_conf
= d
->config
;
38 pci_conf
[0x04] = 0x07; // master, memory and I/O
39 pci_conf
[0x05] = 0x00;
40 pci_conf
[0x06] = 0x00;
41 pci_conf
[0x07] = 0x02; // PCI_status_devsel_medium
42 pci_conf
[0x4c] = 0x4d;
43 pci_conf
[0x4e] = 0x03;
44 pci_conf
[0x4f] = 0x00;
45 pci_conf
[0x60] = 0x0a; // PCI A -> IRQ 10
46 pci_conf
[0x61] = 0x0a; // PCI B -> IRQ 10
47 pci_conf
[0x62] = 0x0b; // PCI C -> IRQ 11
48 pci_conf
[0x63] = 0x0b; // PCI D -> IRQ 11
49 pci_conf
[0x69] = 0x02;
50 pci_conf
[0x70] = 0x80;
51 pci_conf
[0x76] = 0x0c;
52 pci_conf
[0x77] = 0x0c;
53 pci_conf
[0x78] = 0x02;
54 pci_conf
[0x79] = 0x00;
55 pci_conf
[0x80] = 0x00;
56 pci_conf
[0x82] = 0x00;
57 pci_conf
[0xa0] = 0x08;
58 pci_conf
[0xa2] = 0x00;
59 pci_conf
[0xa3] = 0x00;
60 pci_conf
[0xa4] = 0x00;
61 pci_conf
[0xa5] = 0x00;
62 pci_conf
[0xa6] = 0x00;
63 pci_conf
[0xa7] = 0x00;
64 pci_conf
[0xa8] = 0x0f;
65 pci_conf
[0xaa] = 0x00;
66 pci_conf
[0xab] = 0x00;
67 pci_conf
[0xac] = 0x00;
68 pci_conf
[0xae] = 0x00;
71 static void piix_save(QEMUFile
* f
, void *opaque
)
73 PCIDevice
*d
= opaque
;
74 pci_device_save(d
, f
);
77 static int piix_load(QEMUFile
* f
, void *opaque
, int version_id
)
79 PCIDevice
*d
= opaque
;
82 return pci_device_load(d
, f
);
85 static int piix4_initfn(PCIDevice
*d
)
89 isa_bus_new(&d
->qdev
);
90 register_savevm(&d
->qdev
, "PIIX4", 0, 2, piix_save
, piix_load
, d
);
93 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
94 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82371AB_0
); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
95 pci_config_set_class(pci_conf
, PCI_CLASS_BRIDGE_ISA
);
98 qemu_register_reset(piix4_reset
, d
);
102 int piix4_init(PCIBus
*bus
, int devfn
)
106 d
= pci_create_simple_multifunction(bus
, devfn
, true, "PIIX4");
110 static PCIDeviceInfo piix4_info
[] = {
112 .qdev
.name
= "PIIX4",
113 .qdev
.desc
= "ISA bridge",
114 .qdev
.size
= sizeof(PCIDevice
),
117 .init
= piix4_initfn
,
123 static void piix4_register(void)
125 pci_qdev_register_many(piix4_info
);
127 device_init(piix4_register
);