4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu-common.h"
21 #ifdef CONFIG_USER_ONLY
33 #include "qemu-char.h"
39 #define MAX_PACKET_LENGTH 4096
41 #include "qemu_socket.h"
49 GDB_SIGNAL_UNKNOWN
= 143
52 #ifdef CONFIG_USER_ONLY
54 /* Map target signal numbers to GDB protocol signal numbers and vice
55 * versa. For user emulation's currently supported systems, we can
56 * assume most signals are defined.
59 static int gdb_signal_table
[] = {
219 /* In system mode we only need SIGINT and SIGTRAP; other signals
220 are not yet supported. */
227 static int gdb_signal_table
[] = {
237 #ifdef CONFIG_USER_ONLY
238 static int target_signal_to_gdb (int sig
)
241 for (i
= 0; i
< ARRAY_SIZE (gdb_signal_table
); i
++)
242 if (gdb_signal_table
[i
] == sig
)
244 return GDB_SIGNAL_UNKNOWN
;
248 static int gdb_signal_to_target (int sig
)
250 if (sig
< ARRAY_SIZE (gdb_signal_table
))
251 return gdb_signal_table
[sig
];
258 typedef struct GDBRegisterState
{
264 struct GDBRegisterState
*next
;
275 typedef struct GDBState
{
276 CPUState
*c_cpu
; /* current CPU for step/continue ops */
277 CPUState
*g_cpu
; /* current CPU for other ops */
278 CPUState
*query_cpu
; /* for q{f|s}ThreadInfo */
279 enum RSState state
; /* parsing state */
280 char line_buf
[MAX_PACKET_LENGTH
];
283 uint8_t last_packet
[MAX_PACKET_LENGTH
+ 4];
286 #ifdef CONFIG_USER_ONLY
290 CharDriverState
*chr
;
291 CharDriverState
*mon_chr
;
295 /* By default use no IRQs and no timers while single stepping so as to
296 * make single stepping like an ICE HW step.
298 static int sstep_flags
= SSTEP_ENABLE
|SSTEP_NOIRQ
|SSTEP_NOTIMER
;
300 static GDBState
*gdbserver_state
;
302 /* This is an ugly hack to cope with both new and old gdb.
303 If gdb sends qXfer:features:read then assume we're talking to a newish
304 gdb that understands target descriptions. */
305 static int gdb_has_xml
;
307 #ifdef CONFIG_USER_ONLY
308 /* XXX: This is not thread safe. Do we care? */
309 static int gdbserver_fd
= -1;
311 static int get_char(GDBState
*s
)
317 ret
= recv(s
->fd
, &ch
, 1, 0);
319 if (errno
== ECONNRESET
)
321 if (errno
!= EINTR
&& errno
!= EAGAIN
)
323 } else if (ret
== 0) {
335 static gdb_syscall_complete_cb gdb_current_syscall_cb
;
343 /* If gdb is connected when the first semihosting syscall occurs then use
344 remote gdb syscalls. Otherwise use native file IO. */
345 int use_gdb_syscalls(void)
347 if (gdb_syscall_mode
== GDB_SYS_UNKNOWN
) {
348 gdb_syscall_mode
= (gdbserver_state
? GDB_SYS_ENABLED
351 return gdb_syscall_mode
== GDB_SYS_ENABLED
;
354 /* Resume execution. */
355 static inline void gdb_continue(GDBState
*s
)
357 #ifdef CONFIG_USER_ONLY
358 s
->running_state
= 1;
364 static void put_buffer(GDBState
*s
, const uint8_t *buf
, int len
)
366 #ifdef CONFIG_USER_ONLY
370 ret
= send(s
->fd
, buf
, len
, 0);
372 if (errno
!= EINTR
&& errno
!= EAGAIN
)
380 qemu_chr_write(s
->chr
, buf
, len
);
384 static inline int fromhex(int v
)
386 if (v
>= '0' && v
<= '9')
388 else if (v
>= 'A' && v
<= 'F')
390 else if (v
>= 'a' && v
<= 'f')
396 static inline int tohex(int v
)
404 static void memtohex(char *buf
, const uint8_t *mem
, int len
)
409 for(i
= 0; i
< len
; i
++) {
411 *q
++ = tohex(c
>> 4);
412 *q
++ = tohex(c
& 0xf);
417 static void hextomem(uint8_t *mem
, const char *buf
, int len
)
421 for(i
= 0; i
< len
; i
++) {
422 mem
[i
] = (fromhex(buf
[0]) << 4) | fromhex(buf
[1]);
427 /* return -1 if error, 0 if OK */
428 static int put_packet_binary(GDBState
*s
, const char *buf
, int len
)
439 for(i
= 0; i
< len
; i
++) {
443 *(p
++) = tohex((csum
>> 4) & 0xf);
444 *(p
++) = tohex((csum
) & 0xf);
446 s
->last_packet_len
= p
- s
->last_packet
;
447 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
449 #ifdef CONFIG_USER_ONLY
462 /* return -1 if error, 0 if OK */
463 static int put_packet(GDBState
*s
, const char *buf
)
466 printf("reply='%s'\n", buf
);
469 return put_packet_binary(s
, buf
, strlen(buf
));
472 /* The GDB remote protocol transfers values in target byte order. This means
473 we can use the raw memory access routines to access the value buffer.
474 Conveniently, these also handle the case where the buffer is mis-aligned.
476 #define GET_REG8(val) do { \
477 stb_p(mem_buf, val); \
480 #define GET_REG16(val) do { \
481 stw_p(mem_buf, val); \
484 #define GET_REG32(val) do { \
485 stl_p(mem_buf, val); \
488 #define GET_REG64(val) do { \
489 stq_p(mem_buf, val); \
493 #if TARGET_LONG_BITS == 64
494 #define GET_REGL(val) GET_REG64(val)
495 #define ldtul_p(addr) ldq_p(addr)
497 #define GET_REGL(val) GET_REG32(val)
498 #define ldtul_p(addr) ldl_p(addr)
501 #if defined(TARGET_I386)
504 static const int gpr_map
[16] = {
505 R_EAX
, R_EBX
, R_ECX
, R_EDX
, R_ESI
, R_EDI
, R_EBP
, R_ESP
,
506 8, 9, 10, 11, 12, 13, 14, 15
509 #define gpr_map gpr_map32
511 static const int gpr_map32
[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
513 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
515 #define IDX_IP_REG CPU_NB_REGS
516 #define IDX_FLAGS_REG (IDX_IP_REG + 1)
517 #define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
518 #define IDX_FP_REGS (IDX_SEG_REGS + 6)
519 #define IDX_XMM_REGS (IDX_FP_REGS + 16)
520 #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
522 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
524 if (n
< CPU_NB_REGS
) {
525 if (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
) {
526 GET_REG64(env
->regs
[gpr_map
[n
]]);
527 } else if (n
< CPU_NB_REGS32
) {
528 GET_REG32(env
->regs
[gpr_map32
[n
]]);
530 } else if (n
>= IDX_FP_REGS
&& n
< IDX_FP_REGS
+ 8) {
531 #ifdef USE_X86LDOUBLE
532 /* FIXME: byteswap float values - after fixing fpregs layout. */
533 memcpy(mem_buf
, &env
->fpregs
[n
- IDX_FP_REGS
], 10);
535 memset(mem_buf
, 0, 10);
538 } else if (n
>= IDX_XMM_REGS
&& n
< IDX_XMM_REGS
+ CPU_NB_REGS
) {
540 if (n
< CPU_NB_REGS32
||
541 (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
)) {
542 stq_p(mem_buf
, env
->xmm_regs
[n
].XMM_Q(0));
543 stq_p(mem_buf
+ 8, env
->xmm_regs
[n
].XMM_Q(1));
549 if (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
) {
554 case IDX_FLAGS_REG
: GET_REG32(env
->eflags
);
556 case IDX_SEG_REGS
: GET_REG32(env
->segs
[R_CS
].selector
);
557 case IDX_SEG_REGS
+ 1: GET_REG32(env
->segs
[R_SS
].selector
);
558 case IDX_SEG_REGS
+ 2: GET_REG32(env
->segs
[R_DS
].selector
);
559 case IDX_SEG_REGS
+ 3: GET_REG32(env
->segs
[R_ES
].selector
);
560 case IDX_SEG_REGS
+ 4: GET_REG32(env
->segs
[R_FS
].selector
);
561 case IDX_SEG_REGS
+ 5: GET_REG32(env
->segs
[R_GS
].selector
);
563 case IDX_FP_REGS
+ 8: GET_REG32(env
->fpuc
);
564 case IDX_FP_REGS
+ 9: GET_REG32((env
->fpus
& ~0x3800) |
565 (env
->fpstt
& 0x7) << 11);
566 case IDX_FP_REGS
+ 10: GET_REG32(0); /* ftag */
567 case IDX_FP_REGS
+ 11: GET_REG32(0); /* fiseg */
568 case IDX_FP_REGS
+ 12: GET_REG32(0); /* fioff */
569 case IDX_FP_REGS
+ 13: GET_REG32(0); /* foseg */
570 case IDX_FP_REGS
+ 14: GET_REG32(0); /* fooff */
571 case IDX_FP_REGS
+ 15: GET_REG32(0); /* fop */
573 case IDX_MXCSR_REG
: GET_REG32(env
->mxcsr
);
579 static int cpu_x86_gdb_load_seg(CPUState
*env
, int sreg
, uint8_t *mem_buf
)
581 uint16_t selector
= ldl_p(mem_buf
);
583 if (selector
!= env
->segs
[sreg
].selector
) {
584 #if defined(CONFIG_USER_ONLY)
585 cpu_x86_load_seg(env
, sreg
, selector
);
587 unsigned int limit
, flags
;
590 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
591 base
= selector
<< 4;
595 if (!cpu_x86_get_descr_debug(env
, selector
, &base
, &limit
, &flags
))
598 cpu_x86_load_seg_cache(env
, sreg
, selector
, base
, limit
, flags
);
604 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
608 if (n
< CPU_NB_REGS
) {
609 if (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
) {
610 env
->regs
[gpr_map
[n
]] = ldtul_p(mem_buf
);
611 return sizeof(target_ulong
);
612 } else if (n
< CPU_NB_REGS32
) {
614 env
->regs
[n
] &= ~0xffffffffUL
;
615 env
->regs
[n
] |= (uint32_t)ldl_p(mem_buf
);
618 } else if (n
>= IDX_FP_REGS
&& n
< IDX_FP_REGS
+ 8) {
619 #ifdef USE_X86LDOUBLE
620 /* FIXME: byteswap float values - after fixing fpregs layout. */
621 memcpy(&env
->fpregs
[n
- IDX_FP_REGS
], mem_buf
, 10);
624 } else if (n
>= IDX_XMM_REGS
&& n
< IDX_XMM_REGS
+ CPU_NB_REGS
) {
626 if (n
< CPU_NB_REGS32
||
627 (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
)) {
628 env
->xmm_regs
[n
].XMM_Q(0) = ldq_p(mem_buf
);
629 env
->xmm_regs
[n
].XMM_Q(1) = ldq_p(mem_buf
+ 8);
635 if (TARGET_LONG_BITS
== 64 && env
->hflags
& HF_CS64_MASK
) {
636 env
->eip
= ldq_p(mem_buf
);
639 env
->eip
&= ~0xffffffffUL
;
640 env
->eip
|= (uint32_t)ldl_p(mem_buf
);
644 env
->eflags
= ldl_p(mem_buf
);
647 case IDX_SEG_REGS
: return cpu_x86_gdb_load_seg(env
, R_CS
, mem_buf
);
648 case IDX_SEG_REGS
+ 1: return cpu_x86_gdb_load_seg(env
, R_SS
, mem_buf
);
649 case IDX_SEG_REGS
+ 2: return cpu_x86_gdb_load_seg(env
, R_DS
, mem_buf
);
650 case IDX_SEG_REGS
+ 3: return cpu_x86_gdb_load_seg(env
, R_ES
, mem_buf
);
651 case IDX_SEG_REGS
+ 4: return cpu_x86_gdb_load_seg(env
, R_FS
, mem_buf
);
652 case IDX_SEG_REGS
+ 5: return cpu_x86_gdb_load_seg(env
, R_GS
, mem_buf
);
654 case IDX_FP_REGS
+ 8:
655 env
->fpuc
= ldl_p(mem_buf
);
657 case IDX_FP_REGS
+ 9:
658 tmp
= ldl_p(mem_buf
);
659 env
->fpstt
= (tmp
>> 11) & 7;
660 env
->fpus
= tmp
& ~0x3800;
662 case IDX_FP_REGS
+ 10: /* ftag */ return 4;
663 case IDX_FP_REGS
+ 11: /* fiseg */ return 4;
664 case IDX_FP_REGS
+ 12: /* fioff */ return 4;
665 case IDX_FP_REGS
+ 13: /* foseg */ return 4;
666 case IDX_FP_REGS
+ 14: /* fooff */ return 4;
667 case IDX_FP_REGS
+ 15: /* fop */ return 4;
670 env
->mxcsr
= ldl_p(mem_buf
);
674 /* Unrecognised register. */
678 #elif defined (TARGET_PPC)
680 /* Old gdb always expects FP registers. Newer (xml-aware) gdb only
681 expects whatever the target description contains. Due to a
682 historical mishap the FP registers appear in between core integer
683 regs and PC, MSR, CR, and so forth. We hack round this by giving the
684 FP regs zero size when talking to a newer gdb. */
685 #define NUM_CORE_REGS 71
686 #if defined (TARGET_PPC64)
687 #define GDB_CORE_XML "power64-core.xml"
689 #define GDB_CORE_XML "power-core.xml"
692 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
696 GET_REGL(env
->gpr
[n
]);
701 stfq_p(mem_buf
, env
->fpr
[n
-32]);
705 case 64: GET_REGL(env
->nip
);
706 case 65: GET_REGL(env
->msr
);
711 for (i
= 0; i
< 8; i
++)
712 cr
|= env
->crf
[i
] << (32 - ((i
+ 1) * 4));
715 case 67: GET_REGL(env
->lr
);
716 case 68: GET_REGL(env
->ctr
);
717 case 69: GET_REGL(env
->xer
);
722 GET_REG32(0); /* fpscr */
729 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
733 env
->gpr
[n
] = ldtul_p(mem_buf
);
734 return sizeof(target_ulong
);
739 env
->fpr
[n
-32] = ldfq_p(mem_buf
);
744 env
->nip
= ldtul_p(mem_buf
);
745 return sizeof(target_ulong
);
747 ppc_store_msr(env
, ldtul_p(mem_buf
));
748 return sizeof(target_ulong
);
751 uint32_t cr
= ldl_p(mem_buf
);
753 for (i
= 0; i
< 8; i
++)
754 env
->crf
[i
] = (cr
>> (32 - ((i
+ 1) * 4))) & 0xF;
758 env
->lr
= ldtul_p(mem_buf
);
759 return sizeof(target_ulong
);
761 env
->ctr
= ldtul_p(mem_buf
);
762 return sizeof(target_ulong
);
764 env
->xer
= ldtul_p(mem_buf
);
765 return sizeof(target_ulong
);
776 #elif defined (TARGET_SPARC)
778 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
779 #define NUM_CORE_REGS 86
781 #define NUM_CORE_REGS 72
785 #define GET_REGA(val) GET_REG32(val)
787 #define GET_REGA(val) GET_REGL(val)
790 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
794 GET_REGA(env
->gregs
[n
]);
797 /* register window */
798 GET_REGA(env
->regwptr
[n
- 8]);
800 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
803 GET_REG32(*((uint32_t *)&env
->fpr
[n
- 32]));
805 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
807 case 64: GET_REGA(env
->y
);
808 case 65: GET_REGA(GET_PSR(env
));
809 case 66: GET_REGA(env
->wim
);
810 case 67: GET_REGA(env
->tbr
);
811 case 68: GET_REGA(env
->pc
);
812 case 69: GET_REGA(env
->npc
);
813 case 70: GET_REGA(env
->fsr
);
814 case 71: GET_REGA(0); /* csr */
815 default: GET_REGA(0);
820 GET_REG32(*((uint32_t *)&env
->fpr
[n
- 32]));
823 /* f32-f62 (double width, even numbers only) */
826 val
= (uint64_t)*((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 32]) << 32;
827 val
|= *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 33]);
831 case 80: GET_REGL(env
->pc
);
832 case 81: GET_REGL(env
->npc
);
833 case 82: GET_REGL(((uint64_t)GET_CCR(env
) << 32) |
834 ((env
->asi
& 0xff) << 24) |
835 ((env
->pstate
& 0xfff) << 8) |
837 case 83: GET_REGL(env
->fsr
);
838 case 84: GET_REGL(env
->fprs
);
839 case 85: GET_REGL(env
->y
);
845 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
847 #if defined(TARGET_ABI32)
850 tmp
= ldl_p(mem_buf
);
854 tmp
= ldtul_p(mem_buf
);
861 /* register window */
862 env
->regwptr
[n
- 8] = tmp
;
864 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
867 *((uint32_t *)&env
->fpr
[n
- 32]) = tmp
;
869 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
871 case 64: env
->y
= tmp
; break;
872 case 65: PUT_PSR(env
, tmp
); break;
873 case 66: env
->wim
= tmp
; break;
874 case 67: env
->tbr
= tmp
; break;
875 case 68: env
->pc
= tmp
; break;
876 case 69: env
->npc
= tmp
; break;
877 case 70: env
->fsr
= tmp
; break;
885 env
->fpr
[n
] = ldfl_p(mem_buf
);
888 /* f32-f62 (double width, even numbers only) */
889 *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 32]) = tmp
>> 32;
890 *((uint32_t *)&env
->fpr
[(n
- 64) * 2 + 33]) = tmp
;
893 case 80: env
->pc
= tmp
; break;
894 case 81: env
->npc
= tmp
; break;
896 PUT_CCR(env
, tmp
>> 32);
897 env
->asi
= (tmp
>> 24) & 0xff;
898 env
->pstate
= (tmp
>> 8) & 0xfff;
899 PUT_CWP64(env
, tmp
& 0xff);
901 case 83: env
->fsr
= tmp
; break;
902 case 84: env
->fprs
= tmp
; break;
903 case 85: env
->y
= tmp
; break;
910 #elif defined (TARGET_ARM)
912 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
913 whatever the target description contains. Due to a historical mishap
914 the FPA registers appear in between core integer regs and the CPSR.
915 We hack round this by giving the FPA regs zero size when talking to a
917 #define NUM_CORE_REGS 26
918 #define GDB_CORE_XML "arm-core.xml"
920 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
923 /* Core integer register. */
924 GET_REG32(env
->regs
[n
]);
930 memset(mem_buf
, 0, 12);
935 /* FPA status register. */
941 GET_REG32(cpsr_read(env
));
943 /* Unknown register. */
947 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
951 tmp
= ldl_p(mem_buf
);
953 /* Mask out low bit of PC to workaround gdb bugs. This will probably
954 cause problems if we ever implement the Jazelle DBX extensions. */
959 /* Core integer register. */
963 if (n
< 24) { /* 16-23 */
964 /* FPA registers (ignored). */
971 /* FPA status register (ignored). */
977 cpsr_write (env
, tmp
, 0xffffffff);
980 /* Unknown register. */
984 #elif defined (TARGET_M68K)
986 #define NUM_CORE_REGS 18
988 #define GDB_CORE_XML "cf-core.xml"
990 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
994 GET_REG32(env
->dregs
[n
]);
997 GET_REG32(env
->aregs
[n
- 8]);
1000 case 16: GET_REG32(env
->sr
);
1001 case 17: GET_REG32(env
->pc
);
1004 /* FP registers not included here because they vary between
1005 ColdFire and m68k. Use XML bits for these. */
1009 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1013 tmp
= ldl_p(mem_buf
);
1017 env
->dregs
[n
] = tmp
;
1018 } else if (n
< 16) {
1020 env
->aregs
[n
- 8] = tmp
;
1023 case 16: env
->sr
= tmp
; break;
1024 case 17: env
->pc
= tmp
; break;
1030 #elif defined (TARGET_MIPS)
1032 #define NUM_CORE_REGS 73
1034 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1037 GET_REGL(env
->active_tc
.gpr
[n
]);
1039 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
1040 if (n
>= 38 && n
< 70) {
1041 if (env
->CP0_Status
& (1 << CP0St_FR
))
1042 GET_REGL(env
->active_fpu
.fpr
[n
- 38].d
);
1044 GET_REGL(env
->active_fpu
.fpr
[n
- 38].w
[FP_ENDIAN_IDX
]);
1047 case 70: GET_REGL((int32_t)env
->active_fpu
.fcr31
);
1048 case 71: GET_REGL((int32_t)env
->active_fpu
.fcr0
);
1052 case 32: GET_REGL((int32_t)env
->CP0_Status
);
1053 case 33: GET_REGL(env
->active_tc
.LO
[0]);
1054 case 34: GET_REGL(env
->active_tc
.HI
[0]);
1055 case 35: GET_REGL(env
->CP0_BadVAddr
);
1056 case 36: GET_REGL((int32_t)env
->CP0_Cause
);
1057 case 37: GET_REGL(env
->active_tc
.PC
| !!(env
->hflags
& MIPS_HFLAG_M16
));
1058 case 72: GET_REGL(0); /* fp */
1059 case 89: GET_REGL((int32_t)env
->CP0_PRid
);
1061 if (n
>= 73 && n
<= 88) {
1062 /* 16 embedded regs. */
1069 /* convert MIPS rounding mode in FCR31 to IEEE library */
1070 static unsigned int ieee_rm
[] =
1072 float_round_nearest_even
,
1073 float_round_to_zero
,
1077 #define RESTORE_ROUNDING_MODE \
1078 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1080 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1084 tmp
= ldtul_p(mem_buf
);
1087 env
->active_tc
.gpr
[n
] = tmp
;
1088 return sizeof(target_ulong
);
1090 if (env
->CP0_Config1
& (1 << CP0C1_FP
)
1091 && n
>= 38 && n
< 73) {
1093 if (env
->CP0_Status
& (1 << CP0St_FR
))
1094 env
->active_fpu
.fpr
[n
- 38].d
= tmp
;
1096 env
->active_fpu
.fpr
[n
- 38].w
[FP_ENDIAN_IDX
] = tmp
;
1100 env
->active_fpu
.fcr31
= tmp
& 0xFF83FFFF;
1101 /* set rounding mode */
1102 RESTORE_ROUNDING_MODE
;
1103 #ifndef CONFIG_SOFTFLOAT
1104 /* no floating point exception for native float */
1105 SET_FP_ENABLE(env
->active_fpu
.fcr31
, 0);
1108 case 71: env
->active_fpu
.fcr0
= tmp
; break;
1110 return sizeof(target_ulong
);
1113 case 32: env
->CP0_Status
= tmp
; break;
1114 case 33: env
->active_tc
.LO
[0] = tmp
; break;
1115 case 34: env
->active_tc
.HI
[0] = tmp
; break;
1116 case 35: env
->CP0_BadVAddr
= tmp
; break;
1117 case 36: env
->CP0_Cause
= tmp
; break;
1119 env
->active_tc
.PC
= tmp
& ~(target_ulong
)1;
1121 env
->hflags
|= MIPS_HFLAG_M16
;
1123 env
->hflags
&= ~(MIPS_HFLAG_M16
);
1126 case 72: /* fp, ignored */ break;
1130 /* Other registers are readonly. Ignore writes. */
1134 return sizeof(target_ulong
);
1136 #elif defined (TARGET_SH4)
1138 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1139 /* FIXME: We should use XML for this. */
1141 #define NUM_CORE_REGS 59
1143 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1146 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
1147 GET_REGL(env
->gregs
[n
+ 16]);
1149 GET_REGL(env
->gregs
[n
]);
1151 } else if (n
< 16) {
1152 GET_REGL(env
->gregs
[n
- 8]);
1153 } else if (n
>= 25 && n
< 41) {
1154 GET_REGL(env
->fregs
[(n
- 25) + ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
1155 } else if (n
>= 43 && n
< 51) {
1156 GET_REGL(env
->gregs
[n
- 43]);
1157 } else if (n
>= 51 && n
< 59) {
1158 GET_REGL(env
->gregs
[n
- (51 - 16)]);
1161 case 16: GET_REGL(env
->pc
);
1162 case 17: GET_REGL(env
->pr
);
1163 case 18: GET_REGL(env
->gbr
);
1164 case 19: GET_REGL(env
->vbr
);
1165 case 20: GET_REGL(env
->mach
);
1166 case 21: GET_REGL(env
->macl
);
1167 case 22: GET_REGL(env
->sr
);
1168 case 23: GET_REGL(env
->fpul
);
1169 case 24: GET_REGL(env
->fpscr
);
1170 case 41: GET_REGL(env
->ssr
);
1171 case 42: GET_REGL(env
->spc
);
1177 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1181 tmp
= ldl_p(mem_buf
);
1184 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
1185 env
->gregs
[n
+ 16] = tmp
;
1187 env
->gregs
[n
] = tmp
;
1190 } else if (n
< 16) {
1191 env
->gregs
[n
- 8] = tmp
;
1193 } else if (n
>= 25 && n
< 41) {
1194 env
->fregs
[(n
- 25) + ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)] = tmp
;
1195 } else if (n
>= 43 && n
< 51) {
1196 env
->gregs
[n
- 43] = tmp
;
1198 } else if (n
>= 51 && n
< 59) {
1199 env
->gregs
[n
- (51 - 16)] = tmp
;
1203 case 16: env
->pc
= tmp
;
1204 case 17: env
->pr
= tmp
;
1205 case 18: env
->gbr
= tmp
;
1206 case 19: env
->vbr
= tmp
;
1207 case 20: env
->mach
= tmp
;
1208 case 21: env
->macl
= tmp
;
1209 case 22: env
->sr
= tmp
;
1210 case 23: env
->fpul
= tmp
;
1211 case 24: env
->fpscr
= tmp
;
1212 case 41: env
->ssr
= tmp
;
1213 case 42: env
->spc
= tmp
;
1219 #elif defined (TARGET_MICROBLAZE)
1221 #define NUM_CORE_REGS (32 + 5)
1223 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1226 GET_REG32(env
->regs
[n
]);
1228 GET_REG32(env
->sregs
[n
- 32]);
1233 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1237 if (n
> NUM_CORE_REGS
)
1240 tmp
= ldl_p(mem_buf
);
1245 env
->sregs
[n
- 32] = tmp
;
1249 #elif defined (TARGET_CRIS)
1251 #define NUM_CORE_REGS 49
1253 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1257 srs
= env
->pregs
[PR_SRS
];
1259 GET_REG32(env
->regs
[n
]);
1262 if (n
>= 21 && n
< 32) {
1263 GET_REG32(env
->pregs
[n
- 16]);
1265 if (n
>= 33 && n
< 49) {
1266 GET_REG32(env
->sregs
[srs
][n
- 33]);
1269 case 16: GET_REG8(env
->pregs
[0]);
1270 case 17: GET_REG8(env
->pregs
[1]);
1271 case 18: GET_REG32(env
->pregs
[2]);
1272 case 19: GET_REG8(srs
);
1273 case 20: GET_REG16(env
->pregs
[4]);
1274 case 32: GET_REG32(env
->pc
);
1280 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1287 tmp
= ldl_p(mem_buf
);
1293 if (n
>= 21 && n
< 32) {
1294 env
->pregs
[n
- 16] = tmp
;
1297 /* FIXME: Should support function regs be writable? */
1301 case 18: env
->pregs
[PR_PID
] = tmp
; break;
1304 case 32: env
->pc
= tmp
; break;
1309 #elif defined (TARGET_ALPHA)
1311 #define NUM_CORE_REGS 65
1313 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1316 GET_REGL(env
->ir
[n
]);
1324 val
= *((uint64_t *)&env
->fir
[n
-32]);
1328 GET_REGL(env
->fpcr
);
1340 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1343 tmp
= ldtul_p(mem_buf
);
1349 if (n
> 31 && n
< 63) {
1350 env
->fir
[n
- 32] = ldfl_p(mem_buf
);
1359 #elif defined (TARGET_S390X)
1361 #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1363 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1366 case S390_PSWM_REGNUM
: GET_REGL(env
->psw
.mask
); break;
1367 case S390_PSWA_REGNUM
: GET_REGL(env
->psw
.addr
); break;
1368 case S390_R0_REGNUM
... S390_R15_REGNUM
:
1369 GET_REGL(env
->regs
[n
-S390_R0_REGNUM
]); break;
1370 case S390_A0_REGNUM
... S390_A15_REGNUM
:
1371 GET_REG32(env
->aregs
[n
-S390_A0_REGNUM
]); break;
1372 case S390_FPC_REGNUM
: GET_REG32(env
->fpc
); break;
1373 case S390_F0_REGNUM
... S390_F15_REGNUM
:
1376 case S390_PC_REGNUM
: GET_REGL(env
->psw
.addr
); break;
1377 case S390_CC_REGNUM
: GET_REG32(env
->cc
); break;
1383 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1388 tmpl
= ldtul_p(mem_buf
);
1389 tmp32
= ldl_p(mem_buf
);
1392 case S390_PSWM_REGNUM
: env
->psw
.mask
= tmpl
; break;
1393 case S390_PSWA_REGNUM
: env
->psw
.addr
= tmpl
; break;
1394 case S390_R0_REGNUM
... S390_R15_REGNUM
:
1395 env
->regs
[n
-S390_R0_REGNUM
] = tmpl
; break;
1396 case S390_A0_REGNUM
... S390_A15_REGNUM
:
1397 env
->aregs
[n
-S390_A0_REGNUM
] = tmp32
; r
=4; break;
1398 case S390_FPC_REGNUM
: env
->fpc
= tmp32
; r
=4; break;
1399 case S390_F0_REGNUM
... S390_F15_REGNUM
:
1402 case S390_PC_REGNUM
: env
->psw
.addr
= tmpl
; break;
1403 case S390_CC_REGNUM
: env
->cc
= tmp32
; r
=4; break;
1410 #define NUM_CORE_REGS 0
1412 static int cpu_gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1417 static int cpu_gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int n
)
1424 static int num_g_regs
= NUM_CORE_REGS
;
1427 /* Encode data using the encoding for 'x' packets. */
1428 static int memtox(char *buf
, const char *mem
, int len
)
1436 case '#': case '$': case '*': case '}':
1448 static const char *get_feature_xml(const char *p
, const char **newp
)
1450 extern const char *const xml_builtin
[][2];
1454 static char target_xml
[1024];
1457 while (p
[len
] && p
[len
] != ':')
1462 if (strncmp(p
, "target.xml", len
) == 0) {
1463 /* Generate the XML description for this CPU. */
1464 if (!target_xml
[0]) {
1465 GDBRegisterState
*r
;
1467 snprintf(target_xml
, sizeof(target_xml
),
1468 "<?xml version=\"1.0\"?>"
1469 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1471 "<xi:include href=\"%s\"/>",
1474 for (r
= first_cpu
->gdb_regs
; r
; r
= r
->next
) {
1475 pstrcat(target_xml
, sizeof(target_xml
), "<xi:include href=\"");
1476 pstrcat(target_xml
, sizeof(target_xml
), r
->xml
);
1477 pstrcat(target_xml
, sizeof(target_xml
), "\"/>");
1479 pstrcat(target_xml
, sizeof(target_xml
), "</target>");
1483 for (i
= 0; ; i
++) {
1484 name
= xml_builtin
[i
][0];
1485 if (!name
|| (strncmp(name
, p
, len
) == 0 && strlen(name
) == len
))
1488 return name
? xml_builtin
[i
][1] : NULL
;
1492 static int gdb_read_register(CPUState
*env
, uint8_t *mem_buf
, int reg
)
1494 GDBRegisterState
*r
;
1496 if (reg
< NUM_CORE_REGS
)
1497 return cpu_gdb_read_register(env
, mem_buf
, reg
);
1499 for (r
= env
->gdb_regs
; r
; r
= r
->next
) {
1500 if (r
->base_reg
<= reg
&& reg
< r
->base_reg
+ r
->num_regs
) {
1501 return r
->get_reg(env
, mem_buf
, reg
- r
->base_reg
);
1507 static int gdb_write_register(CPUState
*env
, uint8_t *mem_buf
, int reg
)
1509 GDBRegisterState
*r
;
1511 if (reg
< NUM_CORE_REGS
)
1512 return cpu_gdb_write_register(env
, mem_buf
, reg
);
1514 for (r
= env
->gdb_regs
; r
; r
= r
->next
) {
1515 if (r
->base_reg
<= reg
&& reg
< r
->base_reg
+ r
->num_regs
) {
1516 return r
->set_reg(env
, mem_buf
, reg
- r
->base_reg
);
1522 /* Register a supplemental set of CPU registers. If g_pos is nonzero it
1523 specifies the first register number and these registers are included in
1524 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1525 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1528 void gdb_register_coprocessor(CPUState
* env
,
1529 gdb_reg_cb get_reg
, gdb_reg_cb set_reg
,
1530 int num_regs
, const char *xml
, int g_pos
)
1532 GDBRegisterState
*s
;
1533 GDBRegisterState
**p
;
1534 static int last_reg
= NUM_CORE_REGS
;
1536 s
= (GDBRegisterState
*)qemu_mallocz(sizeof(GDBRegisterState
));
1537 s
->base_reg
= last_reg
;
1538 s
->num_regs
= num_regs
;
1539 s
->get_reg
= get_reg
;
1540 s
->set_reg
= set_reg
;
1544 /* Check for duplicates. */
1545 if (strcmp((*p
)->xml
, xml
) == 0)
1549 /* Add to end of list. */
1550 last_reg
+= num_regs
;
1553 if (g_pos
!= s
->base_reg
) {
1554 fprintf(stderr
, "Error: Bad gdb register numbering for '%s'\n"
1555 "Expected %d got %d\n", xml
, g_pos
, s
->base_reg
);
1557 num_g_regs
= last_reg
;
1562 #ifndef CONFIG_USER_ONLY
1563 static const int xlat_gdb_type
[] = {
1564 [GDB_WATCHPOINT_WRITE
] = BP_GDB
| BP_MEM_WRITE
,
1565 [GDB_WATCHPOINT_READ
] = BP_GDB
| BP_MEM_READ
,
1566 [GDB_WATCHPOINT_ACCESS
] = BP_GDB
| BP_MEM_ACCESS
,
1570 static int gdb_breakpoint_insert(target_ulong addr
, target_ulong len
, int type
)
1576 return kvm_insert_breakpoint(gdbserver_state
->c_cpu
, addr
, len
, type
);
1579 case GDB_BREAKPOINT_SW
:
1580 case GDB_BREAKPOINT_HW
:
1581 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1582 err
= cpu_breakpoint_insert(env
, addr
, BP_GDB
, NULL
);
1587 #ifndef CONFIG_USER_ONLY
1588 case GDB_WATCHPOINT_WRITE
:
1589 case GDB_WATCHPOINT_READ
:
1590 case GDB_WATCHPOINT_ACCESS
:
1591 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1592 err
= cpu_watchpoint_insert(env
, addr
, len
, xlat_gdb_type
[type
],
1604 static int gdb_breakpoint_remove(target_ulong addr
, target_ulong len
, int type
)
1610 return kvm_remove_breakpoint(gdbserver_state
->c_cpu
, addr
, len
, type
);
1613 case GDB_BREAKPOINT_SW
:
1614 case GDB_BREAKPOINT_HW
:
1615 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1616 err
= cpu_breakpoint_remove(env
, addr
, BP_GDB
);
1621 #ifndef CONFIG_USER_ONLY
1622 case GDB_WATCHPOINT_WRITE
:
1623 case GDB_WATCHPOINT_READ
:
1624 case GDB_WATCHPOINT_ACCESS
:
1625 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1626 err
= cpu_watchpoint_remove(env
, addr
, len
, xlat_gdb_type
[type
]);
1637 static void gdb_breakpoint_remove_all(void)
1641 if (kvm_enabled()) {
1642 kvm_remove_all_breakpoints(gdbserver_state
->c_cpu
);
1646 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1647 cpu_breakpoint_remove_all(env
, BP_GDB
);
1648 #ifndef CONFIG_USER_ONLY
1649 cpu_watchpoint_remove_all(env
, BP_GDB
);
1654 static void gdb_set_cpu_pc(GDBState
*s
, target_ulong pc
)
1656 #if defined(TARGET_I386)
1657 cpu_synchronize_state(s
->c_cpu
);
1659 #elif defined (TARGET_PPC)
1661 #elif defined (TARGET_SPARC)
1663 s
->c_cpu
->npc
= pc
+ 4;
1664 #elif defined (TARGET_ARM)
1665 s
->c_cpu
->regs
[15] = pc
;
1666 #elif defined (TARGET_SH4)
1668 #elif defined (TARGET_MIPS)
1669 s
->c_cpu
->active_tc
.PC
= pc
& ~(target_ulong
)1;
1671 s
->c_cpu
->hflags
|= MIPS_HFLAG_M16
;
1673 s
->c_cpu
->hflags
&= ~(MIPS_HFLAG_M16
);
1675 #elif defined (TARGET_MICROBLAZE)
1676 s
->c_cpu
->sregs
[SR_PC
] = pc
;
1677 #elif defined (TARGET_CRIS)
1679 #elif defined (TARGET_ALPHA)
1681 #elif defined (TARGET_S390X)
1682 cpu_synchronize_state(s
->c_cpu
);
1683 s
->c_cpu
->psw
.addr
= pc
;
1687 static inline int gdb_id(CPUState
*env
)
1689 #if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1690 return env
->host_tid
;
1692 return env
->cpu_index
+ 1;
1696 static CPUState
*find_cpu(uint32_t thread_id
)
1700 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
1701 if (gdb_id(env
) == thread_id
) {
1709 static int gdb_handle_packet(GDBState
*s
, const char *line_buf
)
1714 int ch
, reg_size
, type
, res
;
1715 char buf
[MAX_PACKET_LENGTH
];
1716 uint8_t mem_buf
[MAX_PACKET_LENGTH
];
1718 target_ulong addr
, len
;
1721 printf("command='%s'\n", line_buf
);
1727 /* TODO: Make this return the correct value for user-mode. */
1728 snprintf(buf
, sizeof(buf
), "T%02xthread:%02x;", GDB_SIGNAL_TRAP
,
1731 /* Remove all the breakpoints when this query is issued,
1732 * because gdb is doing and initial connect and the state
1733 * should be cleaned up.
1735 gdb_breakpoint_remove_all();
1739 addr
= strtoull(p
, (char **)&p
, 16);
1740 gdb_set_cpu_pc(s
, addr
);
1746 s
->signal
= gdb_signal_to_target (strtoul(p
, (char **)&p
, 16));
1747 if (s
->signal
== -1)
1752 if (strncmp(p
, "Cont", 4) == 0) {
1753 int res_signal
, res_thread
;
1757 put_packet(s
, "vCont;c;C;s;S");
1772 if (action
== 'C' || action
== 'S') {
1773 signal
= strtoul(p
, (char **)&p
, 16);
1774 } else if (action
!= 'c' && action
!= 's') {
1780 thread
= strtoull(p
+1, (char **)&p
, 16);
1782 action
= tolower(action
);
1783 if (res
== 0 || (res
== 'c' && action
== 's')) {
1785 res_signal
= signal
;
1786 res_thread
= thread
;
1790 if (res_thread
!= -1 && res_thread
!= 0) {
1791 env
= find_cpu(res_thread
);
1793 put_packet(s
, "E22");
1799 cpu_single_step(s
->c_cpu
, sstep_flags
);
1801 s
->signal
= res_signal
;
1807 goto unknown_command
;
1810 /* Kill the target */
1811 fprintf(stderr
, "\nQEMU: Terminated via GDBstub\n");
1815 gdb_breakpoint_remove_all();
1817 put_packet(s
, "OK");
1821 addr
= strtoull(p
, (char **)&p
, 16);
1822 gdb_set_cpu_pc(s
, addr
);
1824 cpu_single_step(s
->c_cpu
, sstep_flags
);
1832 ret
= strtoull(p
, (char **)&p
, 16);
1835 err
= strtoull(p
, (char **)&p
, 16);
1842 if (gdb_current_syscall_cb
)
1843 gdb_current_syscall_cb(s
->c_cpu
, ret
, err
);
1845 put_packet(s
, "T02");
1852 cpu_synchronize_state(s
->g_cpu
);
1854 for (addr
= 0; addr
< num_g_regs
; addr
++) {
1855 reg_size
= gdb_read_register(s
->g_cpu
, mem_buf
+ len
, addr
);
1858 memtohex(buf
, mem_buf
, len
);
1862 cpu_synchronize_state(s
->g_cpu
);
1863 registers
= mem_buf
;
1864 len
= strlen(p
) / 2;
1865 hextomem((uint8_t *)registers
, p
, len
);
1866 for (addr
= 0; addr
< num_g_regs
&& len
> 0; addr
++) {
1867 reg_size
= gdb_write_register(s
->g_cpu
, registers
, addr
);
1869 registers
+= reg_size
;
1871 put_packet(s
, "OK");
1874 addr
= strtoull(p
, (char **)&p
, 16);
1877 len
= strtoull(p
, NULL
, 16);
1878 if (cpu_memory_rw_debug(s
->g_cpu
, addr
, mem_buf
, len
, 0) != 0) {
1879 put_packet (s
, "E14");
1881 memtohex(buf
, mem_buf
, len
);
1886 addr
= strtoull(p
, (char **)&p
, 16);
1889 len
= strtoull(p
, (char **)&p
, 16);
1892 hextomem(mem_buf
, p
, len
);
1893 if (cpu_memory_rw_debug(s
->g_cpu
, addr
, mem_buf
, len
, 1) != 0)
1894 put_packet(s
, "E14");
1896 put_packet(s
, "OK");
1899 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1900 This works, but can be very slow. Anything new enough to
1901 understand XML also knows how to use this properly. */
1903 goto unknown_command
;
1904 addr
= strtoull(p
, (char **)&p
, 16);
1905 reg_size
= gdb_read_register(s
->g_cpu
, mem_buf
, addr
);
1907 memtohex(buf
, mem_buf
, reg_size
);
1910 put_packet(s
, "E14");
1915 goto unknown_command
;
1916 addr
= strtoull(p
, (char **)&p
, 16);
1919 reg_size
= strlen(p
) / 2;
1920 hextomem(mem_buf
, p
, reg_size
);
1921 gdb_write_register(s
->g_cpu
, mem_buf
, addr
);
1922 put_packet(s
, "OK");
1926 type
= strtoul(p
, (char **)&p
, 16);
1929 addr
= strtoull(p
, (char **)&p
, 16);
1932 len
= strtoull(p
, (char **)&p
, 16);
1934 res
= gdb_breakpoint_insert(addr
, len
, type
);
1936 res
= gdb_breakpoint_remove(addr
, len
, type
);
1938 put_packet(s
, "OK");
1939 else if (res
== -ENOSYS
)
1942 put_packet(s
, "E22");
1946 thread
= strtoull(p
, (char **)&p
, 16);
1947 if (thread
== -1 || thread
== 0) {
1948 put_packet(s
, "OK");
1951 env
= find_cpu(thread
);
1953 put_packet(s
, "E22");
1959 put_packet(s
, "OK");
1963 put_packet(s
, "OK");
1966 put_packet(s
, "E22");
1971 thread
= strtoull(p
, (char **)&p
, 16);
1972 env
= find_cpu(thread
);
1975 put_packet(s
, "OK");
1977 put_packet(s
, "E22");
1982 /* parse any 'q' packets here */
1983 if (!strcmp(p
,"qemu.sstepbits")) {
1984 /* Query Breakpoint bit definitions */
1985 snprintf(buf
, sizeof(buf
), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1991 } else if (strncmp(p
,"qemu.sstep",10) == 0) {
1992 /* Display or change the sstep_flags */
1995 /* Display current setting */
1996 snprintf(buf
, sizeof(buf
), "0x%x", sstep_flags
);
2001 type
= strtoul(p
, (char **)&p
, 16);
2003 put_packet(s
, "OK");
2005 } else if (strcmp(p
,"C") == 0) {
2006 /* "Current thread" remains vague in the spec, so always return
2007 * the first CPU (gdb returns the first thread). */
2008 put_packet(s
, "QC1");
2010 } else if (strcmp(p
,"fThreadInfo") == 0) {
2011 s
->query_cpu
= first_cpu
;
2012 goto report_cpuinfo
;
2013 } else if (strcmp(p
,"sThreadInfo") == 0) {
2016 snprintf(buf
, sizeof(buf
), "m%x", gdb_id(s
->query_cpu
));
2018 s
->query_cpu
= s
->query_cpu
->next_cpu
;
2022 } else if (strncmp(p
,"ThreadExtraInfo,", 16) == 0) {
2023 thread
= strtoull(p
+16, (char **)&p
, 16);
2024 env
= find_cpu(thread
);
2026 cpu_synchronize_state(env
);
2027 len
= snprintf((char *)mem_buf
, sizeof(mem_buf
),
2028 "CPU#%d [%s]", env
->cpu_index
,
2029 env
->halted
? "halted " : "running");
2030 memtohex(buf
, mem_buf
, len
);
2035 #ifdef CONFIG_USER_ONLY
2036 else if (strncmp(p
, "Offsets", 7) == 0) {
2037 TaskState
*ts
= s
->c_cpu
->opaque
;
2039 snprintf(buf
, sizeof(buf
),
2040 "Text=" TARGET_ABI_FMT_lx
";Data=" TARGET_ABI_FMT_lx
2041 ";Bss=" TARGET_ABI_FMT_lx
,
2042 ts
->info
->code_offset
,
2043 ts
->info
->data_offset
,
2044 ts
->info
->data_offset
);
2048 #else /* !CONFIG_USER_ONLY */
2049 else if (strncmp(p
, "Rcmd,", 5) == 0) {
2050 int len
= strlen(p
+ 5);
2052 if ((len
% 2) != 0) {
2053 put_packet(s
, "E01");
2056 hextomem(mem_buf
, p
+ 5, len
);
2059 qemu_chr_read(s
->mon_chr
, mem_buf
, len
);
2060 put_packet(s
, "OK");
2063 #endif /* !CONFIG_USER_ONLY */
2064 if (strncmp(p
, "Supported", 9) == 0) {
2065 snprintf(buf
, sizeof(buf
), "PacketSize=%x", MAX_PACKET_LENGTH
);
2067 pstrcat(buf
, sizeof(buf
), ";qXfer:features:read+");
2073 if (strncmp(p
, "Xfer:features:read:", 19) == 0) {
2075 target_ulong total_len
;
2079 xml
= get_feature_xml(p
, &p
);
2081 snprintf(buf
, sizeof(buf
), "E00");
2088 addr
= strtoul(p
, (char **)&p
, 16);
2091 len
= strtoul(p
, (char **)&p
, 16);
2093 total_len
= strlen(xml
);
2094 if (addr
> total_len
) {
2095 snprintf(buf
, sizeof(buf
), "E00");
2099 if (len
> (MAX_PACKET_LENGTH
- 5) / 2)
2100 len
= (MAX_PACKET_LENGTH
- 5) / 2;
2101 if (len
< total_len
- addr
) {
2103 len
= memtox(buf
+ 1, xml
+ addr
, len
);
2106 len
= memtox(buf
+ 1, xml
+ addr
, total_len
- addr
);
2108 put_packet_binary(s
, buf
, len
+ 1);
2112 /* Unrecognised 'q' command. */
2113 goto unknown_command
;
2117 /* put empty packet */
2125 void gdb_set_stop_cpu(CPUState
*env
)
2127 gdbserver_state
->c_cpu
= env
;
2128 gdbserver_state
->g_cpu
= env
;
2131 #ifndef CONFIG_USER_ONLY
2132 static void gdb_vm_state_change(void *opaque
, int running
, int reason
)
2134 GDBState
*s
= gdbserver_state
;
2135 CPUState
*env
= s
->c_cpu
;
2140 if (running
|| (reason
!= EXCP_DEBUG
&& reason
!= EXCP_INTERRUPT
) ||
2141 s
->state
== RS_INACTIVE
|| s
->state
== RS_SYSCALL
)
2144 /* disable single step if it was enable */
2145 cpu_single_step(env
, 0);
2147 if (reason
== EXCP_DEBUG
) {
2148 if (env
->watchpoint_hit
) {
2149 switch (env
->watchpoint_hit
->flags
& BP_MEM_ACCESS
) {
2160 snprintf(buf
, sizeof(buf
),
2161 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx
";",
2162 GDB_SIGNAL_TRAP
, gdb_id(env
), type
,
2163 env
->watchpoint_hit
->vaddr
);
2165 env
->watchpoint_hit
= NULL
;
2169 ret
= GDB_SIGNAL_TRAP
;
2171 ret
= GDB_SIGNAL_INT
;
2173 snprintf(buf
, sizeof(buf
), "T%02xthread:%02x;", ret
, gdb_id(env
));
2178 /* Send a gdb syscall request.
2179 This accepts limited printf-style format specifiers, specifically:
2180 %x - target_ulong argument printed in hex.
2181 %lx - 64-bit argument printed in hex.
2182 %s - string pointer (target_ulong) and length (int) pair. */
2183 void gdb_do_syscall(gdb_syscall_complete_cb cb
, const char *fmt
, ...)
2192 s
= gdbserver_state
;
2195 gdb_current_syscall_cb
= cb
;
2196 s
->state
= RS_SYSCALL
;
2197 #ifndef CONFIG_USER_ONLY
2198 vm_stop(EXCP_DEBUG
);
2209 addr
= va_arg(va
, target_ulong
);
2210 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, TARGET_FMT_lx
, addr
);
2213 if (*(fmt
++) != 'x')
2215 i64
= va_arg(va
, uint64_t);
2216 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, "%" PRIx64
, i64
);
2219 addr
= va_arg(va
, target_ulong
);
2220 p
+= snprintf(p
, &buf
[sizeof(buf
)] - p
, TARGET_FMT_lx
"/%x",
2221 addr
, va_arg(va
, int));
2225 fprintf(stderr
, "gdbstub: Bad syscall format string '%s'\n",
2236 #ifdef CONFIG_USER_ONLY
2237 gdb_handlesig(s
->c_cpu
, 0);
2243 static void gdb_read_byte(GDBState
*s
, int ch
)
2248 #ifndef CONFIG_USER_ONLY
2249 if (s
->last_packet_len
) {
2250 /* Waiting for a response to the last packet. If we see the start
2251 of a new command then abandon the previous response. */
2254 printf("Got NACK, retransmitting\n");
2256 put_buffer(s
, (uint8_t *)s
->last_packet
, s
->last_packet_len
);
2260 printf("Got ACK\n");
2262 printf("Got '%c' when expecting ACK/NACK\n", ch
);
2264 if (ch
== '+' || ch
== '$')
2265 s
->last_packet_len
= 0;
2270 /* when the CPU is running, we cannot do anything except stop
2271 it when receiving a char */
2272 vm_stop(EXCP_INTERRUPT
);
2279 s
->line_buf_index
= 0;
2280 s
->state
= RS_GETLINE
;
2285 s
->state
= RS_CHKSUM1
;
2286 } else if (s
->line_buf_index
>= sizeof(s
->line_buf
) - 1) {
2289 s
->line_buf
[s
->line_buf_index
++] = ch
;
2293 s
->line_buf
[s
->line_buf_index
] = '\0';
2294 s
->line_csum
= fromhex(ch
) << 4;
2295 s
->state
= RS_CHKSUM2
;
2298 s
->line_csum
|= fromhex(ch
);
2300 for(i
= 0; i
< s
->line_buf_index
; i
++) {
2301 csum
+= s
->line_buf
[i
];
2303 if (s
->line_csum
!= (csum
& 0xff)) {
2305 put_buffer(s
, &reply
, 1);
2309 put_buffer(s
, &reply
, 1);
2310 s
->state
= gdb_handle_packet(s
, s
->line_buf
);
2319 #ifdef CONFIG_USER_ONLY
2325 s
= gdbserver_state
;
2327 if (gdbserver_fd
< 0 || s
->fd
< 0)
2334 gdb_handlesig (CPUState
*env
, int sig
)
2340 s
= gdbserver_state
;
2341 if (gdbserver_fd
< 0 || s
->fd
< 0)
2344 /* disable single step if it was enabled */
2345 cpu_single_step(env
, 0);
2350 snprintf(buf
, sizeof(buf
), "S%02x", target_signal_to_gdb (sig
));
2353 /* put_packet() might have detected that the peer terminated the
2360 s
->running_state
= 0;
2361 while (s
->running_state
== 0) {
2362 n
= read (s
->fd
, buf
, 256);
2367 for (i
= 0; i
< n
; i
++)
2368 gdb_read_byte (s
, buf
[i
]);
2370 else if (n
== 0 || errno
!= EAGAIN
)
2372 /* XXX: Connection closed. Should probably wait for annother
2373 connection before continuing. */
2382 /* Tell the remote gdb that the process has exited. */
2383 void gdb_exit(CPUState
*env
, int code
)
2388 s
= gdbserver_state
;
2389 if (gdbserver_fd
< 0 || s
->fd
< 0)
2392 snprintf(buf
, sizeof(buf
), "W%02x", code
);
2396 /* Tell the remote gdb that the process has exited due to SIG. */
2397 void gdb_signalled(CPUState
*env
, int sig
)
2402 s
= gdbserver_state
;
2403 if (gdbserver_fd
< 0 || s
->fd
< 0)
2406 snprintf(buf
, sizeof(buf
), "X%02x", target_signal_to_gdb (sig
));
2410 static void gdb_accept(void)
2413 struct sockaddr_in sockaddr
;
2418 len
= sizeof(sockaddr
);
2419 fd
= accept(gdbserver_fd
, (struct sockaddr
*)&sockaddr
, &len
);
2420 if (fd
< 0 && errno
!= EINTR
) {
2423 } else if (fd
>= 0) {
2425 fcntl(fd
, F_SETFD
, FD_CLOEXEC
);
2431 /* set short latency */
2433 setsockopt(fd
, IPPROTO_TCP
, TCP_NODELAY
, (char *)&val
, sizeof(val
));
2435 s
= qemu_mallocz(sizeof(GDBState
));
2436 s
->c_cpu
= first_cpu
;
2437 s
->g_cpu
= first_cpu
;
2441 gdbserver_state
= s
;
2443 fcntl(fd
, F_SETFL
, O_NONBLOCK
);
2446 static int gdbserver_open(int port
)
2448 struct sockaddr_in sockaddr
;
2451 fd
= socket(PF_INET
, SOCK_STREAM
, 0);
2457 fcntl(fd
, F_SETFD
, FD_CLOEXEC
);
2460 /* allow fast reuse */
2462 setsockopt(fd
, SOL_SOCKET
, SO_REUSEADDR
, (char *)&val
, sizeof(val
));
2464 sockaddr
.sin_family
= AF_INET
;
2465 sockaddr
.sin_port
= htons(port
);
2466 sockaddr
.sin_addr
.s_addr
= 0;
2467 ret
= bind(fd
, (struct sockaddr
*)&sockaddr
, sizeof(sockaddr
));
2472 ret
= listen(fd
, 0);
2480 int gdbserver_start(int port
)
2482 gdbserver_fd
= gdbserver_open(port
);
2483 if (gdbserver_fd
< 0)
2485 /* accept connections */
2490 /* Disable gdb stub for child processes. */
2491 void gdbserver_fork(CPUState
*env
)
2493 GDBState
*s
= gdbserver_state
;
2494 if (gdbserver_fd
< 0 || s
->fd
< 0)
2498 cpu_breakpoint_remove_all(env
, BP_GDB
);
2499 cpu_watchpoint_remove_all(env
, BP_GDB
);
2502 static int gdb_chr_can_receive(void *opaque
)
2504 /* We can handle an arbitrarily large amount of data.
2505 Pick the maximum packet size, which is as good as anything. */
2506 return MAX_PACKET_LENGTH
;
2509 static void gdb_chr_receive(void *opaque
, const uint8_t *buf
, int size
)
2513 for (i
= 0; i
< size
; i
++) {
2514 gdb_read_byte(gdbserver_state
, buf
[i
]);
2518 static void gdb_chr_event(void *opaque
, int event
)
2521 case CHR_EVENT_OPENED
:
2522 vm_stop(EXCP_INTERRUPT
);
2530 static void gdb_monitor_output(GDBState
*s
, const char *msg
, int len
)
2532 char buf
[MAX_PACKET_LENGTH
];
2535 if (len
> (MAX_PACKET_LENGTH
/2) - 1)
2536 len
= (MAX_PACKET_LENGTH
/2) - 1;
2537 memtohex(buf
+ 1, (uint8_t *)msg
, len
);
2541 static int gdb_monitor_write(CharDriverState
*chr
, const uint8_t *buf
, int len
)
2543 const char *p
= (const char *)buf
;
2546 max_sz
= (sizeof(gdbserver_state
->last_packet
) - 2) / 2;
2548 if (len
<= max_sz
) {
2549 gdb_monitor_output(gdbserver_state
, p
, len
);
2552 gdb_monitor_output(gdbserver_state
, p
, max_sz
);
2560 static void gdb_sigterm_handler(int signal
)
2563 vm_stop(EXCP_INTERRUPT
);
2567 int gdbserver_start(const char *device
)
2570 char gdbstub_device_name
[128];
2571 CharDriverState
*chr
= NULL
;
2572 CharDriverState
*mon_chr
;
2576 if (strcmp(device
, "none") != 0) {
2577 if (strstart(device
, "tcp:", NULL
)) {
2578 /* enforce required TCP attributes */
2579 snprintf(gdbstub_device_name
, sizeof(gdbstub_device_name
),
2580 "%s,nowait,nodelay,server", device
);
2581 device
= gdbstub_device_name
;
2584 else if (strcmp(device
, "stdio") == 0) {
2585 struct sigaction act
;
2587 memset(&act
, 0, sizeof(act
));
2588 act
.sa_handler
= gdb_sigterm_handler
;
2589 sigaction(SIGINT
, &act
, NULL
);
2592 chr
= qemu_chr_open("gdb", device
, NULL
);
2596 qemu_chr_add_handlers(chr
, gdb_chr_can_receive
, gdb_chr_receive
,
2597 gdb_chr_event
, NULL
);
2600 s
= gdbserver_state
;
2602 s
= qemu_mallocz(sizeof(GDBState
));
2603 gdbserver_state
= s
;
2605 qemu_add_vm_change_state_handler(gdb_vm_state_change
, NULL
);
2607 /* Initialize a monitor terminal for gdb */
2608 mon_chr
= qemu_mallocz(sizeof(*mon_chr
));
2609 mon_chr
->chr_write
= gdb_monitor_write
;
2610 monitor_init(mon_chr
, 0);
2613 qemu_chr_close(s
->chr
);
2614 mon_chr
= s
->mon_chr
;
2615 memset(s
, 0, sizeof(GDBState
));
2617 s
->c_cpu
= first_cpu
;
2618 s
->g_cpu
= first_cpu
;
2620 s
->state
= chr
? RS_IDLE
: RS_INACTIVE
;
2621 s
->mon_chr
= mon_chr
;