4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "device-assignment.h"
33 #include "qemu-objects.h"
38 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
40 # define PCI_DPRINTF(format, ...) do { } while (0)
46 pci_set_irq_fn set_irq
;
47 pci_map_irq_fn map_irq
;
48 pci_hotplug_fn hotplug
;
49 DeviceState
*hotplug_qdev
;
51 PCIDevice
*devices
[256];
52 PCIDevice
*parent_dev
;
53 target_phys_addr_t mem_base
;
55 QLIST_HEAD(, PCIBus
) child
; /* this will be replaced by qdev later */
56 QLIST_ENTRY(PCIBus
) sibling
;/* this will be replaced by qdev later */
58 /* The bus IRQ state is the logical OR of the connected devices.
59 Keep a count of the number of devices with raised IRQs. */
64 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
65 static char *pcibus_get_dev_path(DeviceState
*dev
);
67 static struct BusInfo pci_bus_info
= {
69 .size
= sizeof(PCIBus
),
70 .print_dev
= pcibus_dev_print
,
71 .get_dev_path
= pcibus_get_dev_path
,
72 .props
= (Property
[]) {
73 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
74 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
75 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
76 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
77 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
78 DEFINE_PROP_END_OF_LIST()
82 static void pci_update_mappings(PCIDevice
*d
);
83 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
84 static int pci_add_option_rom(PCIDevice
*pdev
);
85 static void pci_del_option_rom(PCIDevice
*pdev
);
87 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
88 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
93 QLIST_ENTRY(PCIHostBus
) next
;
95 static QLIST_HEAD(, PCIHostBus
) host_buses
;
97 static const VMStateDescription vmstate_pcibus
= {
100 .minimum_version_id
= 1,
101 .minimum_version_id_old
= 1,
102 .fields
= (VMStateField
[]) {
103 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
104 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
105 VMSTATE_END_OF_LIST()
109 static int pci_bar(PCIDevice
*d
, int reg
)
113 if (reg
!= PCI_ROM_SLOT
)
114 return PCI_BASE_ADDRESS_0
+ reg
* 4;
116 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
117 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
120 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
122 return (d
->irq_state
>> irq_num
) & 0x1;
125 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
127 d
->irq_state
&= ~(0x1 << irq_num
);
128 d
->irq_state
|= level
<< irq_num
;
131 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
136 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
139 pci_dev
= bus
->parent_dev
;
141 bus
->irq_count
[irq_num
] += change
;
142 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
145 /* Update interrupt status bit in config space on interrupt
147 static void pci_update_irq_status(PCIDevice
*dev
)
149 if (dev
->irq_state
) {
150 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
152 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
156 static void pci_device_reset(PCIDevice
*dev
)
161 pci_update_irq_status(dev
);
162 /* Clear all writeable bits */
163 pci_set_word(dev
->config
+ PCI_COMMAND
,
164 pci_get_word(dev
->config
+ PCI_COMMAND
) &
165 ~pci_get_word(dev
->wmask
+ PCI_COMMAND
));
166 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
167 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
168 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
169 PCIIORegion
*region
= &dev
->io_regions
[r
];
174 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
175 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
176 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
178 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
181 pci_update_mappings(dev
);
184 static void pci_bus_reset(void *opaque
)
186 PCIBus
*bus
= opaque
;
189 for (i
= 0; i
< bus
->nirq
; i
++) {
190 bus
->irq_count
[i
] = 0;
192 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
193 if (bus
->devices
[i
]) {
194 pci_device_reset(bus
->devices
[i
]);
199 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
201 struct PCIHostBus
*host
;
202 host
= qemu_mallocz(sizeof(*host
));
203 host
->domain
= domain
;
205 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
208 PCIBus
*pci_find_root_bus(int domain
)
210 struct PCIHostBus
*host
;
212 QLIST_FOREACH(host
, &host_buses
, next
) {
213 if (host
->domain
== domain
) {
221 int pci_find_domain(const PCIBus
*bus
)
224 struct PCIHostBus
*host
;
226 /* obtain root bus */
227 while ((d
= bus
->parent_dev
) != NULL
) {
231 QLIST_FOREACH(host
, &host_buses
, next
) {
232 if (host
->bus
== bus
) {
237 abort(); /* should not be reached */
241 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
242 const char *name
, int devfn_min
)
244 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
245 assert(PCI_FUNC(devfn_min
) == 0);
246 bus
->devfn_min
= devfn_min
;
249 QLIST_INIT(&bus
->child
);
250 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
252 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
253 qemu_register_reset(pci_bus_reset
, bus
);
256 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
260 bus
= qemu_mallocz(sizeof(*bus
));
261 bus
->qbus
.qdev_allocated
= 1;
262 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
266 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
267 void *irq_opaque
, int nirq
)
269 bus
->set_irq
= set_irq
;
270 bus
->map_irq
= map_irq
;
271 bus
->irq_opaque
= irq_opaque
;
273 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
276 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
278 bus
->qbus
.allow_hotplug
= 1;
279 bus
->hotplug
= hotplug
;
280 bus
->hotplug_qdev
= qdev
;
283 void pci_bus_set_mem_base(PCIBus
*bus
, target_phys_addr_t base
)
285 bus
->mem_base
= base
;
288 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
289 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
290 void *irq_opaque
, int devfn_min
, int nirq
)
294 bus
= pci_bus_new(parent
, name
, devfn_min
);
295 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
299 static void pci_register_secondary_bus(PCIBus
*parent
,
302 pci_map_irq_fn map_irq
,
305 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
306 bus
->map_irq
= map_irq
;
307 bus
->parent_dev
= dev
;
309 QLIST_INIT(&bus
->child
);
310 QLIST_INSERT_HEAD(&parent
->child
, bus
, sibling
);
313 static void pci_unregister_secondary_bus(PCIBus
*bus
)
315 assert(QLIST_EMPTY(&bus
->child
));
316 QLIST_REMOVE(bus
, sibling
);
319 int pci_bus_num(PCIBus
*s
)
322 return 0; /* pci host bridge */
323 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
326 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
328 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
332 assert(size
== pci_config_size(s
));
333 config
= qemu_malloc(size
);
335 qemu_get_buffer(f
, config
, size
);
336 for (i
= 0; i
< size
; ++i
) {
337 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
]) {
342 memcpy(s
->config
, config
, size
);
344 pci_update_mappings(s
);
350 /* just put buffer */
351 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
353 const uint8_t **v
= pv
;
354 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
355 qemu_put_buffer(f
, *v
, size
);
358 static VMStateInfo vmstate_info_pci_config
= {
359 .name
= "pci config",
360 .get
= get_pci_config_device
,
361 .put
= put_pci_config_device
,
364 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
366 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
367 uint32_t irq_state
[PCI_NUM_PINS
];
369 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
370 irq_state
[i
] = qemu_get_be32(f
);
371 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
372 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
378 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
379 pci_set_irq_state(s
, i
, irq_state
[i
]);
385 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
388 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
390 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
391 qemu_put_be32(f
, pci_irq_state(s
, i
));
395 static VMStateInfo vmstate_info_pci_irq_state
= {
396 .name
= "pci irq state",
397 .get
= get_pci_irq_state
,
398 .put
= put_pci_irq_state
,
401 const VMStateDescription vmstate_pci_device
= {
404 .minimum_version_id
= 1,
405 .minimum_version_id_old
= 1,
406 .fields
= (VMStateField
[]) {
407 VMSTATE_INT32_LE(version_id
, PCIDevice
),
408 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
409 vmstate_info_pci_config
,
410 PCI_CONFIG_SPACE_SIZE
),
411 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
412 vmstate_info_pci_irq_state
,
413 PCI_NUM_PINS
* sizeof(int32_t)),
414 VMSTATE_END_OF_LIST()
418 const VMStateDescription vmstate_pcie_device
= {
421 .minimum_version_id
= 1,
422 .minimum_version_id_old
= 1,
423 .fields
= (VMStateField
[]) {
424 VMSTATE_INT32_LE(version_id
, PCIDevice
),
425 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
426 vmstate_info_pci_config
,
427 PCIE_CONFIG_SPACE_SIZE
),
428 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
429 vmstate_info_pci_irq_state
,
430 PCI_NUM_PINS
* sizeof(int32_t)),
431 VMSTATE_END_OF_LIST()
435 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
437 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
440 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
442 /* Clear interrupt status bit: it is implicit
443 * in irq_state which we are saving.
444 * This makes us compatible with old devices
445 * which never set or clear this bit. */
446 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
447 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
448 /* Restore the interrupt status bit. */
449 pci_update_irq_status(s
);
452 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
455 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
456 /* Restore the interrupt status bit. */
457 pci_update_irq_status(s
);
461 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
463 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
464 pci_default_sub_vendor_id
);
465 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
466 pci_default_sub_device_id
);
470 * Parse pci address in qemu command
471 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
473 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
478 unsigned long dom
= 0, bus
= 0;
482 val
= strtoul(p
, &e
, 16);
488 val
= strtoul(p
, &e
, 16);
495 val
= strtoul(p
, &e
, 16);
501 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
509 /* Note: QEMU doesn't implement domains other than 0 */
510 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
520 * Parse device seg and bdf in device assignment command:
522 * -pcidevice host=[seg:]bus:dev.func
524 * Parse [seg:]<bus>:<slot>.<func> return -1 on error
526 int pci_parse_host_devaddr(const char *addr
, int *segp
, int *busp
,
527 int *slotp
, int *funcp
)
532 int seg
= 0, bus
= 0, slot
= 0, func
= 0;
534 /* parse optional seg */
545 if (val
<= 0 || val
> 2)
550 val
= strtoul(p
, &e
, 16);
562 val
= strtoul(p
, &e
, 16);
568 val
= strtoul(p
, &e
, 16);
574 val
= strtoul(p
, &e
, 16);
583 if (seg
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 0x7)
596 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
599 /* strip legacy tag */
600 if (!strncmp(addr
, "pci_addr=", 9)) {
603 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
604 monitor_printf(mon
, "Invalid pci address\n");
610 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
617 return pci_find_bus(pci_find_root_bus(0), 0);
620 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
625 return pci_find_bus(pci_find_root_bus(dom
), bus
);
628 static void pci_init_cmask(PCIDevice
*dev
)
630 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
631 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
632 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
633 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
634 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
635 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
636 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
637 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
640 static void pci_init_wmask(PCIDevice
*dev
)
642 int config_size
= pci_config_size(dev
);
644 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
645 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
646 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
647 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
648 PCI_COMMAND_INTX_DISABLE
);
650 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
651 config_size
- PCI_CONFIG_HEADER_SIZE
);
654 static void pci_init_wmask_bridge(PCIDevice
*d
)
656 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
657 PCI_SEC_LETENCY_TIMER */
658 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
661 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
662 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
663 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
664 PCI_MEMORY_RANGE_MASK
& 0xffff);
665 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
666 PCI_MEMORY_RANGE_MASK
& 0xffff);
667 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
668 PCI_PREF_RANGE_MASK
& 0xffff);
669 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
670 PCI_PREF_RANGE_MASK
& 0xffff);
672 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
673 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
675 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
, 0xffff);
678 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
680 uint8_t slot
= PCI_SLOT(dev
->devfn
);
683 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
684 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
688 * multifuction bit is interpreted in two ways as follows.
689 * - all functions must set the bit to 1.
691 * - function 0 must set the bit, but the rest function (> 0)
692 * is allowed to leave the bit to 0.
693 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
695 * So OS (at least Linux) checks the bit of only function 0,
696 * and doesn't see the bit of function > 0.
698 * The below check allows both interpretation.
700 if (PCI_FUNC(dev
->devfn
)) {
701 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
702 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
703 /* function 0 should set multifunction bit */
704 error_report("PCI: single function device can't be populated "
705 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
711 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
714 /* function 0 indicates single function, so function > 0 must be NULL */
715 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
716 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
717 error_report("PCI: %x.0 indicates single function, "
718 "but %x.%x is already populated.",
726 static void pci_config_alloc(PCIDevice
*pci_dev
)
728 int config_size
= pci_config_size(pci_dev
);
730 pci_dev
->config
= qemu_mallocz(config_size
);
731 pci_dev
->cmask
= qemu_mallocz(config_size
);
732 pci_dev
->wmask
= qemu_mallocz(config_size
);
733 pci_dev
->used
= qemu_mallocz(config_size
);
736 static void pci_config_free(PCIDevice
*pci_dev
)
738 qemu_free(pci_dev
->config
);
739 qemu_free(pci_dev
->cmask
);
740 qemu_free(pci_dev
->wmask
);
741 qemu_free(pci_dev
->used
);
744 /* -1 for devfn means auto assign */
745 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
746 const char *name
, int devfn
,
747 PCIConfigReadFunc
*config_read
,
748 PCIConfigWriteFunc
*config_write
,
752 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
753 devfn
+= PCI_FUNC_MAX
) {
754 if (!bus
->devices
[devfn
])
757 error_report("PCI: no slot/function available for %s, all in use", name
);
760 } else if (bus
->devices
[devfn
]) {
761 error_report("PCI: slot %d function %d not available for %s, in use by %s",
762 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
766 pci_dev
->devfn
= devfn
;
767 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
768 pci_dev
->irq_state
= 0;
769 pci_config_alloc(pci_dev
);
772 pci_set_default_subsystem_id(pci_dev
);
774 pci_init_cmask(pci_dev
);
775 pci_init_wmask(pci_dev
);
777 pci_init_wmask_bridge(pci_dev
);
779 if (pci_init_multifunction(bus
, pci_dev
)) {
780 pci_config_free(pci_dev
);
785 config_read
= pci_default_read_config
;
787 config_write
= pci_default_write_config
;
788 pci_dev
->config_read
= config_read
;
789 pci_dev
->config_write
= config_write
;
790 bus
->devices
[devfn
] = pci_dev
;
791 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
792 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
796 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
798 qemu_free_irqs(pci_dev
->irq
);
799 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
800 pci_config_free(pci_dev
);
803 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
804 int instance_size
, int devfn
,
805 PCIConfigReadFunc
*config_read
,
806 PCIConfigWriteFunc
*config_write
)
810 pci_dev
= qemu_mallocz(instance_size
);
811 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
812 config_read
, config_write
,
813 PCI_HEADER_TYPE_NORMAL
);
814 if (pci_dev
== NULL
) {
815 hw_error("PCI: can't register device\n");
820 static target_phys_addr_t
pci_to_cpu_addr(PCIBus
*bus
,
821 target_phys_addr_t addr
)
823 return addr
+ bus
->mem_base
;
826 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
831 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
832 r
= &pci_dev
->io_regions
[i
];
833 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
835 if (r
->type
== PCI_BASE_ADDRESS_SPACE_IO
) {
836 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
838 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev
->bus
,
846 static int pci_unregister_device(DeviceState
*dev
)
848 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
849 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
853 ret
= info
->exit(pci_dev
);
857 pci_unregister_io_regions(pci_dev
);
858 pci_del_option_rom(pci_dev
);
859 do_pci_unregister_device(pci_dev
);
863 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
864 pcibus_t size
, int type
,
865 PCIMapIORegionFunc
*map_func
)
871 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
874 if (size
& (size
-1)) {
875 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
876 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
880 r
= &pci_dev
->io_regions
[region_num
];
881 r
->addr
= PCI_BAR_UNMAPPED
;
883 r
->filtered_size
= size
;
885 r
->map_func
= map_func
;
888 addr
= pci_bar(pci_dev
, region_num
);
889 if (region_num
== PCI_ROM_SLOT
) {
890 /* ROM enable bit is writeable */
891 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
893 pci_set_long(pci_dev
->config
+ addr
, type
);
894 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
895 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
896 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
897 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
899 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
900 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
904 static uint32_t pci_config_get_io_base(PCIDevice
*d
,
905 uint32_t base
, uint32_t base_upper16
)
909 val
= ((uint32_t)d
->config
[base
] & PCI_IO_RANGE_MASK
) << 8;
910 if (d
->config
[base
] & PCI_IO_RANGE_TYPE_32
) {
911 val
|= (uint32_t)pci_get_word(d
->config
+ base_upper16
) << 16;
916 static pcibus_t
pci_config_get_memory_base(PCIDevice
*d
, uint32_t base
)
918 return ((pcibus_t
)pci_get_word(d
->config
+ base
) & PCI_MEMORY_RANGE_MASK
)
922 static pcibus_t
pci_config_get_pref_base(PCIDevice
*d
,
923 uint32_t base
, uint32_t upper
)
928 tmp
= (pcibus_t
)pci_get_word(d
->config
+ base
);
929 val
= (tmp
& PCI_PREF_RANGE_MASK
) << 16;
930 if (tmp
& PCI_PREF_RANGE_TYPE_64
) {
931 val
|= (pcibus_t
)pci_get_long(d
->config
+ upper
) << 32;
936 static pcibus_t
pci_bridge_get_base(PCIDevice
*bridge
, uint8_t type
)
939 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
940 base
= pci_config_get_io_base(bridge
,
941 PCI_IO_BASE
, PCI_IO_BASE_UPPER16
);
943 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
944 base
= pci_config_get_pref_base(
945 bridge
, PCI_PREF_MEMORY_BASE
, PCI_PREF_BASE_UPPER32
);
947 base
= pci_config_get_memory_base(bridge
, PCI_MEMORY_BASE
);
954 static pcibus_t
pci_bridge_get_limit(PCIDevice
*bridge
, uint8_t type
)
957 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
958 limit
= pci_config_get_io_base(bridge
,
959 PCI_IO_LIMIT
, PCI_IO_LIMIT_UPPER16
);
960 limit
|= 0xfff; /* PCI bridge spec 3.2.5.6. */
962 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
963 limit
= pci_config_get_pref_base(
964 bridge
, PCI_PREF_MEMORY_LIMIT
, PCI_PREF_LIMIT_UPPER32
);
966 limit
= pci_config_get_memory_base(bridge
, PCI_MEMORY_LIMIT
);
968 limit
|= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
973 static void pci_bridge_filter(PCIDevice
*d
, pcibus_t
*addr
, pcibus_t
*size
,
976 pcibus_t base
= *addr
;
977 pcibus_t limit
= *addr
+ *size
- 1;
980 for (br
= d
->bus
->parent_dev
; br
; br
= br
->bus
->parent_dev
) {
981 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
983 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
984 if (!(cmd
& PCI_COMMAND_IO
)) {
988 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
993 base
= MAX(base
, pci_bridge_get_base(br
, type
));
994 limit
= MIN(limit
, pci_bridge_get_limit(br
, type
));
1001 *size
= limit
- base
+ 1;
1004 *addr
= PCI_BAR_UNMAPPED
;
1008 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1009 int reg
, uint8_t type
, pcibus_t size
)
1011 pcibus_t new_addr
, last_addr
;
1012 int bar
= pci_bar(d
, reg
);
1013 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1015 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1016 if (!(cmd
& PCI_COMMAND_IO
)) {
1017 return PCI_BAR_UNMAPPED
;
1019 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1020 last_addr
= new_addr
+ size
- 1;
1021 /* NOTE: we have only 64K ioports on PC */
1022 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
1023 return PCI_BAR_UNMAPPED
;
1028 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1029 return PCI_BAR_UNMAPPED
;
1031 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1032 new_addr
= pci_get_quad(d
->config
+ bar
);
1034 new_addr
= pci_get_long(d
->config
+ bar
);
1036 /* the ROM slot has a specific enable bit */
1037 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1038 return PCI_BAR_UNMAPPED
;
1040 new_addr
&= ~(size
- 1);
1041 last_addr
= new_addr
+ size
- 1;
1042 /* NOTE: we do not support wrapping */
1043 /* XXX: as we cannot support really dynamic
1044 mappings, we handle specific values as invalid
1046 if (last_addr
<= new_addr
|| new_addr
== 0 ||
1047 last_addr
== PCI_BAR_UNMAPPED
) {
1048 return PCI_BAR_UNMAPPED
;
1051 /* Now pcibus_t is 64bit.
1052 * Check if 32 bit BAR wraps around explicitly.
1053 * Without this, PC ide doesn't work well.
1054 * TODO: remove this work around.
1056 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1057 return PCI_BAR_UNMAPPED
;
1061 * OS is allowed to set BAR beyond its addressable
1062 * bits. For example, 32 bit OS can set 64bit bar
1063 * to >4G. Check it. TODO: we might need to support
1064 * it in the future for e.g. PAE.
1066 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
1067 return PCI_BAR_UNMAPPED
;
1073 static void pci_update_mappings(PCIDevice
*d
)
1077 pcibus_t new_addr
, filtered_size
;
1079 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1080 r
= &d
->io_regions
[i
];
1082 /* this region isn't registered */
1086 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1088 /* bridge filtering */
1089 filtered_size
= r
->size
;
1090 if (new_addr
!= PCI_BAR_UNMAPPED
) {
1091 pci_bridge_filter(d
, &new_addr
, &filtered_size
, r
->type
);
1094 /* This bar isn't changed */
1095 if (new_addr
== r
->addr
&& filtered_size
== r
->filtered_size
)
1098 /* now do the real mapping */
1099 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1100 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1102 /* NOTE: specific hack for IDE in PC case:
1103 only one byte must be mapped. */
1104 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1105 if (class == 0x0101 && r
->size
== 4) {
1106 isa_unassign_ioport(r
->addr
+ 2, 1);
1108 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
1111 cpu_register_physical_memory(pci_to_cpu_addr(d
->bus
, r
->addr
),
1114 qemu_unregister_coalesced_mmio(r
->addr
, r
->filtered_size
);
1118 r
->filtered_size
= filtered_size
;
1119 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1121 * TODO: currently almost all the map funcions assumes
1122 * filtered_size == size and addr & ~(size - 1) == addr.
1123 * However with bridge filtering, they aren't always true.
1124 * Teach them such cases, such that filtered_size < size and
1125 * addr & (size - 1) != 0.
1127 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1128 r
->map_func(d
, i
, r
->addr
, r
->filtered_size
, r
->type
);
1130 r
->map_func(d
, i
, pci_to_cpu_addr(d
->bus
, r
->addr
),
1131 r
->filtered_size
, r
->type
);
1137 static inline int pci_irq_disabled(PCIDevice
*d
)
1139 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1142 /* Called after interrupt disabled field update in config space,
1143 * assert/deassert interrupts if necessary.
1144 * Gets original interrupt disable bit value (before update). */
1145 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1147 int i
, disabled
= pci_irq_disabled(d
);
1148 if (disabled
== was_irq_disabled
)
1150 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1151 int state
= pci_irq_state(d
, i
);
1152 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1156 static uint32_t pci_read_config(PCIDevice
*d
,
1157 uint32_t address
, int len
)
1161 len
= MIN(len
, pci_config_size(d
) - address
);
1162 memcpy(&val
, d
->config
+ address
, len
);
1163 return le32_to_cpu(val
);
1166 uint32_t pci_default_read_config(PCIDevice
*d
,
1167 uint32_t address
, int len
)
1169 assert(len
== 1 || len
== 2 || len
== 4);
1171 if (pci_access_cap_config(d
, address
, len
)) {
1172 return d
->cap
.config_read(d
, address
, len
);
1175 return pci_read_config(d
, address
, len
);
1178 static void pci_write_config(PCIDevice
*pci_dev
,
1179 uint32_t address
, uint32_t val
, int len
)
1182 for (i
= 0; i
< len
; i
++) {
1183 pci_dev
->config
[address
+ i
] = val
& 0xff;
1188 int pci_access_cap_config(PCIDevice
*pci_dev
, uint32_t address
, int len
)
1190 if (pci_dev
->cap
.supported
&& address
>= pci_dev
->cap
.start
&&
1191 (address
+ len
) < pci_dev
->cap
.start
+ pci_dev
->cap
.length
)
1196 uint32_t pci_default_cap_read_config(PCIDevice
*pci_dev
,
1197 uint32_t address
, int len
)
1199 return pci_read_config(pci_dev
, address
, len
);
1202 void pci_default_cap_write_config(PCIDevice
*pci_dev
,
1203 uint32_t address
, uint32_t val
, int len
)
1205 pci_write_config(pci_dev
, address
, val
, len
);
1208 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1210 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1211 uint32_t config_size
= pci_config_size(d
);
1213 if (pci_access_cap_config(d
, addr
, l
)) {
1214 d
->cap
.config_write(d
, addr
, val
, l
);
1218 for (i
= 0; i
< l
&& addr
+ i
< config_size
; val
>>= 8, ++i
) {
1219 uint8_t wmask
= d
->wmask
[addr
+ i
];
1220 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1223 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1224 if (kvm_enabled() && kvm_irqchip_in_kernel() &&
1225 addr
>= PIIX_CONFIG_IRQ_ROUTE
&&
1226 addr
< PIIX_CONFIG_IRQ_ROUTE
+ 4)
1227 assigned_dev_update_irqs();
1228 #endif /* CONFIG_KVM_DEVICE_ASSIGNMENT */
1230 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1231 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1232 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1233 range_covers_byte(addr
, l
, PCI_COMMAND
))
1234 pci_update_mappings(d
);
1236 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1237 pci_update_irq_disabled(d
, was_irq_disabled
);
1240 /***********************************************************/
1241 /* generic PCI irq support */
1243 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1244 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1246 PCIDevice
*pci_dev
= opaque
;
1249 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1253 #if defined(TARGET_IA64)
1254 ioapic_set_irq(pci_dev
, irq_num
, level
);
1257 pci_set_irq_state(pci_dev
, irq_num
, level
);
1258 pci_update_irq_status(pci_dev
);
1259 if (pci_irq_disabled(pci_dev
))
1261 pci_change_irq_level(pci_dev
, irq_num
, change
);
1264 int pci_map_irq(PCIDevice
*pci_dev
, int pin
)
1266 return pci_dev
->bus
->map_irq(pci_dev
, pin
);
1269 /***********************************************************/
1270 /* monitor info on PCI */
1277 static const pci_class_desc pci_class_descriptions
[] =
1279 { 0x0100, "SCSI controller"},
1280 { 0x0101, "IDE controller"},
1281 { 0x0102, "Floppy controller"},
1282 { 0x0103, "IPI controller"},
1283 { 0x0104, "RAID controller"},
1284 { 0x0106, "SATA controller"},
1285 { 0x0107, "SAS controller"},
1286 { 0x0180, "Storage controller"},
1287 { 0x0200, "Ethernet controller"},
1288 { 0x0201, "Token Ring controller"},
1289 { 0x0202, "FDDI controller"},
1290 { 0x0203, "ATM controller"},
1291 { 0x0280, "Network controller"},
1292 { 0x0300, "VGA controller"},
1293 { 0x0301, "XGA controller"},
1294 { 0x0302, "3D controller"},
1295 { 0x0380, "Display controller"},
1296 { 0x0400, "Video controller"},
1297 { 0x0401, "Audio controller"},
1299 { 0x0480, "Multimedia controller"},
1300 { 0x0500, "RAM controller"},
1301 { 0x0501, "Flash controller"},
1302 { 0x0580, "Memory controller"},
1303 { 0x0600, "Host bridge"},
1304 { 0x0601, "ISA bridge"},
1305 { 0x0602, "EISA bridge"},
1306 { 0x0603, "MC bridge"},
1307 { 0x0604, "PCI bridge"},
1308 { 0x0605, "PCMCIA bridge"},
1309 { 0x0606, "NUBUS bridge"},
1310 { 0x0607, "CARDBUS bridge"},
1311 { 0x0608, "RACEWAY bridge"},
1312 { 0x0680, "Bridge"},
1313 { 0x0c03, "USB controller"},
1317 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1318 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1323 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1324 d
= bus
->devices
[devfn
];
1331 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1332 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1334 bus
= pci_find_bus(bus
, bus_num
);
1337 pci_for_each_device_under_bus(bus
, fn
);
1341 static void pci_device_print(Monitor
*mon
, QDict
*device
)
1345 uint64_t addr
, size
;
1347 monitor_printf(mon
, " Bus %2" PRId64
", ", qdict_get_int(device
, "bus"));
1348 monitor_printf(mon
, "device %3" PRId64
", function %" PRId64
":\n",
1349 qdict_get_int(device
, "slot"),
1350 qdict_get_int(device
, "function"));
1351 monitor_printf(mon
, " ");
1353 qdict
= qdict_get_qdict(device
, "class_info");
1354 if (qdict_haskey(qdict
, "desc")) {
1355 monitor_printf(mon
, "%s", qdict_get_str(qdict
, "desc"));
1357 monitor_printf(mon
, "Class %04" PRId64
, qdict_get_int(qdict
, "class"));
1360 qdict
= qdict_get_qdict(device
, "id");
1361 monitor_printf(mon
, ": PCI device %04" PRIx64
":%04" PRIx64
"\n",
1362 qdict_get_int(qdict
, "device"),
1363 qdict_get_int(qdict
, "vendor"));
1365 if (qdict_haskey(device
, "irq")) {
1366 monitor_printf(mon
, " IRQ %" PRId64
".\n",
1367 qdict_get_int(device
, "irq"));
1370 if (qdict_haskey(device
, "pci_bridge")) {
1373 qdict
= qdict_get_qdict(device
, "pci_bridge");
1375 info
= qdict_get_qdict(qdict
, "bus");
1376 monitor_printf(mon
, " BUS %" PRId64
".\n",
1377 qdict_get_int(info
, "number"));
1378 monitor_printf(mon
, " secondary bus %" PRId64
".\n",
1379 qdict_get_int(info
, "secondary"));
1380 monitor_printf(mon
, " subordinate bus %" PRId64
".\n",
1381 qdict_get_int(info
, "subordinate"));
1383 info
= qdict_get_qdict(qdict
, "io_range");
1384 monitor_printf(mon
, " IO range [0x%04"PRIx64
", 0x%04"PRIx64
"]\n",
1385 qdict_get_int(info
, "base"),
1386 qdict_get_int(info
, "limit"));
1388 info
= qdict_get_qdict(qdict
, "memory_range");
1390 " memory range [0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1391 qdict_get_int(info
, "base"),
1392 qdict_get_int(info
, "limit"));
1394 info
= qdict_get_qdict(qdict
, "prefetchable_range");
1395 monitor_printf(mon
, " prefetchable memory range "
1396 "[0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1397 qdict_get_int(info
, "base"),
1398 qdict_get_int(info
, "limit"));
1401 QLIST_FOREACH_ENTRY(qdict_get_qlist(device
, "regions"), entry
) {
1402 qdict
= qobject_to_qdict(qlist_entry_obj(entry
));
1403 monitor_printf(mon
, " BAR%d: ", (int) qdict_get_int(qdict
, "bar"));
1405 addr
= qdict_get_int(qdict
, "address");
1406 size
= qdict_get_int(qdict
, "size");
1408 if (!strcmp(qdict_get_str(qdict
, "type"), "io")) {
1409 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
1410 " [0x%04"FMT_PCIBUS
"].\n",
1411 addr
, addr
+ size
- 1);
1413 monitor_printf(mon
, "%d bit%s memory at 0x%08"FMT_PCIBUS
1414 " [0x%08"FMT_PCIBUS
"].\n",
1415 qdict_get_bool(qdict
, "mem_type_64") ? 64 : 32,
1416 qdict_get_bool(qdict
, "prefetch") ?
1417 " prefetchable" : "", addr
, addr
+ size
- 1);
1421 monitor_printf(mon
, " id \"%s\"\n", qdict_get_str(device
, "qdev_id"));
1423 if (qdict_haskey(device
, "pci_bridge")) {
1424 qdict
= qdict_get_qdict(device
, "pci_bridge");
1425 if (qdict_haskey(qdict
, "devices")) {
1427 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1428 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1434 void do_pci_info_print(Monitor
*mon
, const QObject
*data
)
1436 QListEntry
*bus
, *dev
;
1438 QLIST_FOREACH_ENTRY(qobject_to_qlist(data
), bus
) {
1439 QDict
*qdict
= qobject_to_qdict(qlist_entry_obj(bus
));
1440 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1441 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1446 static QObject
*pci_get_dev_class(const PCIDevice
*dev
)
1449 const pci_class_desc
*desc
;
1451 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1452 desc
= pci_class_descriptions
;
1453 while (desc
->desc
&& class != desc
->class)
1457 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1460 return qobject_from_jsonf("{ 'class': %d }", class);
1464 static QObject
*pci_get_dev_id(const PCIDevice
*dev
)
1466 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1467 pci_get_word(dev
->config
+ PCI_VENDOR_ID
),
1468 pci_get_word(dev
->config
+ PCI_DEVICE_ID
));
1471 static QObject
*pci_get_regions_list(const PCIDevice
*dev
)
1474 QList
*regions_list
;
1476 regions_list
= qlist_new();
1478 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1480 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1486 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1487 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1488 "'address': %" PRId64
", "
1489 "'size': %" PRId64
" }",
1490 i
, r
->addr
, r
->size
);
1492 int mem_type_64
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
;
1494 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1495 "'mem_type_64': %i, 'prefetch': %i, "
1496 "'address': %" PRId64
", "
1497 "'size': %" PRId64
" }",
1499 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
,
1503 qlist_append_obj(regions_list
, obj
);
1506 return QOBJECT(regions_list
);
1509 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
);
1511 static QObject
*pci_get_dev_dict(PCIDevice
*dev
, PCIBus
*bus
, int bus_num
)
1516 obj
= qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1519 PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
),
1520 pci_get_dev_class(dev
), pci_get_dev_id(dev
),
1521 pci_get_regions_list(dev
),
1522 dev
->qdev
.id
? dev
->qdev
.id
: "");
1524 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1525 QDict
*qdict
= qobject_to_qdict(obj
);
1526 qdict_put(qdict
, "irq", qint_from_int(dev
->config
[PCI_INTERRUPT_LINE
]));
1529 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1530 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1532 QObject
*pci_bridge
;
1534 pci_bridge
= qobject_from_jsonf("{ 'bus': "
1535 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1536 "'io_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1537 "'memory_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1538 "'prefetchable_range': { 'base': %" PRId64
", 'limit': %" PRId64
"} }",
1539 dev
->config
[PCI_PRIMARY_BUS
], dev
->config
[PCI_SECONDARY_BUS
],
1540 dev
->config
[PCI_SUBORDINATE_BUS
],
1541 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1542 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1543 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1544 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1545 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1546 PCI_BASE_ADDRESS_MEM_PREFETCH
),
1547 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1548 PCI_BASE_ADDRESS_MEM_PREFETCH
));
1550 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1551 PCIBus
*child_bus
= pci_find_bus(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1554 qdict
= qobject_to_qdict(pci_bridge
);
1555 qdict_put_obj(qdict
, "devices",
1556 pci_get_devices_list(child_bus
,
1557 dev
->config
[PCI_SECONDARY_BUS
]));
1560 qdict
= qobject_to_qdict(obj
);
1561 qdict_put_obj(qdict
, "pci_bridge", pci_bridge
);
1567 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
)
1573 dev_list
= qlist_new();
1575 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1576 dev
= bus
->devices
[devfn
];
1578 qlist_append_obj(dev_list
, pci_get_dev_dict(dev
, bus
, bus_num
));
1582 return QOBJECT(dev_list
);
1585 static QObject
*pci_get_bus_dict(PCIBus
*bus
, int bus_num
)
1587 bus
= pci_find_bus(bus
, bus_num
);
1589 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1590 bus_num
, pci_get_devices_list(bus
, bus_num
));
1596 void do_pci_info(Monitor
*mon
, QObject
**ret_data
)
1599 struct PCIHostBus
*host
;
1601 bus_list
= qlist_new();
1603 QLIST_FOREACH(host
, &host_buses
, next
) {
1604 QObject
*obj
= pci_get_bus_dict(host
->bus
, 0);
1606 qlist_append_obj(bus_list
, obj
);
1610 *ret_data
= QOBJECT(bus_list
);
1613 static const char * const pci_nic_models
[] = {
1625 static const char * const pci_nic_names
[] = {
1637 /* Initialize a PCI NIC. */
1638 /* FIXME callers should check for failure, but don't */
1639 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1640 const char *default_devaddr
)
1642 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1649 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1653 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1655 error_report("Invalid PCI device address %s for device %s",
1656 devaddr
, pci_nic_names
[i
]);
1660 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1661 dev
= &pci_dev
->qdev
;
1662 qdev_set_nic_properties(dev
, nd
);
1663 if (qdev_init(dev
) < 0)
1668 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1669 const char *default_devaddr
)
1673 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1676 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1690 static void pci_bridge_update_mappings_fn(PCIBus
*b
, PCIDevice
*d
)
1692 pci_update_mappings(d
);
1695 static void pci_bridge_update_mappings(PCIBus
*b
)
1699 pci_for_each_device_under_bus(b
, pci_bridge_update_mappings_fn
);
1701 QLIST_FOREACH(child
, &b
->child
, sibling
) {
1702 pci_bridge_update_mappings(child
);
1706 static void pci_bridge_write_config(PCIDevice
*d
,
1707 uint32_t address
, uint32_t val
, int len
)
1709 pci_default_write_config(d
, address
, val
, len
);
1711 if (/* io base/limit */
1712 ranges_overlap(address
, len
, PCI_IO_BASE
, 2) ||
1714 /* memory base/limit, prefetchable base/limit and
1715 io base/limit upper 16 */
1716 ranges_overlap(address
, len
, PCI_MEMORY_BASE
, 20)) {
1717 PCIBridge
*s
= container_of(d
, PCIBridge
, dev
);
1718 PCIBus
*secondary_bus
= &s
->bus
;
1719 pci_bridge_update_mappings(secondary_bus
);
1723 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1731 if (pci_bus_num(bus
) == bus_num
) {
1736 if (!bus
->parent_dev
/* host pci bridge */ ||
1737 (bus
->parent_dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1738 bus_num
<= bus
->parent_dev
->config
[PCI_SUBORDINATE_BUS
])) {
1739 for (; bus
; bus
= sec
) {
1740 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1741 assert(sec
->parent_dev
);
1742 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1745 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1746 bus_num
<= sec
->parent_dev
->config
[PCI_SUBORDINATE_BUS
]) {
1756 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, int slot
, int function
)
1758 bus
= pci_find_bus(bus
, bus_num
);
1763 return bus
->devices
[PCI_DEVFN(slot
, function
)];
1766 static int pci_bridge_initfn(PCIDevice
*dev
)
1768 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1770 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
1771 pci_config_set_device_id(s
->dev
.config
, s
->did
);
1773 pci_set_word(dev
->config
+ PCI_STATUS
,
1774 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1775 pci_config_set_class(dev
->config
, PCI_CLASS_BRIDGE_PCI
);
1776 dev
->config
[PCI_HEADER_TYPE
] =
1777 (dev
->config
[PCI_HEADER_TYPE
] & PCI_HEADER_TYPE_MULTI_FUNCTION
) |
1778 PCI_HEADER_TYPE_BRIDGE
;
1779 pci_set_word(dev
->config
+ PCI_SEC_STATUS
,
1780 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1784 static int pci_bridge_exitfn(PCIDevice
*pci_dev
)
1786 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, pci_dev
);
1787 PCIBus
*bus
= &s
->bus
;
1788 pci_unregister_secondary_bus(bus
);
1792 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, bool multifunction
,
1793 uint16_t vid
, uint16_t did
,
1794 pci_map_irq_fn map_irq
, const char *name
)
1799 dev
= pci_create_multifunction(bus
, devfn
, multifunction
, "pci-bridge");
1800 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
1801 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
1802 qdev_init_nofail(&dev
->qdev
);
1804 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1805 pci_register_secondary_bus(bus
, &s
->bus
, &s
->dev
, map_irq
, name
);
1809 PCIDevice
*pci_bridge_get_device(PCIBus
*bus
)
1811 return bus
->parent_dev
;
1814 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1816 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1817 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
1821 /* initialize cap_present for pci_is_express() and pci_config_size() */
1822 if (info
->is_express
) {
1823 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1826 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1827 devfn
= pci_dev
->devfn
;
1828 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
1829 info
->config_read
, info
->config_write
,
1831 if (pci_dev
== NULL
)
1833 rc
= info
->init(pci_dev
);
1835 do_pci_unregister_device(pci_dev
);
1840 if (pci_dev
->romfile
== NULL
&& info
->romfile
!= NULL
)
1841 pci_dev
->romfile
= qemu_strdup(info
->romfile
);
1842 pci_add_option_rom(pci_dev
);
1844 if (qdev
->hotplugged
) {
1845 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
, 1);
1847 int r
= pci_unregister_device(&pci_dev
->qdev
);
1855 static int pci_unplug_device(DeviceState
*qdev
)
1857 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1859 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
, 0);
1862 void pci_qdev_register(PCIDeviceInfo
*info
)
1864 info
->qdev
.init
= pci_qdev_init
;
1865 info
->qdev
.unplug
= pci_unplug_device
;
1866 info
->qdev
.exit
= pci_unregister_device
;
1867 info
->qdev
.bus_info
= &pci_bus_info
;
1868 qdev_register(&info
->qdev
);
1871 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1873 while (info
->qdev
.name
) {
1874 pci_qdev_register(info
);
1879 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1884 dev
= qdev_create(&bus
->qbus
, name
);
1885 qdev_prop_set_uint32(dev
, "addr", devfn
);
1886 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1887 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1890 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1894 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1895 qdev_init_nofail(&dev
->qdev
);
1899 int pci_enable_capability_support(PCIDevice
*pci_dev
,
1900 uint32_t config_start
,
1901 PCICapConfigReadFunc
*config_read
,
1902 PCICapConfigWriteFunc
*config_write
,
1903 PCICapConfigInitFunc
*config_init
)
1908 pci_dev
->config
[0x06] |= 0x10; // status = capabilities
1910 if (config_start
== 0)
1911 pci_dev
->cap
.start
= PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR
;
1912 else if (config_start
>= 0x40 && config_start
< 0xff)
1913 pci_dev
->cap
.start
= config_start
;
1918 pci_dev
->cap
.config_read
= config_read
;
1920 pci_dev
->cap
.config_read
= pci_default_cap_read_config
;
1922 pci_dev
->cap
.config_write
= config_write
;
1924 pci_dev
->cap
.config_write
= pci_default_cap_write_config
;
1925 pci_dev
->cap
.supported
= 1;
1926 pci_dev
->config
[PCI_CAPABILITY_LIST
] = pci_dev
->cap
.start
;
1927 return config_init(pci_dev
);
1930 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1932 return pci_create_multifunction(bus
, devfn
, false, name
);
1935 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1937 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1940 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1942 int config_size
= pci_config_size(pdev
);
1943 int offset
= PCI_CONFIG_HEADER_SIZE
;
1945 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1948 else if (i
- offset
+ 1 == size
)
1953 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1958 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1961 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1962 prev
= next
+ PCI_CAP_LIST_NEXT
)
1963 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1971 void pci_map_option_rom(PCIDevice
*pdev
, int region_num
, pcibus_t addr
, pcibus_t size
, int type
)
1973 cpu_register_physical_memory(addr
, size
, pdev
->rom_offset
);
1976 /* Add an option rom for the device */
1977 static int pci_add_option_rom(PCIDevice
*pdev
)
1986 if (strlen(pdev
->romfile
) == 0)
1989 if (!pdev
->rom_bar
) {
1991 * Load rom via fw_cfg instead of creating a rom bar,
1992 * for 0.11 compatibility.
1994 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1995 if (class == 0x0300) {
1996 rom_add_vga(pdev
->romfile
);
1998 rom_add_option(pdev
->romfile
);
2003 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2005 path
= qemu_strdup(pdev
->romfile
);
2008 size
= get_image_size(path
);
2010 error_report("%s: failed to find romfile \"%s\"",
2011 __FUNCTION__
, pdev
->romfile
);
2014 if (size
& (size
- 1)) {
2015 size
= 1 << qemu_fls(size
);
2018 if (pdev
->qdev
.info
->vmsd
)
2019 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->vmsd
->name
);
2021 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->name
);
2022 pdev
->rom_offset
= qemu_ram_alloc(&pdev
->qdev
, name
, size
);
2024 ptr
= qemu_get_ram_ptr(pdev
->rom_offset
);
2025 load_image(path
, ptr
);
2028 pci_register_bar(pdev
, PCI_ROM_SLOT
, size
,
2029 0, pci_map_option_rom
);
2034 static void pci_del_option_rom(PCIDevice
*pdev
)
2036 if (!pdev
->rom_offset
)
2039 qemu_ram_free(pdev
->rom_offset
);
2040 pdev
->rom_offset
= 0;
2043 /* Reserve space and add capability to the linked list in pci config space */
2044 int pci_add_capability_at_offset(PCIDevice
*pdev
, uint8_t cap_id
,
2045 uint8_t offset
, uint8_t size
)
2047 uint8_t *config
= pdev
->config
+ offset
;
2048 config
[PCI_CAP_LIST_ID
] = cap_id
;
2049 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2050 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2051 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2052 memset(pdev
->used
+ offset
, 0xFF, size
);
2053 /* Make capability read-only by default */
2054 memset(pdev
->wmask
+ offset
, 0, size
);
2055 /* Check capability by default */
2056 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2060 /* Find and reserve space and add capability to the linked list
2061 * in pci config space */
2062 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2064 uint8_t offset
= pci_find_space(pdev
, size
);
2068 return pci_add_capability_at_offset(pdev
, cap_id
, offset
, size
);
2071 /* Unlink capability from the pci config space. */
2072 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2074 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2077 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2078 /* Make capability writeable again */
2079 memset(pdev
->wmask
+ offset
, 0xff, size
);
2080 /* Clear cmask as device-specific registers can't be checked */
2081 memset(pdev
->cmask
+ offset
, 0, size
);
2082 memset(pdev
->used
+ offset
, 0, size
);
2084 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2085 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2088 /* Reserve space for capability at a known offset (to call after load). */
2089 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
2091 memset(pdev
->used
+ offset
, 0xff, size
);
2094 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2096 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2099 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2101 PCIDevice
*d
= (PCIDevice
*)dev
;
2102 const pci_class_desc
*desc
;
2107 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2108 desc
= pci_class_descriptions
;
2109 while (desc
->desc
&& class != desc
->class)
2112 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2114 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2117 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2118 "pci id %04x:%04x (sub %04x:%04x)\n",
2120 d
->config
[PCI_SECONDARY_BUS
],
2121 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2122 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2123 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2124 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2125 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2126 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2127 r
= &d
->io_regions
[i
];
2130 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2131 " [0x%"FMT_PCIBUS
"]\n",
2133 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2134 r
->addr
, r
->addr
+ r
->size
- 1);
2138 static char *pcibus_get_dev_path(DeviceState
*dev
)
2140 PCIDevice
*d
= (PCIDevice
*)dev
;
2143 snprintf(path
, sizeof(path
), "%04x:%02x:%02x.%x",
2144 pci_find_domain(d
->bus
), d
->config
[PCI_SECONDARY_BUS
],
2145 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
));
2147 return strdup(path
);
2150 static PCIDeviceInfo bridge_info
= {
2151 .qdev
.name
= "pci-bridge",
2152 .qdev
.size
= sizeof(PCIBridge
),
2153 .init
= pci_bridge_initfn
,
2154 .exit
= pci_bridge_exitfn
,
2155 .config_write
= pci_bridge_write_config
,
2157 .qdev
.props
= (Property
[]) {
2158 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
2159 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
2160 DEFINE_PROP_END_OF_LIST(),
2164 static void pci_register_devices(void)
2166 pci_qdev_register(&bridge_info
);
2169 device_init(pci_register_devices
)