hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8 #include "kvm.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78
  79 #define FMT_PCIBUS                      PRIx64
  80
  81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  82                                 uint32_t address, uint32_t data, int len);
  83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  84                                    uint32_t address, int len);
  85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  86                                 pcibus_t addr, pcibus_t size, int type);
  87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  88
  89 typedef struct PCIIORegion {
  90     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  92     pcibus_t size;
  93     pcibus_t filtered_size;
  94     uint8_t type;
  95     PCIMapIORegionFunc *map_func;
  96 } PCIIORegion;
  97
  98 #define PCI_ROM_SLOT 6
  99 #define PCI_NUM_REGIONS 7
 100
 101 #include "pci_regs.h"
 102
 103 /* PCI HEADER_TYPE */
 104 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 105
 106 /* Size of the standard PCI config header */
 107 #define PCI_CONFIG_HEADER_SIZE 0x40
 108 /* Size of the standard PCI config space */
 109 #define PCI_CONFIG_SPACE_SIZE 0x100
 110 /* Size of the standart PCIe config space: 4KB */
 111 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 112
 113 #define PCI_NUM_PINS 4 /* A-D */
 114
 115 /* Bits in cap_present field. */
 116 enum {
 117     QEMU_PCI_CAP_MSI = 0x1,
 118     QEMU_PCI_CAP_MSIX = 0x2,
 119     QEMU_PCI_CAP_EXPRESS = 0x4,
 120
 121     /* multifunction capable device */
 122 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 123     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 124
 125     /* command register SERR bit enabled */
 126 #define QEMU_PCI_CAP_SERR_BITNR 4
 127     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 128 };
 129
 130 typedef int (*msix_mask_notifier_func)(PCIDevice *, unsigned vector,
 131                                        int masked);
 132
 133 struct PCIDevice {
 134     DeviceState qdev;
 135     /* PCI config space */
 136     uint8_t *config;
 137
 138     /* Used to enable config checks on load. Note that writeable bits are
 139      * never checked even if set in cmask. */
 140     uint8_t *cmask;
 141
 142     /* Used to implement R/W bytes */
 143     uint8_t *wmask;
 144
 145     /* Used to implement RW1C(Write 1 to Clear) bytes */
 146     uint8_t *w1cmask;
 147
 148     /* Used to allocate config space and track capabilities. */
 149     uint8_t *config_map;
 150
 151     /* the following fields are read only */
 152     PCIBus *bus;
 153     uint32_t devfn;
 154     char name[64];
 155     PCIIORegion io_regions[PCI_NUM_REGIONS];
 156
 157     /* do not access the following fields */
 158     PCIConfigReadFunc *config_read;
 159     PCIConfigWriteFunc *config_write;
 160
 161     /* IRQ objects for the INTA-INTD pins.  */
 162     qemu_irq *irq;
 163
 164     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 165     uint8_t irq_state;
 166
 167     /* Capability bits */
 168     uint32_t cap_present;
 169
 170     /* Offset of MSI-X capability in config space */
 171     uint8_t msix_cap;
 172
 173     /* MSI-X entries */
 174     int msix_entries_nr;
 175
 176     /* Space to store MSIX table */
 177     uint8_t *msix_table_page;
 178     /* MMIO index used to map MSIX table and pending bit entries. */
 179     int msix_mmio_index;
 180     /* Reference-count for entries actually in use by driver. */
 181     unsigned *msix_entry_used;
 182     /* Region including the MSI-X table */
 183     uint32_t msix_bar_size;
 184     /* Version id needed for VMState */
 185     int32_t version_id;
 186
 187     /* Offset of MSI capability in config space */
 188     uint8_t msi_cap;
 189
 190     /* PCI Express */
 191     PCIExpressDevice exp;
 192
 193     /* Location of option rom */
 194     char *romfile;
 195     ram_addr_t rom_offset;
 196     uint32_t rom_bar;
 197
 198     /* How much space does an MSIX table need. */
 199     /* The spec requires giving the table structure
 200      * a 4K aligned region all by itself. Align it to
 201      * target pages so that drivers can do passthrough
 202      * on the rest of the region. */
 203     target_phys_addr_t msix_page_size;
 204
 205     KVMMsiMessage *msix_irq_entries;
 206
 207     msix_mask_notifier_func msix_mask_notifier;
 208 };
 209
 210 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 211                                int instance_size, int devfn,
 212                                PCIConfigReadFunc *config_read,
 213                                PCIConfigWriteFunc *config_write);
 214
 215 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 216                             pcibus_t size, uint8_t type,
 217                             PCIMapIORegionFunc *map_func);
 218
 219 void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr,
 220                         pcibus_t size, int type);
 221
 222 int pci_map_irq(PCIDevice *pci_dev, int pin);
 223
 224 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 225                        uint8_t offset, uint8_t size);
 226
 227 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 228
 229 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 230
 231 uint32_t pci_default_read_config(PCIDevice *d,
 232                                  uint32_t address, int len);
 233 void pci_default_write_config(PCIDevice *d,
 234                               uint32_t address, uint32_t val, int len);
 235 void pci_device_save(PCIDevice *s, QEMUFile *f);
 236 int pci_device_load(PCIDevice *s, QEMUFile *f);
 237 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 238 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 239
 240 typedef enum {
 241     PCI_HOTPLUG_DISABLED,
 242     PCI_HOTPLUG_ENABLED,
 243     PCI_COLDPLUG_ENABLED,
 244 } PCIHotplugState;
 245
 246 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 247                               PCIHotplugState state);
 248 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 249                          const char *name, uint8_t devfn_min);
 250 PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min);
 251 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 252                   void *irq_opaque, int nirq);
 253 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 254 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 255                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 256                          void *irq_opaque, uint8_t devfn_min, int nirq);
 257 void pci_device_reset(PCIDevice *dev);
 258 void pci_bus_reset(PCIBus *bus);
 259
 260 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 261
 262 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 263                         const char *default_devaddr);
 264 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 265                                const char *default_devaddr);
 266 int pci_bus_num(PCIBus *s);
 267 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 268 PCIBus *pci_find_root_bus(int domain);
 269 int pci_find_domain(const PCIBus *bus);
 270 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 271 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 272 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 273 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 274
 275 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 276                       unsigned int *slotp, unsigned int *funcp);
 277 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 278                      unsigned *slotp);
 279
 280 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
 281                            int *slotp, int *funcp);
 282
 283 void do_pci_info_print(Monitor *mon, const QObject *data);
 284 void do_pci_info(Monitor *mon, QObject **ret_data);
 285 void pci_bridge_update_mappings(PCIBus *b);
 286
 287 void pci_device_deassert_intx(PCIDevice *dev);
 288
 289 static inline void
 290 pci_set_byte(uint8_t *config, uint8_t val)
 291 {
 292     *config = val;
 293 }
 294
 295 static inline uint8_t
 296 pci_get_byte(const uint8_t *config)
 297 {
 298     return *config;
 299 }
 300
 301 static inline void
 302 pci_set_word(uint8_t *config, uint16_t val)
 303 {
 304     cpu_to_le16wu((uint16_t *)config, val);
 305 }
 306
 307 static inline uint16_t
 308 pci_get_word(const uint8_t *config)
 309 {
 310     return le16_to_cpupu((const uint16_t *)config);
 311 }
 312
 313 static inline void
 314 pci_set_long(uint8_t *config, uint32_t val)
 315 {
 316     cpu_to_le32wu((uint32_t *)config, val);
 317 }
 318
 319 static inline uint32_t
 320 pci_get_long(const uint8_t *config)
 321 {
 322     return le32_to_cpupu((const uint32_t *)config);
 323 }
 324
 325 static inline void
 326 pci_set_quad(uint8_t *config, uint64_t val)
 327 {
 328     cpu_to_le64w((uint64_t *)config, val);
 329 }
 330
 331 static inline uint64_t
 332 pci_get_quad(const uint8_t *config)
 333 {
 334     return le64_to_cpup((const uint64_t *)config);
 335 }
 336
 337 static inline void
 338 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 339 {
 340     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 341 }
 342
 343 static inline void
 344 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 345 {
 346     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 347 }
 348
 349 static inline void
 350 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 351 {
 352     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 353 }
 354
 355 static inline void
 356 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 357 {
 358     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 359 }
 360
 361 static inline void
 362 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 363 {
 364     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 365 }
 366
 367 static inline void
 368 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 369 {
 370     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 371 }
 372
 373 /*
 374  * helper functions to do bit mask operation on configuration space.
 375  * Just to set bit, use test-and-set and discard returned value.
 376  * Just to clear bit, use test-and-clear and discard returned value.
 377  * NOTE: They aren't atomic.
 378  */
 379 static inline uint8_t
 380 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 381 {
 382     uint8_t val = pci_get_byte(config);
 383     pci_set_byte(config, val & ~mask);
 384     return val & mask;
 385 }
 386
 387 static inline uint8_t
 388 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 389 {
 390     uint8_t val = pci_get_byte(config);
 391     pci_set_byte(config, val | mask);
 392     return val & mask;
 393 }
 394
 395 static inline uint16_t
 396 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 397 {
 398     uint16_t val = pci_get_word(config);
 399     pci_set_word(config, val & ~mask);
 400     return val & mask;
 401 }
 402
 403 static inline uint16_t
 404 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 405 {
 406     uint16_t val = pci_get_word(config);
 407     pci_set_word(config, val | mask);
 408     return val & mask;
 409 }
 410
 411 static inline uint32_t
 412 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 413 {
 414     uint32_t val = pci_get_long(config);
 415     pci_set_long(config, val & ~mask);
 416     return val & mask;
 417 }
 418
 419 static inline uint32_t
 420 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 421 {
 422     uint32_t val = pci_get_long(config);
 423     pci_set_long(config, val | mask);
 424     return val & mask;
 425 }
 426
 427 static inline uint64_t
 428 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 429 {
 430     uint64_t val = pci_get_quad(config);
 431     pci_set_quad(config, val & ~mask);
 432     return val & mask;
 433 }
 434
 435 static inline uint64_t
 436 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 437 {
 438     uint64_t val = pci_get_quad(config);
 439     pci_set_quad(config, val | mask);
 440     return val & mask;
 441 }
 442
 443 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 444 typedef struct {
 445     DeviceInfo qdev;
 446     pci_qdev_initfn init;
 447     PCIUnregisterFunc *exit;
 448     PCIConfigReadFunc *config_read;
 449     PCIConfigWriteFunc *config_write;
 450
 451     /*
 452      * pci-to-pci bridge or normal device.
 453      * This doesn't mean pci host switch.
 454      * When card bus bridge is supported, this would be enhanced.
 455      */
 456     int is_bridge;
 457
 458     /* pcie stuff */
 459     int is_express;   /* is this device pci express? */
 460
 461     /* device isn't hot-pluggable */
 462     int no_hotplug;
 463
 464     /* rom bar */
 465     const char *romfile;
 466 } PCIDeviceInfo;
 467
 468 void pci_qdev_register(PCIDeviceInfo *info);
 469 void pci_qdev_register_many(PCIDeviceInfo *info);
 470
 471 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 472                                     const char *name);
 473 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 474                                            bool multifunction,
 475                                            const char *name);
 476 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
 477                                         bool multifunction,
 478                                         const char *name);
 479 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 480 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 481 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
 482
 483 static inline int pci_is_express(const PCIDevice *d)
 484 {
 485     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 486 }
 487
 488 static inline uint32_t pci_config_size(const PCIDevice *d)
 489 {
 490     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 491 }
 492
 493 #endif