cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_DEFS_H
  20 #define CPU_DEFS_H
  21
  22 #ifndef NEED_CPU_H
  23 #error cpu.h included from common code
  24 #endif
  25
  26 #include "config.h"
  27 #include <setjmp.h>
  28 #include <inttypes.h>
  29 #include <signal.h>
  30 #include <pthread.h>
  31 #include "osdep.h"
  32 #include "qemu-queue.h"
  33 #include "targphys.h"
  34
  35 #ifndef TARGET_LONG_BITS
  36 #error TARGET_LONG_BITS must be defined before including this header
  37 #endif
  38
  39 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  40
  41 typedef int16_t target_short __attribute__ ((aligned(TARGET_SHORT_ALIGNMENT)));
  42 typedef uint16_t target_ushort __attribute__((aligned(TARGET_SHORT_ALIGNMENT)));
  43 typedef int32_t target_int __attribute__((aligned(TARGET_INT_ALIGNMENT)));
  44 typedef uint32_t target_uint __attribute__((aligned(TARGET_INT_ALIGNMENT)));
  45 typedef int64_t target_llong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
  46 typedef uint64_t target_ullong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
  47 /* target_ulong is the type of a virtual address */
  48 #if TARGET_LONG_SIZE == 4
  49 typedef int32_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
  50 typedef uint32_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
  51 #define TARGET_FMT_lx "%08x"
  52 #define TARGET_FMT_ld "%d"
  53 #define TARGET_FMT_lu "%u"
  54 #elif TARGET_LONG_SIZE == 8
  55 typedef int64_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
  56 typedef uint64_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
  57 #define TARGET_FMT_lx "%016" PRIx64
  58 #define TARGET_FMT_ld "%" PRId64
  59 #define TARGET_FMT_lu "%" PRIu64
  60 #else
  61 #error TARGET_LONG_SIZE undefined
  62 #endif
  63
  64 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
  65
  66 #define EXCP_INTERRUPT  0x10000 /* async interruption */
  67 #define EXCP_HLT        0x10001 /* hlt instruction reached */
  68 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
  69 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
  70
  71 #define TB_JMP_CACHE_BITS 12
  72 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
  73
  74 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
  75    addresses on the same page.  The top bits are the same.  This allows
  76    TLB invalidation to quickly clear a subset of the hash table.  */
  77 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
  78 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
  79 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
  80 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
  81
  82 #if !defined(CONFIG_USER_ONLY)
  83 #define CPU_TLB_BITS 8
  84 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
  85
  86 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
  87 #define CPU_TLB_ENTRY_BITS 4
  88 #else
  89 #define CPU_TLB_ENTRY_BITS 5
  90 #endif
  91
  92 typedef struct CPUTLBEntry {
  93     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
  94        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
  95                                     go directly to ram.
  96        bit 3                      : indicates that the entry is invalid
  97        bit 2..0                   : zero
  98     */
  99     target_ulong addr_read;
 100     target_ulong addr_write;
 101     target_ulong addr_code;
 102     /* Addend to virtual address to get host address.  IO accesses
 103        use the corresponding iotlb value.  */
 104     unsigned long addend;
 105     /* padding to get a power of two size */
 106     uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
 107                   (sizeof(target_ulong) * 3 +
 108                    ((-sizeof(target_ulong) * 3) & (sizeof(unsigned long) - 1)) +
 109                    sizeof(unsigned long))];
 110 } CPUTLBEntry;
 111
 112 extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];
 113
 114 #define CPU_COMMON_TLB \
 115     /* The meaning of the MMU modes is defined in the target code. */   \
 116     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
 117     target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
 118     target_ulong tlb_flush_addr;                                        \
 119     target_ulong tlb_flush_mask;
 120
 121 #else
 122
 123 #define CPU_COMMON_TLB
 124
 125 #endif
 126
 127
 128 #ifdef HOST_WORDS_BIGENDIAN
 129 typedef struct icount_decr_u16 {
 130     uint16_t high;
 131     uint16_t low;
 132 } icount_decr_u16;
 133 #else
 134 typedef struct icount_decr_u16 {
 135     uint16_t low;
 136     uint16_t high;
 137 } icount_decr_u16;
 138 #endif
 139
 140 struct kvm_run;
 141 struct KVMState;
 142 struct qemu_work_item;
 143
 144 typedef struct CPUBreakpoint {
 145     target_ulong pc;
 146     int flags; /* BP_* */
 147     QTAILQ_ENTRY(CPUBreakpoint) entry;
 148 } CPUBreakpoint;
 149
 150 typedef struct CPUWatchpoint {
 151     target_ulong vaddr;
 152     target_ulong len_mask;
 153     int flags; /* BP_* */
 154     QTAILQ_ENTRY(CPUWatchpoint) entry;
 155 } CPUWatchpoint;
 156
 157 /* forward decleration */
 158 struct qemu_work_item;
 159
 160 struct KVMCPUState {
 161     pthread_t thread;
 162     int signalled;
 163     struct qemu_work_item *queued_work_first, *queued_work_last;
 164 };
 165
 166 #define CPU_TEMP_BUF_NLONGS 128
 167 #define CPU_COMMON                                                      \
 168     struct TranslationBlock *current_tb; /* currently executing TB  */  \
 169     /* soft mmu support */                                              \
 170     /* in order to avoid passing too many arguments to the MMIO         \
 171        helpers, we store some rarely used information in the CPU        \
 172        context) */                                                      \
 173     unsigned long mem_io_pc; /* host pc at which the memory was         \
 174                                 accessed */                             \
 175     target_ulong mem_io_vaddr; /* target virtual addr at which the      \
 176                                      memory was accessed */             \
 177     uint32_t halted; /* Nonzero if the CPU is in suspend state */       \
 178     uint32_t interrupt_request;                                         \
 179     volatile sig_atomic_t exit_request;                                 \
 180     CPU_COMMON_TLB                                                      \
 181     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
 182     /* buffer for temporaries in the code generator */                  \
 183     long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \
 184                                                                         \
 185     int64_t icount_extra; /* Instructions until next timer event.  */   \
 186     /* Number of cycles left, with interrupt flag in high bit.          \
 187        This allows a single read-compare-cbranch-write sequence to test \
 188        for both decrementer underflow and exceptions.  */               \
 189     union {                                                             \
 190         uint32_t u32;                                                   \
 191         icount_decr_u16 u16;                                            \
 192     } icount_decr;                                                      \
 193     uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
 194                                                                         \
 195     /* from this point: preserved by CPU reset */                       \
 196     /* ice debug support */                                             \
 197     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;            \
 198     int singlestep_enabled;                                             \
 199                                                                         \
 200     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;            \
 201     CPUWatchpoint *watchpoint_hit;                                      \
 202                                                                         \
 203     struct GDBRegisterState *gdb_regs;                                  \
 204                                                                         \
 205     /* Core interrupt code */                                           \
 206     jmp_buf jmp_env;                                                    \
 207     int exception_index;                                                \
 208                                                                         \
 209     CPUState *next_cpu; /* next CPU sharing TB cache */                 \
 210     int cpu_index; /* CPU index (informative) */                        \
 211     uint32_t host_tid; /* host thread ID */                             \
 212     int numa_node; /* NUMA node this cpu is belonging to  */            \
 213     int nr_cores;  /* number of cores within this CPU package */        \
 214     int nr_threads;/* number of threads within this CPU */              \
 215     int running; /* Nonzero if cpu is currently running(usermode).  */  \
 216     int thread_id;                                                      \
 217     /* user data */                                                     \
 218     void *opaque;                                                       \
 219                                                                         \
 220     uint32_t created;                                                   \
 221     uint32_t stop;   /* Stop request */                                 \
 222     uint32_t stopped; /* Artificially stopped */                        \
 223     struct QemuThread *thread;                                          \
 224     struct QemuCond *halt_cond;                                         \
 225     int thread_kicked;                                                  \
 226     struct qemu_work_item *queued_work_first, *queued_work_last;        \
 227     const char *cpu_model_str;                                          \
 228     struct KVMState *kvm_state;                                         \
 229     struct kvm_run *kvm_run;                                            \
 230     int kvm_fd;                                                         \
 231     int kvm_vcpu_dirty;                                                 \
 232     struct KVMCPUState kvm_cpu_state;
 233
 234 #endif