gdbstub.c

   1 /*
   2  * gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "qemu-common.h"
  21 #ifdef CONFIG_USER_ONLY
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <stdarg.h>
  25 #include <string.h>
  26 #include <errno.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "qemu.h"
  31 #else
  32 #include "monitor.h"
  33 #include "qemu-char.h"
  34 #include "sysemu.h"
  35 #include "gdbstub.h"
  36 #endif
  37 #include "qemu-kvm.h"
  38
  39 #define MAX_PACKET_LENGTH 4096
  40
  41 #include "qemu_socket.h"
  42 #include "kvm.h"
  43
  44
  45 enum {
  46     GDB_SIGNAL_0 = 0,
  47     GDB_SIGNAL_INT = 2,
  48     GDB_SIGNAL_TRAP = 5,
  49     GDB_SIGNAL_UNKNOWN = 143
  50 };
  51
  52 #ifdef CONFIG_USER_ONLY
  53
  54 /* Map target signal numbers to GDB protocol signal numbers and vice
  55  * versa.  For user emulation's currently supported systems, we can
  56  * assume most signals are defined.
  57  */
  58
  59 static int gdb_signal_table[] = {
  60     0,
  61     TARGET_SIGHUP,
  62     TARGET_SIGINT,
  63     TARGET_SIGQUIT,
  64     TARGET_SIGILL,
  65     TARGET_SIGTRAP,
  66     TARGET_SIGABRT,
  67     -1, /* SIGEMT */
  68     TARGET_SIGFPE,
  69     TARGET_SIGKILL,
  70     TARGET_SIGBUS,
  71     TARGET_SIGSEGV,
  72     TARGET_SIGSYS,
  73     TARGET_SIGPIPE,
  74     TARGET_SIGALRM,
  75     TARGET_SIGTERM,
  76     TARGET_SIGURG,
  77     TARGET_SIGSTOP,
  78     TARGET_SIGTSTP,
  79     TARGET_SIGCONT,
  80     TARGET_SIGCHLD,
  81     TARGET_SIGTTIN,
  82     TARGET_SIGTTOU,
  83     TARGET_SIGIO,
  84     TARGET_SIGXCPU,
  85     TARGET_SIGXFSZ,
  86     TARGET_SIGVTALRM,
  87     TARGET_SIGPROF,
  88     TARGET_SIGWINCH,
  89     -1, /* SIGLOST */
  90     TARGET_SIGUSR1,
  91     TARGET_SIGUSR2,
  92 #ifdef TARGET_SIGPWR
  93     TARGET_SIGPWR,
  94 #else
  95     -1,
  96 #endif
  97     -1, /* SIGPOLL */
  98     -1,
  99     -1,
 100     -1,
 101     -1,
 102     -1,
 103     -1,
 104     -1,
 105     -1,
 106     -1,
 107     -1,
 108     -1,
 109 #ifdef __SIGRTMIN
 110     __SIGRTMIN + 1,
 111     __SIGRTMIN + 2,
 112     __SIGRTMIN + 3,
 113     __SIGRTMIN + 4,
 114     __SIGRTMIN + 5,
 115     __SIGRTMIN + 6,
 116     __SIGRTMIN + 7,
 117     __SIGRTMIN + 8,
 118     __SIGRTMIN + 9,
 119     __SIGRTMIN + 10,
 120     __SIGRTMIN + 11,
 121     __SIGRTMIN + 12,
 122     __SIGRTMIN + 13,
 123     __SIGRTMIN + 14,
 124     __SIGRTMIN + 15,
 125     __SIGRTMIN + 16,
 126     __SIGRTMIN + 17,
 127     __SIGRTMIN + 18,
 128     __SIGRTMIN + 19,
 129     __SIGRTMIN + 20,
 130     __SIGRTMIN + 21,
 131     __SIGRTMIN + 22,
 132     __SIGRTMIN + 23,
 133     __SIGRTMIN + 24,
 134     __SIGRTMIN + 25,
 135     __SIGRTMIN + 26,
 136     __SIGRTMIN + 27,
 137     __SIGRTMIN + 28,
 138     __SIGRTMIN + 29,
 139     __SIGRTMIN + 30,
 140     __SIGRTMIN + 31,
 141     -1, /* SIGCANCEL */
 142     __SIGRTMIN,
 143     __SIGRTMIN + 32,
 144     __SIGRTMIN + 33,
 145     __SIGRTMIN + 34,
 146     __SIGRTMIN + 35,
 147     __SIGRTMIN + 36,
 148     __SIGRTMIN + 37,
 149     __SIGRTMIN + 38,
 150     __SIGRTMIN + 39,
 151     __SIGRTMIN + 40,
 152     __SIGRTMIN + 41,
 153     __SIGRTMIN + 42,
 154     __SIGRTMIN + 43,
 155     __SIGRTMIN + 44,
 156     __SIGRTMIN + 45,
 157     __SIGRTMIN + 46,
 158     __SIGRTMIN + 47,
 159     __SIGRTMIN + 48,
 160     __SIGRTMIN + 49,
 161     __SIGRTMIN + 50,
 162     __SIGRTMIN + 51,
 163     __SIGRTMIN + 52,
 164     __SIGRTMIN + 53,
 165     __SIGRTMIN + 54,
 166     __SIGRTMIN + 55,
 167     __SIGRTMIN + 56,
 168     __SIGRTMIN + 57,
 169     __SIGRTMIN + 58,
 170     __SIGRTMIN + 59,
 171     __SIGRTMIN + 60,
 172     __SIGRTMIN + 61,
 173     __SIGRTMIN + 62,
 174     __SIGRTMIN + 63,
 175     __SIGRTMIN + 64,
 176     __SIGRTMIN + 65,
 177     __SIGRTMIN + 66,
 178     __SIGRTMIN + 67,
 179     __SIGRTMIN + 68,
 180     __SIGRTMIN + 69,
 181     __SIGRTMIN + 70,
 182     __SIGRTMIN + 71,
 183     __SIGRTMIN + 72,
 184     __SIGRTMIN + 73,
 185     __SIGRTMIN + 74,
 186     __SIGRTMIN + 75,
 187     __SIGRTMIN + 76,
 188     __SIGRTMIN + 77,
 189     __SIGRTMIN + 78,
 190     __SIGRTMIN + 79,
 191     __SIGRTMIN + 80,
 192     __SIGRTMIN + 81,
 193     __SIGRTMIN + 82,
 194     __SIGRTMIN + 83,
 195     __SIGRTMIN + 84,
 196     __SIGRTMIN + 85,
 197     __SIGRTMIN + 86,
 198     __SIGRTMIN + 87,
 199     __SIGRTMIN + 88,
 200     __SIGRTMIN + 89,
 201     __SIGRTMIN + 90,
 202     __SIGRTMIN + 91,
 203     __SIGRTMIN + 92,
 204     __SIGRTMIN + 93,
 205     __SIGRTMIN + 94,
 206     __SIGRTMIN + 95,
 207     -1, /* SIGINFO */
 208     -1, /* UNKNOWN */
 209     -1, /* DEFAULT */
 210     -1,
 211     -1,
 212     -1,
 213     -1,
 214     -1,
 215     -1
 216 #endif
 217 };
 218 #else
 219 /* In system mode we only need SIGINT and SIGTRAP; other signals
 220    are not yet supported.  */
 221
 222 enum {
 223     TARGET_SIGINT = 2,
 224     TARGET_SIGTRAP = 5
 225 };
 226
 227 static int gdb_signal_table[] = {
 228     -1,
 229     -1,
 230     TARGET_SIGINT,
 231     -1,
 232     -1,
 233     TARGET_SIGTRAP
 234 };
 235 #endif
 236
 237 #ifdef CONFIG_USER_ONLY
 238 static int target_signal_to_gdb (int sig)
 239 {
 240     int i;
 241     for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
 242         if (gdb_signal_table[i] == sig)
 243             return i;
 244     return GDB_SIGNAL_UNKNOWN;
 245 }
 246 #endif
 247
 248 static int gdb_signal_to_target (int sig)
 249 {
 250     if (sig < ARRAY_SIZE (gdb_signal_table))
 251         return gdb_signal_table[sig];
 252     else
 253         return -1;
 254 }
 255
 256 //#define DEBUG_GDB
 257
 258 typedef struct GDBRegisterState {
 259     int base_reg;
 260     int num_regs;
 261     gdb_reg_cb get_reg;
 262     gdb_reg_cb set_reg;
 263     const char *xml;
 264     struct GDBRegisterState *next;
 265 } GDBRegisterState;
 266
 267 enum RSState {
 268     RS_INACTIVE,
 269     RS_IDLE,
 270     RS_GETLINE,
 271     RS_CHKSUM1,
 272     RS_CHKSUM2,
 273     RS_SYSCALL,
 274 };
 275 typedef struct GDBState {
 276     CPUState *c_cpu; /* current CPU for step/continue ops */
 277     CPUState *g_cpu; /* current CPU for other ops */
 278     CPUState *query_cpu; /* for q{f|s}ThreadInfo */
 279     enum RSState state; /* parsing state */
 280     char line_buf[MAX_PACKET_LENGTH];
 281     int line_buf_index;
 282     int line_csum;
 283     uint8_t last_packet[MAX_PACKET_LENGTH + 4];
 284     int last_packet_len;
 285     int signal;
 286 #ifdef CONFIG_USER_ONLY
 287     int fd;
 288     int running_state;
 289 #else
 290     CharDriverState *chr;
 291     CharDriverState *mon_chr;
 292 #endif
 293 } GDBState;
 294
 295 /* By default use no IRQs and no timers while single stepping so as to
 296  * make single stepping like an ICE HW step.
 297  */
 298 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
 299
 300 static GDBState *gdbserver_state;
 301
 302 /* This is an ugly hack to cope with both new and old gdb.
 303    If gdb sends qXfer:features:read then assume we're talking to a newish
 304    gdb that understands target descriptions.  */
 305 static int gdb_has_xml;
 306
 307 #ifdef CONFIG_USER_ONLY
 308 /* XXX: This is not thread safe.  Do we care?  */
 309 static int gdbserver_fd = -1;
 310
 311 static int get_char(GDBState *s)
 312 {
 313     uint8_t ch;
 314     int ret;
 315
 316     for(;;) {
 317         ret = recv(s->fd, &ch, 1, 0);
 318         if (ret < 0) {
 319             if (errno == ECONNRESET)
 320                 s->fd = -1;
 321             if (errno != EINTR && errno != EAGAIN)
 322                 return -1;
 323         } else if (ret == 0) {
 324             close(s->fd);
 325             s->fd = -1;
 326             return -1;
 327         } else {
 328             break;
 329         }
 330     }
 331     return ch;
 332 }
 333 #endif
 334
 335 static gdb_syscall_complete_cb gdb_current_syscall_cb;
 336
 337 static enum {
 338     GDB_SYS_UNKNOWN,
 339     GDB_SYS_ENABLED,
 340     GDB_SYS_DISABLED,
 341 } gdb_syscall_mode;
 342
 343 /* If gdb is connected when the first semihosting syscall occurs then use
 344    remote gdb syscalls.  Otherwise use native file IO.  */
 345 int use_gdb_syscalls(void)
 346 {
 347     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
 348         gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
 349                                             : GDB_SYS_DISABLED);
 350     }
 351     return gdb_syscall_mode == GDB_SYS_ENABLED;
 352 }
 353
 354 /* Resume execution.  */
 355 static inline void gdb_continue(GDBState *s)
 356 {
 357 #ifdef CONFIG_USER_ONLY
 358     s->running_state = 1;
 359 #else
 360     vm_start();
 361 #endif
 362 }
 363
 364 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
 365 {
 366 #ifdef CONFIG_USER_ONLY
 367     int ret;
 368
 369     while (len > 0) {
 370         ret = send(s->fd, buf, len, 0);
 371         if (ret < 0) {
 372             if (errno != EINTR && errno != EAGAIN)
 373                 return;
 374         } else {
 375             buf += ret;
 376             len -= ret;
 377         }
 378     }
 379 #else
 380     qemu_chr_write(s->chr, buf, len);
 381 #endif
 382 }
 383
 384 static inline int fromhex(int v)
 385 {
 386     if (v >= '0' && v <= '9')
 387         return v - '0';
 388     else if (v >= 'A' && v <= 'F')
 389         return v - 'A' + 10;
 390     else if (v >= 'a' && v <= 'f')
 391         return v - 'a' + 10;
 392     else
 393         return 0;
 394 }
 395
 396 static inline int tohex(int v)
 397 {
 398     if (v < 10)
 399         return v + '0';
 400     else
 401         return v - 10 + 'a';
 402 }
 403
 404 static void memtohex(char *buf, const uint8_t *mem, int len)
 405 {
 406     int i, c;
 407     char *q;
 408     q = buf;
 409     for(i = 0; i < len; i++) {
 410         c = mem[i];
 411         *q++ = tohex(c >> 4);
 412         *q++ = tohex(c & 0xf);
 413     }
 414     *q = '\0';
 415 }
 416
 417 static void hextomem(uint8_t *mem, const char *buf, int len)
 418 {
 419     int i;
 420
 421     for(i = 0; i < len; i++) {
 422         mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
 423         buf += 2;
 424     }
 425 }
 426
 427 /* return -1 if error, 0 if OK */
 428 static int put_packet_binary(GDBState *s, const char *buf, int len)
 429 {
 430     int csum, i;
 431     uint8_t *p;
 432
 433     for(;;) {
 434         p = s->last_packet;
 435         *(p++) = '$';
 436         memcpy(p, buf, len);
 437         p += len;
 438         csum = 0;
 439         for(i = 0; i < len; i++) {
 440             csum += buf[i];
 441         }
 442         *(p++) = '#';
 443         *(p++) = tohex((csum >> 4) & 0xf);
 444         *(p++) = tohex((csum) & 0xf);
 445
 446         s->last_packet_len = p - s->last_packet;
 447         put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
 448
 449 #ifdef CONFIG_USER_ONLY
 450         i = get_char(s);
 451         if (i < 0)
 452             return -1;
 453         if (i == '+')
 454             break;
 455 #else
 456         break;
 457 #endif
 458     }
 459     return 0;
 460 }
 461
 462 /* return -1 if error, 0 if OK */
 463 static int put_packet(GDBState *s, const char *buf)
 464 {
 465 #ifdef DEBUG_GDB
 466     printf("reply='%s'\n", buf);
 467 #endif
 468
 469     return put_packet_binary(s, buf, strlen(buf));
 470 }
 471
 472 /* The GDB remote protocol transfers values in target byte order.  This means
 473    we can use the raw memory access routines to access the value buffer.
 474    Conveniently, these also handle the case where the buffer is mis-aligned.
 475  */
 476 #define GET_REG8(val) do { \
 477     stb_p(mem_buf, val); \
 478     return 1; \
 479     } while(0)
 480 #define GET_REG16(val) do { \
 481     stw_p(mem_buf, val); \
 482     return 2; \
 483     } while(0)
 484 #define GET_REG32(val) do { \
 485     stl_p(mem_buf, val); \
 486     return 4; \
 487     } while(0)
 488 #define GET_REG64(val) do { \
 489     stq_p(mem_buf, val); \
 490     return 8; \
 491     } while(0)
 492
 493 #if TARGET_LONG_BITS == 64
 494 #define GET_REGL(val) GET_REG64(val)
 495 #define ldtul_p(addr) ldq_p(addr)
 496 #else
 497 #define GET_REGL(val) GET_REG32(val)
 498 #define ldtul_p(addr) ldl_p(addr)
 499 #endif
 500
 501 #if defined(TARGET_I386)
 502
 503 #ifdef TARGET_X86_64
 504 static const int gpr_map[16] = {
 505     R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
 506     8, 9, 10, 11, 12, 13, 14, 15
 507 };
 508 #else
 509 #define gpr_map gpr_map32
 510 #endif
 511 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 512
 513 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
 514
 515 #define IDX_IP_REG      CPU_NB_REGS
 516 #define IDX_FLAGS_REG   (IDX_IP_REG + 1)
 517 #define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
 518 #define IDX_FP_REGS     (IDX_SEG_REGS + 6)
 519 #define IDX_XMM_REGS    (IDX_FP_REGS + 16)
 520 #define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)
 521
 522 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 523 {
 524     if (n < CPU_NB_REGS) {
 525         if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 526             GET_REG64(env->regs[gpr_map[n]]);
 527         } else if (n < CPU_NB_REGS32) {
 528             GET_REG32(env->regs[gpr_map32[n]]);
 529         }
 530     } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 531 #ifdef USE_X86LDOUBLE
 532         /* FIXME: byteswap float values - after fixing fpregs layout. */
 533         memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
 534 #else
 535         memset(mem_buf, 0, 10);
 536 #endif
 537         return 10;
 538     } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 539         n -= IDX_XMM_REGS;
 540         if (n < CPU_NB_REGS32 ||
 541             (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
 542             stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
 543             stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
 544             return 16;
 545         }
 546     } else {
 547         switch (n) {
 548         case IDX_IP_REG:
 549             if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 550                 GET_REG64(env->eip);
 551             } else {
 552                 GET_REG32(env->eip);
 553             }
 554         case IDX_FLAGS_REG: GET_REG32(env->eflags);
 555
 556         case IDX_SEG_REGS:     GET_REG32(env->segs[R_CS].selector);
 557         case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
 558         case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
 559         case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
 560         case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
 561         case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
 562
 563         case IDX_FP_REGS + 8:  GET_REG32(env->fpuc);
 564         case IDX_FP_REGS + 9:  GET_REG32((env->fpus & ~0x3800) |
 565                                          (env->fpstt & 0x7) << 11);
 566         case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
 567         case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
 568         case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
 569         case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
 570         case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
 571         case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
 572
 573         case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
 574         }
 575     }
 576     return 0;
 577 }
 578
 579 static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
 580 {
 581     uint16_t selector = ldl_p(mem_buf);
 582
 583     if (selector != env->segs[sreg].selector) {
 584 #if defined(CONFIG_USER_ONLY)
 585         cpu_x86_load_seg(env, sreg, selector);
 586 #else
 587         unsigned int limit, flags;
 588         target_ulong base;
 589
 590         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 591             base = selector << 4;
 592             limit = 0xffff;
 593             flags = 0;
 594         } else {
 595             if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
 596                 return 4;
 597         }
 598         cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
 599 #endif
 600     }
 601     return 4;
 602 }
 603
 604 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 605 {
 606     uint32_t tmp;
 607
 608     if (n < CPU_NB_REGS) {
 609         if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 610             env->regs[gpr_map[n]] = ldtul_p(mem_buf);
 611             return sizeof(target_ulong);
 612         } else if (n < CPU_NB_REGS32) {
 613             n = gpr_map32[n];
 614             env->regs[n] &= ~0xffffffffUL;
 615             env->regs[n] |= (uint32_t)ldl_p(mem_buf);
 616             return 4;
 617         }
 618     } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 619 #ifdef USE_X86LDOUBLE
 620         /* FIXME: byteswap float values - after fixing fpregs layout. */
 621         memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
 622 #endif
 623         return 10;
 624     } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 625         n -= IDX_XMM_REGS;
 626         if (n < CPU_NB_REGS32 ||
 627             (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
 628             env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
 629             env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
 630             return 16;
 631         }
 632     } else {
 633         switch (n) {
 634         case IDX_IP_REG:
 635             if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 636                 env->eip = ldq_p(mem_buf);
 637                 return 8;
 638             } else {
 639                 env->eip &= ~0xffffffffUL;
 640                 env->eip |= (uint32_t)ldl_p(mem_buf);
 641                 return 4;
 642             }
 643         case IDX_FLAGS_REG:
 644             env->eflags = ldl_p(mem_buf);
 645             return 4;
 646
 647         case IDX_SEG_REGS:     return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
 648         case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
 649         case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
 650         case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
 651         case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
 652         case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
 653
 654         case IDX_FP_REGS + 8:
 655             env->fpuc = ldl_p(mem_buf);
 656             return 4;
 657         case IDX_FP_REGS + 9:
 658             tmp = ldl_p(mem_buf);
 659             env->fpstt = (tmp >> 11) & 7;
 660             env->fpus = tmp & ~0x3800;
 661             return 4;
 662         case IDX_FP_REGS + 10: /* ftag */  return 4;
 663         case IDX_FP_REGS + 11: /* fiseg */ return 4;
 664         case IDX_FP_REGS + 12: /* fioff */ return 4;
 665         case IDX_FP_REGS + 13: /* foseg */ return 4;
 666         case IDX_FP_REGS + 14: /* fooff */ return 4;
 667         case IDX_FP_REGS + 15: /* fop */   return 4;
 668
 669         case IDX_MXCSR_REG:
 670             env->mxcsr = ldl_p(mem_buf);
 671             return 4;
 672         }
 673     }
 674     /* Unrecognised register.  */
 675     return 0;
 676 }
 677
 678 #elif defined (TARGET_PPC)
 679
 680 /* Old gdb always expects FP registers.  Newer (xml-aware) gdb only
 681    expects whatever the target description contains.  Due to a
 682    historical mishap the FP registers appear in between core integer
 683    regs and PC, MSR, CR, and so forth.  We hack round this by giving the
 684    FP regs zero size when talking to a newer gdb.  */
 685 #define NUM_CORE_REGS 71
 686 #if defined (TARGET_PPC64)
 687 #define GDB_CORE_XML "power64-core.xml"
 688 #else
 689 #define GDB_CORE_XML "power-core.xml"
 690 #endif
 691
 692 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 693 {
 694     if (n < 32) {
 695         /* gprs */
 696         GET_REGL(env->gpr[n]);
 697     } else if (n < 64) {
 698         /* fprs */
 699         if (gdb_has_xml)
 700             return 0;
 701         stfq_p(mem_buf, env->fpr[n-32]);
 702         return 8;
 703     } else {
 704         switch (n) {
 705         case 64: GET_REGL(env->nip);
 706         case 65: GET_REGL(env->msr);
 707         case 66:
 708             {
 709                 uint32_t cr = 0;
 710                 int i;
 711                 for (i = 0; i < 8; i++)
 712                     cr |= env->crf[i] << (32 - ((i + 1) * 4));
 713                 GET_REG32(cr);
 714             }
 715         case 67: GET_REGL(env->lr);
 716         case 68: GET_REGL(env->ctr);
 717         case 69: GET_REGL(env->xer);
 718         case 70:
 719             {
 720                 if (gdb_has_xml)
 721                     return 0;
 722                 GET_REG32(0); /* fpscr */
 723             }
 724         }
 725     }
 726     return 0;
 727 }
 728
 729 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 730 {
 731     if (n < 32) {
 732         /* gprs */
 733         env->gpr[n] = ldtul_p(mem_buf);
 734         return sizeof(target_ulong);
 735     } else if (n < 64) {
 736         /* fprs */
 737         if (gdb_has_xml)
 738             return 0;
 739         env->fpr[n-32] = ldfq_p(mem_buf);
 740         return 8;
 741     } else {
 742         switch (n) {
 743         case 64:
 744             env->nip = ldtul_p(mem_buf);
 745             return sizeof(target_ulong);
 746         case 65:
 747             ppc_store_msr(env, ldtul_p(mem_buf));
 748             return sizeof(target_ulong);
 749         case 66:
 750             {
 751                 uint32_t cr = ldl_p(mem_buf);
 752                 int i;
 753                 for (i = 0; i < 8; i++)
 754                     env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
 755                 return 4;
 756             }
 757         case 67:
 758             env->lr = ldtul_p(mem_buf);
 759             return sizeof(target_ulong);
 760         case 68:
 761             env->ctr = ldtul_p(mem_buf);
 762             return sizeof(target_ulong);
 763         case 69:
 764             env->xer = ldtul_p(mem_buf);
 765             return sizeof(target_ulong);
 766         case 70:
 767             /* fpscr */
 768             if (gdb_has_xml)
 769                 return 0;
 770             return 4;
 771         }
 772     }
 773     return 0;
 774 }
 775
 776 #elif defined (TARGET_SPARC)
 777
 778 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
 779 #define NUM_CORE_REGS 86
 780 #else
 781 #define NUM_CORE_REGS 72
 782 #endif
 783
 784 #ifdef TARGET_ABI32
 785 #define GET_REGA(val) GET_REG32(val)
 786 #else
 787 #define GET_REGA(val) GET_REGL(val)
 788 #endif
 789
 790 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 791 {
 792     if (n < 8) {
 793         /* g0..g7 */
 794         GET_REGA(env->gregs[n]);
 795     }
 796     if (n < 32) {
 797         /* register window */
 798         GET_REGA(env->regwptr[n - 8]);
 799     }
 800 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 801     if (n < 64) {
 802         /* fprs */
 803         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 804     }
 805     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 806     switch (n) {
 807     case 64: GET_REGA(env->y);
 808     case 65: GET_REGA(GET_PSR(env));
 809     case 66: GET_REGA(env->wim);
 810     case 67: GET_REGA(env->tbr);
 811     case 68: GET_REGA(env->pc);
 812     case 69: GET_REGA(env->npc);
 813     case 70: GET_REGA(env->fsr);
 814     case 71: GET_REGA(0); /* csr */
 815     default: GET_REGA(0);
 816     }
 817 #else
 818     if (n < 64) {
 819         /* f0-f31 */
 820         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 821     }
 822     if (n < 80) {
 823         /* f32-f62 (double width, even numbers only) */
 824         uint64_t val;
 825
 826         val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
 827         val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
 828         GET_REG64(val);
 829     }
 830     switch (n) {
 831     case 80: GET_REGL(env->pc);
 832     case 81: GET_REGL(env->npc);
 833     case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
 834                            ((env->asi & 0xff) << 24) |
 835                            ((env->pstate & 0xfff) << 8) |
 836                            GET_CWP64(env));
 837     case 83: GET_REGL(env->fsr);
 838     case 84: GET_REGL(env->fprs);
 839     case 85: GET_REGL(env->y);
 840     }
 841 #endif
 842     return 0;
 843 }
 844
 845 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 846 {
 847 #if defined(TARGET_ABI32)
 848     abi_ulong tmp;
 849
 850     tmp = ldl_p(mem_buf);
 851 #else
 852     target_ulong tmp;
 853
 854     tmp = ldtul_p(mem_buf);
 855 #endif
 856
 857     if (n < 8) {
 858         /* g0..g7 */
 859         env->gregs[n] = tmp;
 860     } else if (n < 32) {
 861         /* register window */
 862         env->regwptr[n - 8] = tmp;
 863     }
 864 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 865     else if (n < 64) {
 866         /* fprs */
 867         *((uint32_t *)&env->fpr[n - 32]) = tmp;
 868     } else {
 869         /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 870         switch (n) {
 871         case 64: env->y = tmp; break;
 872         case 65: PUT_PSR(env, tmp); break;
 873         case 66: env->wim = tmp; break;
 874         case 67: env->tbr = tmp; break;
 875         case 68: env->pc = tmp; break;
 876         case 69: env->npc = tmp; break;
 877         case 70: env->fsr = tmp; break;
 878         default: return 0;
 879         }
 880     }
 881     return 4;
 882 #else
 883     else if (n < 64) {
 884         /* f0-f31 */
 885         env->fpr[n] = ldfl_p(mem_buf);
 886         return 4;
 887     } else if (n < 80) {
 888         /* f32-f62 (double width, even numbers only) */
 889         *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
 890         *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
 891     } else {
 892         switch (n) {
 893         case 80: env->pc = tmp; break;
 894         case 81: env->npc = tmp; break;
 895         case 82:
 896             PUT_CCR(env, tmp >> 32);
 897             env->asi = (tmp >> 24) & 0xff;
 898             env->pstate = (tmp >> 8) & 0xfff;
 899             PUT_CWP64(env, tmp & 0xff);
 900             break;
 901         case 83: env->fsr = tmp; break;
 902         case 84: env->fprs = tmp; break;
 903         case 85: env->y = tmp; break;
 904         default: return 0;
 905         }
 906     }
 907     return 8;
 908 #endif
 909 }
 910 #elif defined (TARGET_ARM)
 911
 912 /* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
 913    whatever the target description contains.  Due to a historical mishap
 914    the FPA registers appear in between core integer regs and the CPSR.
 915    We hack round this by giving the FPA regs zero size when talking to a
 916    newer gdb.  */
 917 #define NUM_CORE_REGS 26
 918 #define GDB_CORE_XML "arm-core.xml"
 919
 920 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 921 {
 922     if (n < 16) {
 923         /* Core integer register.  */
 924         GET_REG32(env->regs[n]);
 925     }
 926     if (n < 24) {
 927         /* FPA registers.  */
 928         if (gdb_has_xml)
 929             return 0;
 930         memset(mem_buf, 0, 12);
 931         return 12;
 932     }
 933     switch (n) {
 934     case 24:
 935         /* FPA status register.  */
 936         if (gdb_has_xml)
 937             return 0;
 938         GET_REG32(0);
 939     case 25:
 940         /* CPSR */
 941         GET_REG32(cpsr_read(env));
 942     }
 943     /* Unknown register.  */
 944     return 0;
 945 }
 946
 947 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 948 {
 949     uint32_t tmp;
 950
 951     tmp = ldl_p(mem_buf);
 952
 953     /* Mask out low bit of PC to workaround gdb bugs.  This will probably
 954        cause problems if we ever implement the Jazelle DBX extensions.  */
 955     if (n == 15)
 956         tmp &= ~1;
 957
 958     if (n < 16) {
 959         /* Core integer register.  */
 960         env->regs[n] = tmp;
 961         return 4;
 962     }
 963     if (n < 24) { /* 16-23 */
 964         /* FPA registers (ignored).  */
 965         if (gdb_has_xml)
 966             return 0;
 967         return 12;
 968     }
 969     switch (n) {
 970     case 24:
 971         /* FPA status register (ignored).  */
 972         if (gdb_has_xml)
 973             return 0;
 974         return 4;
 975     case 25:
 976         /* CPSR */
 977         cpsr_write (env, tmp, 0xffffffff);
 978         return 4;
 979     }
 980     /* Unknown register.  */
 981     return 0;
 982 }
 983
 984 #elif defined (TARGET_M68K)
 985
 986 #define NUM_CORE_REGS 18
 987
 988 #define GDB_CORE_XML "cf-core.xml"
 989
 990 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 991 {
 992     if (n < 8) {
 993         /* D0-D7 */
 994         GET_REG32(env->dregs[n]);
 995     } else if (n < 16) {
 996         /* A0-A7 */
 997         GET_REG32(env->aregs[n - 8]);
 998     } else {
 999         switch (n) {
1000         case 16: GET_REG32(env->sr);
1001         case 17: GET_REG32(env->pc);
1002         }
1003     }
1004     /* FP registers not included here because they vary between
1005        ColdFire and m68k.  Use XML bits for these.  */
1006     return 0;
1007 }
1008
1009 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1010 {
1011     uint32_t tmp;
1012
1013     tmp = ldl_p(mem_buf);
1014
1015     if (n < 8) {
1016         /* D0-D7 */
1017         env->dregs[n] = tmp;
1018     } else if (n < 8) {
1019         /* A0-A7 */
1020         env->aregs[n - 8] = tmp;
1021     } else {
1022         switch (n) {
1023         case 16: env->sr = tmp; break;
1024         case 17: env->pc = tmp; break;
1025         default: return 0;
1026         }
1027     }
1028     return 4;
1029 }
1030 #elif defined (TARGET_MIPS)
1031
1032 #define NUM_CORE_REGS 73
1033
1034 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1035 {
1036     if (n < 32) {
1037         GET_REGL(env->active_tc.gpr[n]);
1038     }
1039     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1040         if (n >= 38 && n < 70) {
1041             if (env->CP0_Status & (1 << CP0St_FR))
1042                 GET_REGL(env->active_fpu.fpr[n - 38].d);
1043             else
1044                 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1045         }
1046         switch (n) {
1047         case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1048         case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1049         }
1050     }
1051     switch (n) {
1052     case 32: GET_REGL((int32_t)env->CP0_Status);
1053     case 33: GET_REGL(env->active_tc.LO[0]);
1054     case 34: GET_REGL(env->active_tc.HI[0]);
1055     case 35: GET_REGL(env->CP0_BadVAddr);
1056     case 36: GET_REGL((int32_t)env->CP0_Cause);
1057     case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
1058     case 72: GET_REGL(0); /* fp */
1059     case 89: GET_REGL((int32_t)env->CP0_PRid);
1060     }
1061     if (n >= 73 && n <= 88) {
1062         /* 16 embedded regs.  */
1063         GET_REGL(0);
1064     }
1065
1066     return 0;
1067 }
1068
1069 /* convert MIPS rounding mode in FCR31 to IEEE library */
1070 static unsigned int ieee_rm[] =
1071   {
1072     float_round_nearest_even,
1073     float_round_to_zero,
1074     float_round_up,
1075     float_round_down
1076   };
1077 #define RESTORE_ROUNDING_MODE \
1078     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1079
1080 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1081 {
1082     target_ulong tmp;
1083
1084     tmp = ldtul_p(mem_buf);
1085
1086     if (n < 32) {
1087         env->active_tc.gpr[n] = tmp;
1088         return sizeof(target_ulong);
1089     }
1090     if (env->CP0_Config1 & (1 << CP0C1_FP)
1091             && n >= 38 && n < 73) {
1092         if (n < 70) {
1093             if (env->CP0_Status & (1 << CP0St_FR))
1094               env->active_fpu.fpr[n - 38].d = tmp;
1095             else
1096               env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1097         }
1098         switch (n) {
1099         case 70:
1100             env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1101             /* set rounding mode */
1102             RESTORE_ROUNDING_MODE;
1103 #ifndef CONFIG_SOFTFLOAT
1104             /* no floating point exception for native float */
1105             SET_FP_ENABLE(env->active_fpu.fcr31, 0);
1106 #endif
1107             break;
1108         case 71: env->active_fpu.fcr0 = tmp; break;
1109         }
1110         return sizeof(target_ulong);
1111     }
1112     switch (n) {
1113     case 32: env->CP0_Status = tmp; break;
1114     case 33: env->active_tc.LO[0] = tmp; break;
1115     case 34: env->active_tc.HI[0] = tmp; break;
1116     case 35: env->CP0_BadVAddr = tmp; break;
1117     case 36: env->CP0_Cause = tmp; break;
1118     case 37:
1119         env->active_tc.PC = tmp & ~(target_ulong)1;
1120         if (tmp & 1) {
1121             env->hflags |= MIPS_HFLAG_M16;
1122         } else {
1123             env->hflags &= ~(MIPS_HFLAG_M16);
1124         }
1125         break;
1126     case 72: /* fp, ignored */ break;
1127     default:
1128         if (n > 89)
1129             return 0;
1130         /* Other registers are readonly.  Ignore writes.  */
1131         break;
1132     }
1133
1134     return sizeof(target_ulong);
1135 }
1136 #elif defined (TARGET_SH4)
1137
1138 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1139 /* FIXME: We should use XML for this.  */
1140
1141 #define NUM_CORE_REGS 59
1142
1143 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1144 {
1145     if (n < 8) {
1146         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1147             GET_REGL(env->gregs[n + 16]);
1148         } else {
1149             GET_REGL(env->gregs[n]);
1150         }
1151     } else if (n < 16) {
1152         GET_REGL(env->gregs[n - 8]);
1153     } else if (n >= 25 && n < 41) {
1154         GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1155     } else if (n >= 43 && n < 51) {
1156         GET_REGL(env->gregs[n - 43]);
1157     } else if (n >= 51 && n < 59) {
1158         GET_REGL(env->gregs[n - (51 - 16)]);
1159     }
1160     switch (n) {
1161     case 16: GET_REGL(env->pc);
1162     case 17: GET_REGL(env->pr);
1163     case 18: GET_REGL(env->gbr);
1164     case 19: GET_REGL(env->vbr);
1165     case 20: GET_REGL(env->mach);
1166     case 21: GET_REGL(env->macl);
1167     case 22: GET_REGL(env->sr);
1168     case 23: GET_REGL(env->fpul);
1169     case 24: GET_REGL(env->fpscr);
1170     case 41: GET_REGL(env->ssr);
1171     case 42: GET_REGL(env->spc);
1172     }
1173
1174     return 0;
1175 }
1176
1177 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1178 {
1179     uint32_t tmp;
1180
1181     tmp = ldl_p(mem_buf);
1182
1183     if (n < 8) {
1184         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1185             env->gregs[n + 16] = tmp;
1186         } else {
1187             env->gregs[n] = tmp;
1188         }
1189         return 4;
1190     } else if (n < 16) {
1191         env->gregs[n - 8] = tmp;
1192         return 4;
1193     } else if (n >= 25 && n < 41) {
1194         env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1195     } else if (n >= 43 && n < 51) {
1196         env->gregs[n - 43] = tmp;
1197         return 4;
1198     } else if (n >= 51 && n < 59) {
1199         env->gregs[n - (51 - 16)] = tmp;
1200         return 4;
1201     }
1202     switch (n) {
1203     case 16: env->pc = tmp;
1204     case 17: env->pr = tmp;
1205     case 18: env->gbr = tmp;
1206     case 19: env->vbr = tmp;
1207     case 20: env->mach = tmp;
1208     case 21: env->macl = tmp;
1209     case 22: env->sr = tmp;
1210     case 23: env->fpul = tmp;
1211     case 24: env->fpscr = tmp;
1212     case 41: env->ssr = tmp;
1213     case 42: env->spc = tmp;
1214     default: return 0;
1215     }
1216
1217     return 4;
1218 }
1219 #elif defined (TARGET_MICROBLAZE)
1220
1221 #define NUM_CORE_REGS (32 + 5)
1222
1223 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1224 {
1225     if (n < 32) {
1226         GET_REG32(env->regs[n]);
1227     } else {
1228         GET_REG32(env->sregs[n - 32]);
1229     }
1230     return 0;
1231 }
1232
1233 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1234 {
1235     uint32_t tmp;
1236
1237     if (n > NUM_CORE_REGS)
1238         return 0;
1239
1240     tmp = ldl_p(mem_buf);
1241
1242     if (n < 32) {
1243         env->regs[n] = tmp;
1244     } else {
1245         env->sregs[n - 32] = tmp;
1246     }
1247     return 4;
1248 }
1249 #elif defined (TARGET_CRIS)
1250
1251 #define NUM_CORE_REGS 49
1252
1253 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1254 {
1255     uint8_t srs;
1256
1257     srs = env->pregs[PR_SRS];
1258     if (n < 16) {
1259         GET_REG32(env->regs[n]);
1260     }
1261
1262     if (n >= 21 && n < 32) {
1263         GET_REG32(env->pregs[n - 16]);
1264     }
1265     if (n >= 33 && n < 49) {
1266         GET_REG32(env->sregs[srs][n - 33]);
1267     }
1268     switch (n) {
1269     case 16: GET_REG8(env->pregs[0]);
1270     case 17: GET_REG8(env->pregs[1]);
1271     case 18: GET_REG32(env->pregs[2]);
1272     case 19: GET_REG8(srs);
1273     case 20: GET_REG16(env->pregs[4]);
1274     case 32: GET_REG32(env->pc);
1275     }
1276
1277     return 0;
1278 }
1279
1280 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1281 {
1282     uint32_t tmp;
1283
1284     if (n > 49)
1285         return 0;
1286
1287     tmp = ldl_p(mem_buf);
1288
1289     if (n < 16) {
1290         env->regs[n] = tmp;
1291     }
1292
1293     if (n >= 21 && n < 32) {
1294         env->pregs[n - 16] = tmp;
1295     }
1296
1297     /* FIXME: Should support function regs be writable?  */
1298     switch (n) {
1299     case 16: return 1;
1300     case 17: return 1;
1301     case 18: env->pregs[PR_PID] = tmp; break;
1302     case 19: return 1;
1303     case 20: return 2;
1304     case 32: env->pc = tmp; break;
1305     }
1306
1307     return 4;
1308 }
1309 #elif defined (TARGET_ALPHA)
1310
1311 #define NUM_CORE_REGS 65
1312
1313 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1314 {
1315     if (n < 31) {
1316        GET_REGL(env->ir[n]);
1317     }
1318     else if (n == 31) {
1319        GET_REGL(0);
1320     }
1321     else if (n<63) {
1322        uint64_t val;
1323
1324        val = *((uint64_t *)&env->fir[n-32]);
1325        GET_REGL(val);
1326     }
1327     else if (n==63) {
1328        GET_REGL(env->fpcr);
1329     }
1330     else if (n==64) {
1331        GET_REGL(env->pc);
1332     }
1333     else {
1334        GET_REGL(0);
1335     }
1336
1337     return 0;
1338 }
1339
1340 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1341 {
1342     target_ulong tmp;
1343     tmp = ldtul_p(mem_buf);
1344
1345     if (n < 31) {
1346         env->ir[n] = tmp;
1347     }
1348
1349     if (n > 31 && n < 63) {
1350         env->fir[n - 32] = ldfl_p(mem_buf);
1351     }
1352
1353     if (n == 64 ) {
1354        env->pc=tmp;
1355     }
1356
1357     return 8;
1358 }
1359 #elif defined (TARGET_S390X)
1360
1361 #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1362
1363 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1364 {
1365     switch (n) {
1366         case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
1367         case S390_PSWA_REGNUM: GET_REGL(env->psw.addr); break;
1368         case S390_R0_REGNUM ... S390_R15_REGNUM:
1369             GET_REGL(env->regs[n-S390_R0_REGNUM]); break;
1370         case S390_A0_REGNUM ... S390_A15_REGNUM:
1371             GET_REG32(env->aregs[n-S390_A0_REGNUM]); break;
1372         case S390_FPC_REGNUM: GET_REG32(env->fpc); break;
1373         case S390_F0_REGNUM ... S390_F15_REGNUM:
1374             /* XXX */
1375             break;
1376         case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
1377         case S390_CC_REGNUM: GET_REG32(env->cc); break;
1378     }
1379
1380     return 0;
1381 }
1382
1383 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1384 {
1385     target_ulong tmpl;
1386     uint32_t tmp32;
1387     int r = 8;
1388     tmpl = ldtul_p(mem_buf);
1389     tmp32 = ldl_p(mem_buf);
1390
1391     switch (n) {
1392         case S390_PSWM_REGNUM: env->psw.mask = tmpl; break;
1393         case S390_PSWA_REGNUM: env->psw.addr = tmpl; break;
1394         case S390_R0_REGNUM ... S390_R15_REGNUM:
1395             env->regs[n-S390_R0_REGNUM] = tmpl; break;
1396         case S390_A0_REGNUM ... S390_A15_REGNUM:
1397             env->aregs[n-S390_A0_REGNUM] = tmp32; r=4; break;
1398         case S390_FPC_REGNUM: env->fpc = tmp32; r=4; break;
1399         case S390_F0_REGNUM ... S390_F15_REGNUM:
1400             /* XXX */
1401             break;
1402         case S390_PC_REGNUM: env->psw.addr = tmpl; break;
1403         case S390_CC_REGNUM: env->cc = tmp32; r=4; break;
1404     }
1405
1406     return r;
1407 }
1408 #else
1409
1410 #define NUM_CORE_REGS 0
1411
1412 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1413 {
1414     return 0;
1415 }
1416
1417 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1418 {
1419     return 0;
1420 }
1421
1422 #endif
1423
1424 static int num_g_regs = NUM_CORE_REGS;
1425
1426 #ifdef GDB_CORE_XML
1427 /* Encode data using the encoding for 'x' packets.  */
1428 static int memtox(char *buf, const char *mem, int len)
1429 {
1430     char *p = buf;
1431     char c;
1432
1433     while (len--) {
1434         c = *(mem++);
1435         switch (c) {
1436         case '#': case '$': case '*': case '}':
1437             *(p++) = '}';
1438             *(p++) = c ^ 0x20;
1439             break;
1440         default:
1441             *(p++) = c;
1442             break;
1443         }
1444     }
1445     return p - buf;
1446 }
1447
1448 static const char *get_feature_xml(const char *p, const char **newp)
1449 {
1450     extern const char *const xml_builtin[][2];
1451     size_t len;
1452     int i;
1453     const char *name;
1454     static char target_xml[1024];
1455
1456     len = 0;
1457     while (p[len] && p[len] != ':')
1458         len++;
1459     *newp = p + len;
1460
1461     name = NULL;
1462     if (strncmp(p, "target.xml", len) == 0) {
1463         /* Generate the XML description for this CPU.  */
1464         if (!target_xml[0]) {
1465             GDBRegisterState *r;
1466
1467             snprintf(target_xml, sizeof(target_xml),
1468                      "<?xml version=\"1.0\"?>"
1469                      "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1470                      "<target>"
1471                      "<xi:include href=\"%s\"/>",
1472                      GDB_CORE_XML);
1473
1474             for (r = first_cpu->gdb_regs; r; r = r->next) {
1475                 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1476                 pstrcat(target_xml, sizeof(target_xml), r->xml);
1477                 pstrcat(target_xml, sizeof(target_xml), "\"/>");
1478             }
1479             pstrcat(target_xml, sizeof(target_xml), "</target>");
1480         }
1481         return target_xml;
1482     }
1483     for (i = 0; ; i++) {
1484         name = xml_builtin[i][0];
1485         if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1486             break;
1487     }
1488     return name ? xml_builtin[i][1] : NULL;
1489 }
1490 #endif
1491
1492 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1493 {
1494     GDBRegisterState *r;
1495
1496     if (reg < NUM_CORE_REGS)
1497         return cpu_gdb_read_register(env, mem_buf, reg);
1498
1499     for (r = env->gdb_regs; r; r = r->next) {
1500         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1501             return r->get_reg(env, mem_buf, reg - r->base_reg);
1502         }
1503     }
1504     return 0;
1505 }
1506
1507 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1508 {
1509     GDBRegisterState *r;
1510
1511     if (reg < NUM_CORE_REGS)
1512         return cpu_gdb_write_register(env, mem_buf, reg);
1513
1514     for (r = env->gdb_regs; r; r = r->next) {
1515         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1516             return r->set_reg(env, mem_buf, reg - r->base_reg);
1517         }
1518     }
1519     return 0;
1520 }
1521
1522 /* Register a supplemental set of CPU registers.  If g_pos is nonzero it
1523    specifies the first register number and these registers are included in
1524    a standard "g" packet.  Direction is relative to gdb, i.e. get_reg is
1525    gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1526  */
1527
1528 void gdb_register_coprocessor(CPUState * env,
1529                              gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1530                              int num_regs, const char *xml, int g_pos)
1531 {
1532     GDBRegisterState *s;
1533     GDBRegisterState **p;
1534     static int last_reg = NUM_CORE_REGS;
1535
1536     s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1537     s->base_reg = last_reg;
1538     s->num_regs = num_regs;
1539     s->get_reg = get_reg;
1540     s->set_reg = set_reg;
1541     s->xml = xml;
1542     p = &env->gdb_regs;
1543     while (*p) {
1544         /* Check for duplicates.  */
1545         if (strcmp((*p)->xml, xml) == 0)
1546             return;
1547         p = &(*p)->next;
1548     }
1549     /* Add to end of list.  */
1550     last_reg += num_regs;
1551     *p = s;
1552     if (g_pos) {
1553         if (g_pos != s->base_reg) {
1554             fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1555                     "Expected %d got %d\n", xml, g_pos, s->base_reg);
1556         } else {
1557             num_g_regs = last_reg;
1558         }
1559     }
1560 }
1561
1562 #ifndef CONFIG_USER_ONLY
1563 static const int xlat_gdb_type[] = {
1564     [GDB_WATCHPOINT_WRITE]  = BP_GDB | BP_MEM_WRITE,
1565     [GDB_WATCHPOINT_READ]   = BP_GDB | BP_MEM_READ,
1566     [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1567 };
1568 #endif
1569
1570 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1571 {
1572     CPUState *env;
1573     int err = 0;
1574
1575     if (kvm_enabled())
1576         return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1577
1578     switch (type) {
1579     case GDB_BREAKPOINT_SW:
1580     case GDB_BREAKPOINT_HW:
1581         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1582             err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1583             if (err)
1584                 break;
1585         }
1586         return err;
1587 #ifndef CONFIG_USER_ONLY
1588     case GDB_WATCHPOINT_WRITE:
1589     case GDB_WATCHPOINT_READ:
1590     case GDB_WATCHPOINT_ACCESS:
1591         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1592             err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1593                                         NULL);
1594             if (err)
1595                 break;
1596         }
1597         return err;
1598 #endif
1599     default:
1600         return -ENOSYS;
1601     }
1602 }
1603
1604 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1605 {
1606     CPUState *env;
1607     int err = 0;
1608
1609     if (kvm_enabled())
1610         return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1611
1612     switch (type) {
1613     case GDB_BREAKPOINT_SW:
1614     case GDB_BREAKPOINT_HW:
1615         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1616             err = cpu_breakpoint_remove(env, addr, BP_GDB);
1617             if (err)
1618                 break;
1619         }
1620         return err;
1621 #ifndef CONFIG_USER_ONLY
1622     case GDB_WATCHPOINT_WRITE:
1623     case GDB_WATCHPOINT_READ:
1624     case GDB_WATCHPOINT_ACCESS:
1625         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1626             err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1627             if (err)
1628                 break;
1629         }
1630         return err;
1631 #endif
1632     default:
1633         return -ENOSYS;
1634     }
1635 }
1636
1637 static void gdb_breakpoint_remove_all(void)
1638 {
1639     CPUState *env;
1640
1641     if (kvm_enabled()) {
1642         kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1643         return;
1644     }
1645
1646     for (env = first_cpu; env != NULL; env = env->next_cpu) {
1647         cpu_breakpoint_remove_all(env, BP_GDB);
1648 #ifndef CONFIG_USER_ONLY
1649         cpu_watchpoint_remove_all(env, BP_GDB);
1650 #endif
1651     }
1652 }
1653
1654 static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
1655 {
1656 #if defined(TARGET_I386)
1657     cpu_synchronize_state(s->c_cpu);
1658     s->c_cpu->eip = pc;
1659 #elif defined (TARGET_PPC)
1660     s->c_cpu->nip = pc;
1661 #elif defined (TARGET_SPARC)
1662     s->c_cpu->pc = pc;
1663     s->c_cpu->npc = pc + 4;
1664 #elif defined (TARGET_ARM)
1665     s->c_cpu->regs[15] = pc;
1666 #elif defined (TARGET_SH4)
1667     s->c_cpu->pc = pc;
1668 #elif defined (TARGET_MIPS)
1669     s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
1670     if (pc & 1) {
1671         s->c_cpu->hflags |= MIPS_HFLAG_M16;
1672     } else {
1673         s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
1674     }
1675 #elif defined (TARGET_MICROBLAZE)
1676     s->c_cpu->sregs[SR_PC] = pc;
1677 #elif defined (TARGET_CRIS)
1678     s->c_cpu->pc = pc;
1679 #elif defined (TARGET_ALPHA)
1680     s->c_cpu->pc = pc;
1681 #elif defined (TARGET_S390X)
1682     cpu_synchronize_state(s->c_cpu);
1683     s->c_cpu->psw.addr = pc;
1684 #endif
1685 }
1686
1687 static inline int gdb_id(CPUState *env)
1688 {
1689 #if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1690     return env->host_tid;
1691 #else
1692     return env->cpu_index + 1;
1693 #endif
1694 }
1695
1696 static CPUState *find_cpu(uint32_t thread_id)
1697 {
1698     CPUState *env;
1699
1700     for (env = first_cpu; env != NULL; env = env->next_cpu) {
1701         if (gdb_id(env) == thread_id) {
1702             return env;
1703         }
1704     }
1705
1706     return NULL;
1707 }
1708
1709 static int gdb_handle_packet(GDBState *s, const char *line_buf)
1710 {
1711     CPUState *env;
1712     const char *p;
1713     uint32_t thread;
1714     int ch, reg_size, type, res;
1715     char buf[MAX_PACKET_LENGTH];
1716     uint8_t mem_buf[MAX_PACKET_LENGTH];
1717     uint8_t *registers;
1718     target_ulong addr, len;
1719
1720 #ifdef DEBUG_GDB
1721     printf("command='%s'\n", line_buf);
1722 #endif
1723     p = line_buf;
1724     ch = *p++;
1725     switch(ch) {
1726     case '?':
1727         /* TODO: Make this return the correct value for user-mode.  */
1728         snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1729                  gdb_id(s->c_cpu));
1730         put_packet(s, buf);
1731         /* Remove all the breakpoints when this query is issued,
1732          * because gdb is doing and initial connect and the state
1733          * should be cleaned up.
1734          */
1735         gdb_breakpoint_remove_all();
1736         break;
1737     case 'c':
1738         if (*p != '\0') {
1739             addr = strtoull(p, (char **)&p, 16);
1740             gdb_set_cpu_pc(s, addr);
1741         }
1742         s->signal = 0;
1743         gdb_continue(s);
1744         return RS_IDLE;
1745     case 'C':
1746         s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1747         if (s->signal == -1)
1748             s->signal = 0;
1749         gdb_continue(s);
1750         return RS_IDLE;
1751     case 'v':
1752         if (strncmp(p, "Cont", 4) == 0) {
1753             int res_signal, res_thread;
1754
1755             p += 4;
1756             if (*p == '?') {
1757                 put_packet(s, "vCont;c;C;s;S");
1758                 break;
1759             }
1760             res = 0;
1761             res_signal = 0;
1762             res_thread = 0;
1763             while (*p) {
1764                 int action, signal;
1765
1766                 if (*p++ != ';') {
1767                     res = 0;
1768                     break;
1769                 }
1770                 action = *p++;
1771                 signal = 0;
1772                 if (action == 'C' || action == 'S') {
1773                     signal = strtoul(p, (char **)&p, 16);
1774                 } else if (action != 'c' && action != 's') {
1775                     res = 0;
1776                     break;
1777                 }
1778                 thread = 0;
1779                 if (*p == ':') {
1780                     thread = strtoull(p+1, (char **)&p, 16);
1781                 }
1782                 action = tolower(action);
1783                 if (res == 0 || (res == 'c' && action == 's')) {
1784                     res = action;
1785                     res_signal = signal;
1786                     res_thread = thread;
1787                 }
1788             }
1789             if (res) {
1790                 if (res_thread != -1 && res_thread != 0) {
1791                     env = find_cpu(res_thread);
1792                     if (env == NULL) {
1793                         put_packet(s, "E22");
1794                         break;
1795                     }
1796                     s->c_cpu = env;
1797                 }
1798                 if (res == 's') {
1799                     cpu_single_step(s->c_cpu, sstep_flags);
1800                 }
1801                 s->signal = res_signal;
1802                 gdb_continue(s);
1803                 return RS_IDLE;
1804             }
1805             break;
1806         } else {
1807             goto unknown_command;
1808         }
1809     case 'k':
1810         /* Kill the target */
1811         fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1812         exit(0);
1813     case 'D':
1814         /* Detach packet */
1815         gdb_breakpoint_remove_all();
1816         gdb_continue(s);
1817         put_packet(s, "OK");
1818         break;
1819     case 's':
1820         if (*p != '\0') {
1821             addr = strtoull(p, (char **)&p, 16);
1822             gdb_set_cpu_pc(s, addr);
1823         }
1824         cpu_single_step(s->c_cpu, sstep_flags);
1825         gdb_continue(s);
1826         return RS_IDLE;
1827     case 'F':
1828         {
1829             target_ulong ret;
1830             target_ulong err;
1831
1832             ret = strtoull(p, (char **)&p, 16);
1833             if (*p == ',') {
1834                 p++;
1835                 err = strtoull(p, (char **)&p, 16);
1836             } else {
1837                 err = 0;
1838             }
1839             if (*p == ',')
1840                 p++;
1841             type = *p;
1842             if (gdb_current_syscall_cb)
1843                 gdb_current_syscall_cb(s->c_cpu, ret, err);
1844             if (type == 'C') {
1845                 put_packet(s, "T02");
1846             } else {
1847                 gdb_continue(s);
1848             }
1849         }
1850         break;
1851     case 'g':
1852         cpu_synchronize_state(s->g_cpu);
1853         len = 0;
1854         for (addr = 0; addr < num_g_regs; addr++) {
1855             reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
1856             len += reg_size;
1857         }
1858         memtohex(buf, mem_buf, len);
1859         put_packet(s, buf);
1860         break;
1861     case 'G':
1862         cpu_synchronize_state(s->g_cpu);
1863         registers = mem_buf;
1864         len = strlen(p) / 2;
1865         hextomem((uint8_t *)registers, p, len);
1866         for (addr = 0; addr < num_g_regs && len > 0; addr++) {
1867             reg_size = gdb_write_register(s->g_cpu, registers, addr);
1868             len -= reg_size;
1869             registers += reg_size;
1870         }
1871         put_packet(s, "OK");
1872         break;
1873     case 'm':
1874         addr = strtoull(p, (char **)&p, 16);
1875         if (*p == ',')
1876             p++;
1877         len = strtoull(p, NULL, 16);
1878         if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
1879             put_packet (s, "E14");
1880         } else {
1881             memtohex(buf, mem_buf, len);
1882             put_packet(s, buf);
1883         }
1884         break;
1885     case 'M':
1886         addr = strtoull(p, (char **)&p, 16);
1887         if (*p == ',')
1888             p++;
1889         len = strtoull(p, (char **)&p, 16);
1890         if (*p == ':')
1891             p++;
1892         hextomem(mem_buf, p, len);
1893         if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
1894             put_packet(s, "E14");
1895         else
1896             put_packet(s, "OK");
1897         break;
1898     case 'p':
1899         /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1900            This works, but can be very slow.  Anything new enough to
1901            understand XML also knows how to use this properly.  */
1902         if (!gdb_has_xml)
1903             goto unknown_command;
1904         addr = strtoull(p, (char **)&p, 16);
1905         reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
1906         if (reg_size) {
1907             memtohex(buf, mem_buf, reg_size);
1908             put_packet(s, buf);
1909         } else {
1910             put_packet(s, "E14");
1911         }
1912         break;
1913     case 'P':
1914         if (!gdb_has_xml)
1915             goto unknown_command;
1916         addr = strtoull(p, (char **)&p, 16);
1917         if (*p == '=')
1918             p++;
1919         reg_size = strlen(p) / 2;
1920         hextomem(mem_buf, p, reg_size);
1921         gdb_write_register(s->g_cpu, mem_buf, addr);
1922         put_packet(s, "OK");
1923         break;
1924     case 'Z':
1925     case 'z':
1926         type = strtoul(p, (char **)&p, 16);
1927         if (*p == ',')
1928             p++;
1929         addr = strtoull(p, (char **)&p, 16);
1930         if (*p == ',')
1931             p++;
1932         len = strtoull(p, (char **)&p, 16);
1933         if (ch == 'Z')
1934             res = gdb_breakpoint_insert(addr, len, type);
1935         else
1936             res = gdb_breakpoint_remove(addr, len, type);
1937         if (res >= 0)
1938              put_packet(s, "OK");
1939         else if (res == -ENOSYS)
1940             put_packet(s, "");
1941         else
1942             put_packet(s, "E22");
1943         break;
1944     case 'H':
1945         type = *p++;
1946         thread = strtoull(p, (char **)&p, 16);
1947         if (thread == -1 || thread == 0) {
1948             put_packet(s, "OK");
1949             break;
1950         }
1951         env = find_cpu(thread);
1952         if (env == NULL) {
1953             put_packet(s, "E22");
1954             break;
1955         }
1956         switch (type) {
1957         case 'c':
1958             s->c_cpu = env;
1959             put_packet(s, "OK");
1960             break;
1961         case 'g':
1962             s->g_cpu = env;
1963             put_packet(s, "OK");
1964             break;
1965         default:
1966              put_packet(s, "E22");
1967              break;
1968         }
1969         break;
1970     case 'T':
1971         thread = strtoull(p, (char **)&p, 16);
1972         env = find_cpu(thread);
1973
1974         if (env != NULL) {
1975             put_packet(s, "OK");
1976         } else {
1977             put_packet(s, "E22");
1978         }
1979         break;
1980     case 'q':
1981     case 'Q':
1982         /* parse any 'q' packets here */
1983         if (!strcmp(p,"qemu.sstepbits")) {
1984             /* Query Breakpoint bit definitions */
1985             snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1986                      SSTEP_ENABLE,
1987                      SSTEP_NOIRQ,
1988                      SSTEP_NOTIMER);
1989             put_packet(s, buf);
1990             break;
1991         } else if (strncmp(p,"qemu.sstep",10) == 0) {
1992             /* Display or change the sstep_flags */
1993             p += 10;
1994             if (*p != '=') {
1995                 /* Display current setting */
1996                 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
1997                 put_packet(s, buf);
1998                 break;
1999             }
2000             p++;
2001             type = strtoul(p, (char **)&p, 16);
2002             sstep_flags = type;
2003             put_packet(s, "OK");
2004             break;
2005         } else if (strcmp(p,"C") == 0) {
2006             /* "Current thread" remains vague in the spec, so always return
2007              *  the first CPU (gdb returns the first thread). */
2008             put_packet(s, "QC1");
2009             break;
2010         } else if (strcmp(p,"fThreadInfo") == 0) {
2011             s->query_cpu = first_cpu;
2012             goto report_cpuinfo;
2013         } else if (strcmp(p,"sThreadInfo") == 0) {
2014         report_cpuinfo:
2015             if (s->query_cpu) {
2016                 snprintf(buf, sizeof(buf), "m%x", gdb_id(s->query_cpu));
2017                 put_packet(s, buf);
2018                 s->query_cpu = s->query_cpu->next_cpu;
2019             } else
2020                 put_packet(s, "l");
2021             break;
2022         } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2023             thread = strtoull(p+16, (char **)&p, 16);
2024             env = find_cpu(thread);
2025             if (env != NULL) {
2026                 cpu_synchronize_state(env);
2027                 len = snprintf((char *)mem_buf, sizeof(mem_buf),
2028                                "CPU#%d [%s]", env->cpu_index,
2029                                env->halted ? "halted " : "running");
2030                 memtohex(buf, mem_buf, len);
2031                 put_packet(s, buf);
2032             }
2033             break;
2034         }
2035 #ifdef CONFIG_USER_ONLY
2036         else if (strncmp(p, "Offsets", 7) == 0) {
2037             TaskState *ts = s->c_cpu->opaque;
2038
2039             snprintf(buf, sizeof(buf),
2040                      "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2041                      ";Bss=" TARGET_ABI_FMT_lx,
2042                      ts->info->code_offset,
2043                      ts->info->data_offset,
2044                      ts->info->data_offset);
2045             put_packet(s, buf);
2046             break;
2047         }
2048 #else /* !CONFIG_USER_ONLY */
2049         else if (strncmp(p, "Rcmd,", 5) == 0) {
2050             int len = strlen(p + 5);
2051
2052             if ((len % 2) != 0) {
2053                 put_packet(s, "E01");
2054                 break;
2055             }
2056             hextomem(mem_buf, p + 5, len);
2057             len = len / 2;
2058             mem_buf[len++] = 0;
2059             qemu_chr_read(s->mon_chr, mem_buf, len);
2060             put_packet(s, "OK");
2061             break;
2062         }
2063 #endif /* !CONFIG_USER_ONLY */
2064         if (strncmp(p, "Supported", 9) == 0) {
2065             snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
2066 #ifdef GDB_CORE_XML
2067             pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
2068 #endif
2069             put_packet(s, buf);
2070             break;
2071         }
2072 #ifdef GDB_CORE_XML
2073         if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2074             const char *xml;
2075             target_ulong total_len;
2076
2077             gdb_has_xml = 1;
2078             p += 19;
2079             xml = get_feature_xml(p, &p);
2080             if (!xml) {
2081                 snprintf(buf, sizeof(buf), "E00");
2082                 put_packet(s, buf);
2083                 break;
2084             }
2085
2086             if (*p == ':')
2087                 p++;
2088             addr = strtoul(p, (char **)&p, 16);
2089             if (*p == ',')
2090                 p++;
2091             len = strtoul(p, (char **)&p, 16);
2092
2093             total_len = strlen(xml);
2094             if (addr > total_len) {
2095                 snprintf(buf, sizeof(buf), "E00");
2096                 put_packet(s, buf);
2097                 break;
2098             }
2099             if (len > (MAX_PACKET_LENGTH - 5) / 2)
2100                 len = (MAX_PACKET_LENGTH - 5) / 2;
2101             if (len < total_len - addr) {
2102                 buf[0] = 'm';
2103                 len = memtox(buf + 1, xml + addr, len);
2104             } else {
2105                 buf[0] = 'l';
2106                 len = memtox(buf + 1, xml + addr, total_len - addr);
2107             }
2108             put_packet_binary(s, buf, len + 1);
2109             break;
2110         }
2111 #endif
2112         /* Unrecognised 'q' command.  */
2113         goto unknown_command;
2114
2115     default:
2116     unknown_command:
2117         /* put empty packet */
2118         buf[0] = '\0';
2119         put_packet(s, buf);
2120         break;
2121     }
2122     return RS_IDLE;
2123 }
2124
2125 void gdb_set_stop_cpu(CPUState *env)
2126 {
2127     gdbserver_state->c_cpu = env;
2128     gdbserver_state->g_cpu = env;
2129 }
2130
2131 #ifndef CONFIG_USER_ONLY
2132 static void gdb_vm_state_change(void *opaque, int running, int reason)
2133 {
2134     GDBState *s = gdbserver_state;
2135     CPUState *env = s->c_cpu;
2136     char buf[256];
2137     const char *type;
2138     int ret;
2139
2140     if (running || (reason != EXCP_DEBUG && reason != EXCP_INTERRUPT) ||
2141         s->state == RS_INACTIVE || s->state == RS_SYSCALL)
2142         return;
2143
2144     /* disable single step if it was enable */
2145     cpu_single_step(env, 0);
2146
2147     if (reason == EXCP_DEBUG) {
2148         if (env->watchpoint_hit) {
2149             switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2150             case BP_MEM_READ:
2151                 type = "r";
2152                 break;
2153             case BP_MEM_ACCESS:
2154                 type = "a";
2155                 break;
2156             default:
2157                 type = "";
2158                 break;
2159             }
2160             snprintf(buf, sizeof(buf),
2161                      "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2162                      GDB_SIGNAL_TRAP, gdb_id(env), type,
2163                      env->watchpoint_hit->vaddr);
2164             put_packet(s, buf);
2165             env->watchpoint_hit = NULL;
2166             return;
2167         }
2168         tb_flush(env);
2169         ret = GDB_SIGNAL_TRAP;
2170     } else {
2171         ret = GDB_SIGNAL_INT;
2172     }
2173     snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
2174     put_packet(s, buf);
2175 }
2176 #endif
2177
2178 /* Send a gdb syscall request.
2179    This accepts limited printf-style format specifiers, specifically:
2180     %x  - target_ulong argument printed in hex.
2181     %lx - 64-bit argument printed in hex.
2182     %s  - string pointer (target_ulong) and length (int) pair.  */
2183 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2184 {
2185     va_list va;
2186     char buf[256];
2187     char *p;
2188     target_ulong addr;
2189     uint64_t i64;
2190     GDBState *s;
2191
2192     s = gdbserver_state;
2193     if (!s)
2194         return;
2195     gdb_current_syscall_cb = cb;
2196     s->state = RS_SYSCALL;
2197 #ifndef CONFIG_USER_ONLY
2198     vm_stop(EXCP_DEBUG);
2199 #endif
2200     s->state = RS_IDLE;
2201     va_start(va, fmt);
2202     p = buf;
2203     *(p++) = 'F';
2204     while (*fmt) {
2205         if (*fmt == '%') {
2206             fmt++;
2207             switch (*fmt++) {
2208             case 'x':
2209                 addr = va_arg(va, target_ulong);
2210                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
2211                 break;
2212             case 'l':
2213                 if (*(fmt++) != 'x')
2214                     goto bad_format;
2215                 i64 = va_arg(va, uint64_t);
2216                 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
2217                 break;
2218             case 's':
2219                 addr = va_arg(va, target_ulong);
2220                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
2221                               addr, va_arg(va, int));
2222                 break;
2223             default:
2224             bad_format:
2225                 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2226                         fmt - 1);
2227                 break;
2228             }
2229         } else {
2230             *(p++) = *(fmt++);
2231         }
2232     }
2233     *p = 0;
2234     va_end(va);
2235     put_packet(s, buf);
2236 #ifdef CONFIG_USER_ONLY
2237     gdb_handlesig(s->c_cpu, 0);
2238 #else
2239     cpu_exit(s->c_cpu);
2240 #endif
2241 }
2242
2243 static void gdb_read_byte(GDBState *s, int ch)
2244 {
2245     int i, csum;
2246     uint8_t reply;
2247
2248 #ifndef CONFIG_USER_ONLY
2249     if (s->last_packet_len) {
2250         /* Waiting for a response to the last packet.  If we see the start
2251            of a new command then abandon the previous response.  */
2252         if (ch == '-') {
2253 #ifdef DEBUG_GDB
2254             printf("Got NACK, retransmitting\n");
2255 #endif
2256             put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2257         }
2258 #ifdef DEBUG_GDB
2259         else if (ch == '+')
2260             printf("Got ACK\n");
2261         else
2262             printf("Got '%c' when expecting ACK/NACK\n", ch);
2263 #endif
2264         if (ch == '+' || ch == '$')
2265             s->last_packet_len = 0;
2266         if (ch != '$')
2267             return;
2268     }
2269     if (vm_running) {
2270         /* when the CPU is running, we cannot do anything except stop
2271            it when receiving a char */
2272         vm_stop(EXCP_INTERRUPT);
2273     } else
2274 #endif
2275     {
2276         switch(s->state) {
2277         case RS_IDLE:
2278             if (ch == '$') {
2279                 s->line_buf_index = 0;
2280                 s->state = RS_GETLINE;
2281             }
2282             break;
2283         case RS_GETLINE:
2284             if (ch == '#') {
2285             s->state = RS_CHKSUM1;
2286             } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2287                 s->state = RS_IDLE;
2288             } else {
2289             s->line_buf[s->line_buf_index++] = ch;
2290             }
2291             break;
2292         case RS_CHKSUM1:
2293             s->line_buf[s->line_buf_index] = '\0';
2294             s->line_csum = fromhex(ch) << 4;
2295             s->state = RS_CHKSUM2;
2296             break;
2297         case RS_CHKSUM2:
2298             s->line_csum |= fromhex(ch);
2299             csum = 0;
2300             for(i = 0; i < s->line_buf_index; i++) {
2301                 csum += s->line_buf[i];
2302             }
2303             if (s->line_csum != (csum & 0xff)) {
2304                 reply = '-';
2305                 put_buffer(s, &reply, 1);
2306                 s->state = RS_IDLE;
2307             } else {
2308                 reply = '+';
2309                 put_buffer(s, &reply, 1);
2310                 s->state = gdb_handle_packet(s, s->line_buf);
2311             }
2312             break;
2313         default:
2314             abort();
2315         }
2316     }
2317 }
2318
2319 #ifdef CONFIG_USER_ONLY
2320 int
2321 gdb_queuesig (void)
2322 {
2323     GDBState *s;
2324
2325     s = gdbserver_state;
2326
2327     if (gdbserver_fd < 0 || s->fd < 0)
2328         return 0;
2329     else
2330         return 1;
2331 }
2332
2333 int
2334 gdb_handlesig (CPUState *env, int sig)
2335 {
2336   GDBState *s;
2337   char buf[256];
2338   int n;
2339
2340   s = gdbserver_state;
2341   if (gdbserver_fd < 0 || s->fd < 0)
2342     return sig;
2343
2344   /* disable single step if it was enabled */
2345   cpu_single_step(env, 0);
2346   tb_flush(env);
2347
2348   if (sig != 0)
2349     {
2350       snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2351       put_packet(s, buf);
2352     }
2353   /* put_packet() might have detected that the peer terminated the
2354      connection.  */
2355   if (s->fd < 0)
2356       return sig;
2357
2358   sig = 0;
2359   s->state = RS_IDLE;
2360   s->running_state = 0;
2361   while (s->running_state == 0) {
2362       n = read (s->fd, buf, 256);
2363       if (n > 0)
2364         {
2365           int i;
2366
2367           for (i = 0; i < n; i++)
2368             gdb_read_byte (s, buf[i]);
2369         }
2370       else if (n == 0 || errno != EAGAIN)
2371         {
2372           /* XXX: Connection closed.  Should probably wait for annother
2373              connection before continuing.  */
2374           return sig;
2375         }
2376   }
2377   sig = s->signal;
2378   s->signal = 0;
2379   return sig;
2380 }
2381
2382 /* Tell the remote gdb that the process has exited.  */
2383 void gdb_exit(CPUState *env, int code)
2384 {
2385   GDBState *s;
2386   char buf[4];
2387
2388   s = gdbserver_state;
2389   if (gdbserver_fd < 0 || s->fd < 0)
2390     return;
2391
2392   snprintf(buf, sizeof(buf), "W%02x", code);
2393   put_packet(s, buf);
2394 }
2395
2396 /* Tell the remote gdb that the process has exited due to SIG.  */
2397 void gdb_signalled(CPUState *env, int sig)
2398 {
2399   GDBState *s;
2400   char buf[4];
2401
2402   s = gdbserver_state;
2403   if (gdbserver_fd < 0 || s->fd < 0)
2404     return;
2405
2406   snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2407   put_packet(s, buf);
2408 }
2409
2410 static void gdb_accept(void)
2411 {
2412     GDBState *s;
2413     struct sockaddr_in sockaddr;
2414     socklen_t len;
2415     int val, fd;
2416
2417     for(;;) {
2418         len = sizeof(sockaddr);
2419         fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2420         if (fd < 0 && errno != EINTR) {
2421             perror("accept");
2422             return;
2423         } else if (fd >= 0) {
2424 #ifndef _WIN32
2425             fcntl(fd, F_SETFD, FD_CLOEXEC);
2426 #endif
2427             break;
2428         }
2429     }
2430
2431     /* set short latency */
2432     val = 1;
2433     setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2434
2435     s = qemu_mallocz(sizeof(GDBState));
2436     s->c_cpu = first_cpu;
2437     s->g_cpu = first_cpu;
2438     s->fd = fd;
2439     gdb_has_xml = 0;
2440
2441     gdbserver_state = s;
2442
2443     fcntl(fd, F_SETFL, O_NONBLOCK);
2444 }
2445
2446 static int gdbserver_open(int port)
2447 {
2448     struct sockaddr_in sockaddr;
2449     int fd, val, ret;
2450
2451     fd = socket(PF_INET, SOCK_STREAM, 0);
2452     if (fd < 0) {
2453         perror("socket");
2454         return -1;
2455     }
2456 #ifndef _WIN32
2457     fcntl(fd, F_SETFD, FD_CLOEXEC);
2458 #endif
2459
2460     /* allow fast reuse */
2461     val = 1;
2462     setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2463
2464     sockaddr.sin_family = AF_INET;
2465     sockaddr.sin_port = htons(port);
2466     sockaddr.sin_addr.s_addr = 0;
2467     ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2468     if (ret < 0) {
2469         perror("bind");
2470         return -1;
2471     }
2472     ret = listen(fd, 0);
2473     if (ret < 0) {
2474         perror("listen");
2475         return -1;
2476     }
2477     return fd;
2478 }
2479
2480 int gdbserver_start(int port)
2481 {
2482     gdbserver_fd = gdbserver_open(port);
2483     if (gdbserver_fd < 0)
2484         return -1;
2485     /* accept connections */
2486     gdb_accept();
2487     return 0;
2488 }
2489
2490 /* Disable gdb stub for child processes.  */
2491 void gdbserver_fork(CPUState *env)
2492 {
2493     GDBState *s = gdbserver_state;
2494     if (gdbserver_fd < 0 || s->fd < 0)
2495       return;
2496     close(s->fd);
2497     s->fd = -1;
2498     cpu_breakpoint_remove_all(env, BP_GDB);
2499     cpu_watchpoint_remove_all(env, BP_GDB);
2500 }
2501 #else
2502 static int gdb_chr_can_receive(void *opaque)
2503 {
2504   /* We can handle an arbitrarily large amount of data.
2505    Pick the maximum packet size, which is as good as anything.  */
2506   return MAX_PACKET_LENGTH;
2507 }
2508
2509 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2510 {
2511     int i;
2512
2513     for (i = 0; i < size; i++) {
2514         gdb_read_byte(gdbserver_state, buf[i]);
2515     }
2516 }
2517
2518 static void gdb_chr_event(void *opaque, int event)
2519 {
2520     switch (event) {
2521     case CHR_EVENT_OPENED:
2522         vm_stop(EXCP_INTERRUPT);
2523         gdb_has_xml = 0;
2524         break;
2525     default:
2526         break;
2527     }
2528 }
2529
2530 static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2531 {
2532     char buf[MAX_PACKET_LENGTH];
2533
2534     buf[0] = 'O';
2535     if (len > (MAX_PACKET_LENGTH/2) - 1)
2536         len = (MAX_PACKET_LENGTH/2) - 1;
2537     memtohex(buf + 1, (uint8_t *)msg, len);
2538     put_packet(s, buf);
2539 }
2540
2541 static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2542 {
2543     const char *p = (const char *)buf;
2544     int max_sz;
2545
2546     max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2547     for (;;) {
2548         if (len <= max_sz) {
2549             gdb_monitor_output(gdbserver_state, p, len);
2550             break;
2551         }
2552         gdb_monitor_output(gdbserver_state, p, max_sz);
2553         p += max_sz;
2554         len -= max_sz;
2555     }
2556     return len;
2557 }
2558
2559 #ifndef _WIN32
2560 static void gdb_sigterm_handler(int signal)
2561 {
2562     if (vm_running)
2563         vm_stop(EXCP_INTERRUPT);
2564 }
2565 #endif
2566
2567 int gdbserver_start(const char *device)
2568 {
2569     GDBState *s;
2570     char gdbstub_device_name[128];
2571     CharDriverState *chr = NULL;
2572     CharDriverState *mon_chr;
2573
2574     if (!device)
2575         return -1;
2576     if (strcmp(device, "none") != 0) {
2577         if (strstart(device, "tcp:", NULL)) {
2578             /* enforce required TCP attributes */
2579             snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2580                      "%s,nowait,nodelay,server", device);
2581             device = gdbstub_device_name;
2582         }
2583 #ifndef _WIN32
2584         else if (strcmp(device, "stdio") == 0) {
2585             struct sigaction act;
2586
2587             memset(&act, 0, sizeof(act));
2588             act.sa_handler = gdb_sigterm_handler;
2589             sigaction(SIGINT, &act, NULL);
2590         }
2591 #endif
2592         chr = qemu_chr_open("gdb", device, NULL);
2593         if (!chr)
2594             return -1;
2595
2596         qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2597                               gdb_chr_event, NULL);
2598     }
2599
2600     s = gdbserver_state;
2601     if (!s) {
2602         s = qemu_mallocz(sizeof(GDBState));
2603         gdbserver_state = s;
2604
2605         qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
2606
2607         /* Initialize a monitor terminal for gdb */
2608         mon_chr = qemu_mallocz(sizeof(*mon_chr));
2609         mon_chr->chr_write = gdb_monitor_write;
2610         monitor_init(mon_chr, 0);
2611     } else {
2612         if (s->chr)
2613             qemu_chr_close(s->chr);
2614         mon_chr = s->mon_chr;
2615         memset(s, 0, sizeof(GDBState));
2616     }
2617     s->c_cpu = first_cpu;
2618     s->g_cpu = first_cpu;
2619     s->chr = chr;
2620     s->state = chr ? RS_IDLE : RS_INACTIVE;
2621     s->mon_chr = mon_chr;
2622
2623     return 0;
2624 }
2625 #endif