2 * qemu/kvm integration, x86 specific code
4 * Copyright (C) 2006-2008 Qumranet Technologies
6 * Licensed under the terms of the GNU GPL version 2 or higher.
10 #include "config-host.h"
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
27 #define MSR_IA32_TSC 0x10
29 static struct kvm_msr_list
*kvm_msr_list
;
30 extern unsigned int kvm_shadow_memory
;
31 static int kvm_has_msr_star
;
32 static int kvm_has_vm_hsave_pa
;
34 static int lm_capable_kernel
;
36 int kvm_set_tss_addr(kvm_context_t kvm
, unsigned long addr
)
40 * Tell fw_cfg to notify the BIOS to reserve the range.
42 if (e820_add_entry(addr
, 0x4000, E820_RESERVED
) < 0) {
43 perror("e820_add_entry() table is full");
47 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_TSS_ADDR
, addr
);
49 fprintf(stderr
, "kvm_set_tss_addr: %m\n");
55 static int kvm_init_tss(kvm_context_t kvm
)
59 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_TSS_ADDR
);
62 * this address is 3 pages before the bios, and the bios should present
65 r
= kvm_set_tss_addr(kvm
, 0xfeffd000);
67 fprintf(stderr
, "kvm_init_tss: unable to set tss addr\n");
71 fprintf(stderr
, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
76 static int kvm_set_identity_map_addr(kvm_context_t kvm
, uint64_t addr
)
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
81 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_IDENTITY_MAP_ADDR
);
83 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_IDENTITY_MAP_ADDR
, &addr
);
85 fprintf(stderr
, "kvm_set_identity_map_addr: %m\n");
94 static int kvm_init_identity_map_page(kvm_context_t kvm
)
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
99 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_IDENTITY_MAP_ADDR
);
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
105 r
= kvm_set_identity_map_addr(kvm
, 0xfeffc000);
107 fprintf(stderr
, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
116 static int kvm_create_pit(kvm_context_t kvm
)
121 kvm_state
->pit_in_kernel
= 0;
122 if (!kvm
->no_pit_creation
) {
123 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_PIT
);
125 r
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_PIT
);
127 kvm_state
->pit_in_kernel
= 1;
129 fprintf(stderr
, "Create kernel PIC irqchip failed\n");
138 int kvm_arch_create(kvm_context_t kvm
, unsigned long phys_mem_bytes
,
143 r
= kvm_init_tss(kvm
);
147 r
= kvm_init_identity_map_page(kvm
);
151 r
= kvm_create_pit(kvm
);
155 r
= kvm_init_coalesced_mmio(kvm
);
162 #ifdef KVM_EXIT_TPR_ACCESS
164 static int kvm_handle_tpr_access(CPUState
*env
)
166 struct kvm_run
*run
= env
->kvm_run
;
167 kvm_tpr_access_report(env
,
169 run
->tpr_access
.is_write
);
174 int kvm_enable_vapic(CPUState
*env
, uint64_t vapic
)
176 struct kvm_vapic_addr va
= {
180 return kvm_vcpu_ioctl(env
, KVM_SET_VAPIC_ADDR
, &va
);
185 int kvm_arch_run(CPUState
*env
)
188 struct kvm_run
*run
= env
->kvm_run
;
190 switch (run
->exit_reason
) {
191 #ifdef KVM_EXIT_SET_TPR
192 case KVM_EXIT_SET_TPR
:
195 #ifdef KVM_EXIT_TPR_ACCESS
196 case KVM_EXIT_TPR_ACCESS
:
197 r
= kvm_handle_tpr_access(env
);
208 #ifdef KVM_CAP_IRQCHIP
210 int kvm_get_lapic(CPUState
*env
, struct kvm_lapic_state
*s
)
214 if (!kvm_irqchip_in_kernel())
217 r
= kvm_vcpu_ioctl(env
, KVM_GET_LAPIC
, s
);
219 fprintf(stderr
, "KVM_GET_LAPIC failed\n");
223 int kvm_set_lapic(CPUState
*env
, struct kvm_lapic_state
*s
)
227 if (!kvm_irqchip_in_kernel())
230 r
= kvm_vcpu_ioctl(env
, KVM_SET_LAPIC
, s
);
233 fprintf(stderr
, "KVM_SET_LAPIC failed\n");
241 int kvm_get_pit(kvm_context_t kvm
, struct kvm_pit_state
*s
)
243 if (!kvm_pit_in_kernel())
245 return kvm_vm_ioctl(kvm_state
, KVM_GET_PIT
, s
);
248 int kvm_set_pit(kvm_context_t kvm
, struct kvm_pit_state
*s
)
250 if (!kvm_pit_in_kernel())
252 return kvm_vm_ioctl(kvm_state
, KVM_SET_PIT
, s
);
255 #ifdef KVM_CAP_PIT_STATE2
256 int kvm_get_pit2(kvm_context_t kvm
, struct kvm_pit_state2
*ps2
)
258 if (!kvm_pit_in_kernel())
260 return kvm_vm_ioctl(kvm_state
, KVM_GET_PIT2
, ps2
);
263 int kvm_set_pit2(kvm_context_t kvm
, struct kvm_pit_state2
*ps2
)
265 if (!kvm_pit_in_kernel())
267 return kvm_vm_ioctl(kvm_state
, KVM_SET_PIT2
, ps2
);
273 int kvm_has_pit_state2(kvm_context_t kvm
)
277 #ifdef KVM_CAP_PIT_STATE2
278 r
= kvm_check_extension(kvm_state
, KVM_CAP_PIT_STATE2
);
283 void kvm_show_code(CPUState
*env
)
285 #define SHOW_CODE_LEN 50
286 struct kvm_regs regs
;
287 struct kvm_sregs sregs
;
291 char code_str
[SHOW_CODE_LEN
* 3 + 1];
294 r
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
296 perror("KVM_GET_SREGS");
299 r
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
301 perror("KVM_GET_REGS");
304 rip
= sregs
.cs
.base
+ regs
.rip
;
305 back_offset
= regs
.rip
;
306 if (back_offset
> 20)
309 for (n
= -back_offset
; n
< SHOW_CODE_LEN
-back_offset
; ++n
) {
311 strcat(code_str
, " -->");
312 cpu_physical_memory_rw(rip
+ n
, &code
, 1, 1);
313 sprintf(code_str
+ strlen(code_str
), " %02x", code
);
315 fprintf(stderr
, "code:%s\n", code_str
);
320 * Returns available msr list. User must free.
322 static struct kvm_msr_list
*kvm_get_msr_list(void)
324 struct kvm_msr_list sizer
, *msrs
;
328 r
= kvm_ioctl(kvm_state
, KVM_GET_MSR_INDEX_LIST
, &sizer
);
329 if (r
< 0 && r
!= -E2BIG
)
331 /* Old kernel modules had a bug and could write beyond the provided
332 memory. Allocate at least a safe amount of 1K. */
333 msrs
= qemu_malloc(MAX(1024, sizeof(*msrs
) +
334 sizer
.nmsrs
* sizeof(*msrs
->indices
)));
336 msrs
->nmsrs
= sizer
.nmsrs
;
337 r
= kvm_ioctl(kvm_state
, KVM_GET_MSR_INDEX_LIST
, msrs
);
346 int kvm_get_msrs(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
348 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
352 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
353 r
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, kmsrs
);
354 memcpy(msrs
, kmsrs
->entries
, n
* sizeof *msrs
);
359 int kvm_set_msrs(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
361 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
365 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
366 r
= kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, kmsrs
);
371 int kvm_get_mce_cap_supported(kvm_context_t kvm
, uint64_t *mce_cap
,
377 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_MCE
);
380 return kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
386 int kvm_setup_mce(CPUState
*env
, uint64_t *mcg_cap
)
389 return kvm_vcpu_ioctl(env
, KVM_X86_SETUP_MCE
, mcg_cap
);
395 int kvm_set_mce(CPUState
*env
, struct kvm_x86_mce
*m
)
398 return kvm_vcpu_ioctl(env
, KVM_X86_SET_MCE
, m
);
404 static void print_seg(FILE *file
, const char *name
, struct kvm_segment
*seg
)
407 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
409 name
, seg
->selector
, seg
->base
, seg
->limit
, seg
->present
,
410 seg
->dpl
, seg
->db
, seg
->s
, seg
->type
, seg
->l
, seg
->g
,
414 static void print_dt(FILE *file
, const char *name
, struct kvm_dtable
*dt
)
416 fprintf(stderr
, "%s %llx/%x\n", name
, dt
->base
, dt
->limit
);
419 void kvm_show_regs(CPUState
*env
)
421 struct kvm_regs regs
;
422 struct kvm_sregs sregs
;
425 r
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
427 perror("KVM_GET_REGS");
431 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
432 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
433 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
434 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
435 "rip %016llx rflags %08llx\n",
436 regs
.rax
, regs
.rbx
, regs
.rcx
, regs
.rdx
,
437 regs
.rsi
, regs
.rdi
, regs
.rsp
, regs
.rbp
,
438 regs
.r8
, regs
.r9
, regs
.r10
, regs
.r11
,
439 regs
.r12
, regs
.r13
, regs
.r14
, regs
.r15
,
440 regs
.rip
, regs
.rflags
);
441 r
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
443 perror("KVM_GET_SREGS");
446 print_seg(stderr
, "cs", &sregs
.cs
);
447 print_seg(stderr
, "ds", &sregs
.ds
);
448 print_seg(stderr
, "es", &sregs
.es
);
449 print_seg(stderr
, "ss", &sregs
.ss
);
450 print_seg(stderr
, "fs", &sregs
.fs
);
451 print_seg(stderr
, "gs", &sregs
.gs
);
452 print_seg(stderr
, "tr", &sregs
.tr
);
453 print_seg(stderr
, "ldt", &sregs
.ldt
);
454 print_dt(stderr
, "gdt", &sregs
.gdt
);
455 print_dt(stderr
, "idt", &sregs
.idt
);
456 fprintf(stderr
, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
458 sregs
.cr0
, sregs
.cr2
, sregs
.cr3
, sregs
.cr4
, sregs
.cr8
,
462 static void kvm_set_cr8(CPUState
*env
, uint64_t cr8
)
464 env
->kvm_run
->cr8
= cr8
;
467 int kvm_setup_cpuid(CPUState
*env
, int nent
,
468 struct kvm_cpuid_entry
*entries
)
470 struct kvm_cpuid
*cpuid
;
473 cpuid
= qemu_malloc(sizeof(*cpuid
) + nent
* sizeof(*entries
));
476 memcpy(cpuid
->entries
, entries
, nent
* sizeof(*entries
));
477 r
= kvm_vcpu_ioctl(env
, KVM_SET_CPUID
, cpuid
);
483 int kvm_setup_cpuid2(CPUState
*env
, int nent
,
484 struct kvm_cpuid_entry2
*entries
)
486 struct kvm_cpuid2
*cpuid
;
489 cpuid
= qemu_malloc(sizeof(*cpuid
) + nent
* sizeof(*entries
));
492 memcpy(cpuid
->entries
, entries
, nent
* sizeof(*entries
));
493 r
= kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, cpuid
);
498 int kvm_set_shadow_pages(kvm_context_t kvm
, unsigned int nrshadow_pages
)
500 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
503 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
,
504 KVM_CAP_MMU_SHADOW_CACHE_CONTROL
);
506 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_NR_MMU_PAGES
, nrshadow_pages
);
508 fprintf(stderr
, "kvm_set_shadow_pages: %m\n");
517 int kvm_get_shadow_pages(kvm_context_t kvm
, unsigned int *nrshadow_pages
)
519 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
522 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
,
523 KVM_CAP_MMU_SHADOW_CACHE_CONTROL
);
525 *nrshadow_pages
= kvm_vm_ioctl(kvm_state
, KVM_GET_NR_MMU_PAGES
);
533 static int kvm_enable_tpr_access_reporting(CPUState
*env
)
536 struct kvm_tpr_access_ctl tac
= { .enabled
= 1 };
538 r
= kvm_ioctl(env
->kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_VAPIC
);
541 return kvm_vcpu_ioctl(env
, KVM_TPR_ACCESS_REPORTING
, &tac
);
545 #ifdef KVM_CAP_ADJUST_CLOCK
546 static struct kvm_clock_data kvmclock_data
;
548 static void kvmclock_pre_save(void *opaque
)
550 struct kvm_clock_data
*cl
= opaque
;
552 kvm_vm_ioctl(kvm_state
, KVM_GET_CLOCK
, cl
);
555 static int kvmclock_post_load(void *opaque
, int version_id
)
557 struct kvm_clock_data
*cl
= opaque
;
559 return kvm_vm_ioctl(kvm_state
, KVM_SET_CLOCK
, cl
);
562 static const VMStateDescription vmstate_kvmclock
= {
565 .minimum_version_id
= 1,
566 .minimum_version_id_old
= 1,
567 .pre_save
= kvmclock_pre_save
,
568 .post_load
= kvmclock_post_load
,
569 .fields
= (VMStateField
[]) {
570 VMSTATE_U64(clock
, struct kvm_clock_data
),
571 VMSTATE_END_OF_LIST()
576 int kvm_arch_qemu_create_context(void)
579 struct utsname utsname
;
582 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
584 if (kvm_shadow_memory
)
585 kvm_set_shadow_pages(kvm_context
, kvm_shadow_memory
);
587 kvm_msr_list
= kvm_get_msr_list();
590 for (i
= 0; i
< kvm_msr_list
->nmsrs
; ++i
) {
591 if (kvm_msr_list
->indices
[i
] == MSR_STAR
)
592 kvm_has_msr_star
= 1;
593 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
)
594 kvm_has_vm_hsave_pa
= 1;
597 #ifdef KVM_CAP_ADJUST_CLOCK
598 if (kvm_check_extension(kvm_state
, KVM_CAP_ADJUST_CLOCK
))
599 vmstate_register(NULL
, 0, &vmstate_kvmclock
, &kvmclock_data
);
602 r
= kvm_set_boot_cpu_id(0);
603 if (r
< 0 && r
!= -ENOSYS
) {
610 /* returns 0 on success, non-0 on failure */
611 static int get_msr_entry(struct kvm_msr_entry
*entry
, CPUState
*env
)
613 switch (entry
->index
) {
614 case MSR_IA32_SYSENTER_CS
:
615 env
->sysenter_cs
= entry
->data
;
617 case MSR_IA32_SYSENTER_ESP
:
618 env
->sysenter_esp
= entry
->data
;
620 case MSR_IA32_SYSENTER_EIP
:
621 env
->sysenter_eip
= entry
->data
;
624 env
->star
= entry
->data
;
628 env
->cstar
= entry
->data
;
630 case MSR_KERNELGSBASE
:
631 env
->kernelgsbase
= entry
->data
;
634 env
->fmask
= entry
->data
;
637 env
->lstar
= entry
->data
;
641 env
->tsc
= entry
->data
;
643 case MSR_VM_HSAVE_PA
:
644 env
->vm_hsave
= entry
->data
;
646 case MSR_KVM_SYSTEM_TIME
:
647 env
->system_time_msr
= entry
->data
;
649 case MSR_KVM_WALL_CLOCK
:
650 env
->wall_clock_msr
= entry
->data
;
654 env
->mcg_status
= entry
->data
;
657 env
->mcg_ctl
= entry
->data
;
662 if (entry
->index
>= MSR_MC0_CTL
&&
663 entry
->index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
664 env
->mce_banks
[entry
->index
- MSR_MC0_CTL
] = entry
->data
;
668 printf("Warning unknown msr index 0x%x\n", entry
->index
);
674 static void kvm_arch_save_mpstate(CPUState
*env
)
676 #ifdef KVM_CAP_MP_STATE
678 struct kvm_mp_state mp_state
;
680 r
= kvm_get_mpstate(env
, &mp_state
);
684 env
->mp_state
= mp_state
.mp_state
;
685 if (kvm_irqchip_in_kernel()) {
686 env
->halted
= (env
->mp_state
== KVM_MP_STATE_HALTED
);
694 static void kvm_arch_load_mpstate(CPUState
*env
)
696 #ifdef KVM_CAP_MP_STATE
697 struct kvm_mp_state mp_state
;
700 * -1 indicates that the host did not support GET_MP_STATE ioctl,
703 if (env
->mp_state
!= -1) {
704 mp_state
.mp_state
= env
->mp_state
;
705 kvm_set_mpstate(env
, &mp_state
);
710 static void kvm_reset_mpstate(CPUState
*env
)
712 #ifdef KVM_CAP_MP_STATE
713 if (kvm_check_extension(kvm_state
, KVM_CAP_MP_STATE
)) {
714 if (kvm_irqchip_in_kernel()) {
715 env
->mp_state
= cpu_is_bsp(env
) ? KVM_MP_STATE_RUNNABLE
:
716 KVM_MP_STATE_UNINITIALIZED
;
718 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
724 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
726 lhs
->selector
= rhs
->selector
;
727 lhs
->base
= rhs
->base
;
728 lhs
->limit
= rhs
->limit
;
740 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
742 unsigned flags
= rhs
->flags
;
743 lhs
->selector
= rhs
->selector
;
744 lhs
->base
= rhs
->base
;
745 lhs
->limit
= rhs
->limit
;
746 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
747 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
748 lhs
->dpl
= rhs
->selector
& 3;
749 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
750 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
751 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
752 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
753 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
757 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
759 lhs
->selector
= rhs
->selector
;
760 lhs
->base
= rhs
->base
;
761 lhs
->limit
= rhs
->limit
;
763 (rhs
->type
<< DESC_TYPE_SHIFT
)
764 | (rhs
->present
* DESC_P_MASK
)
765 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
766 | (rhs
->db
<< DESC_B_SHIFT
)
767 | (rhs
->s
* DESC_S_MASK
)
768 | (rhs
->l
<< DESC_L_SHIFT
)
769 | (rhs
->g
* DESC_G_MASK
)
770 | (rhs
->avl
* DESC_AVL_MASK
);
773 #define XSAVE_CWD_RIP 2
774 #define XSAVE_CWD_RDP 4
775 #define XSAVE_MXCSR 6
776 #define XSAVE_ST_SPACE 8
777 #define XSAVE_XMM_SPACE 40
778 #define XSAVE_XSTATE_BV 128
779 #define XSAVE_YMMH_SPACE 144
781 void kvm_arch_load_regs(CPUState
*env
, int level
)
783 struct kvm_regs regs
;
785 struct kvm_sregs sregs
;
786 struct kvm_msr_entry msrs
[100];
789 assert(kvm_cpu_is_stopped(env
) || env
->thread_id
== kvm_get_thread_id());
791 regs
.rax
= env
->regs
[R_EAX
];
792 regs
.rbx
= env
->regs
[R_EBX
];
793 regs
.rcx
= env
->regs
[R_ECX
];
794 regs
.rdx
= env
->regs
[R_EDX
];
795 regs
.rsi
= env
->regs
[R_ESI
];
796 regs
.rdi
= env
->regs
[R_EDI
];
797 regs
.rsp
= env
->regs
[R_ESP
];
798 regs
.rbp
= env
->regs
[R_EBP
];
800 regs
.r8
= env
->regs
[8];
801 regs
.r9
= env
->regs
[9];
802 regs
.r10
= env
->regs
[10];
803 regs
.r11
= env
->regs
[11];
804 regs
.r12
= env
->regs
[12];
805 regs
.r13
= env
->regs
[13];
806 regs
.r14
= env
->regs
[14];
807 regs
.r15
= env
->regs
[15];
810 regs
.rflags
= env
->eflags
;
813 kvm_set_regs(env
, ®s
);
816 if (kvm_check_extension(kvm_state
, KVM_CAP_XSAVE
)) {
817 struct kvm_xsave
* xsave
;
819 uint16_t cwd
, swd
, twd
, fop
;
821 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
822 memset(xsave
, 0, sizeof(struct kvm_xsave
));
823 cwd
= swd
= twd
= fop
= 0;
824 swd
= env
->fpus
& ~(7 << 11);
825 swd
|= (env
->fpstt
& 7) << 11;
827 for (i
= 0; i
< 8; ++i
)
828 twd
|= (!env
->fptags
[i
]) << i
;
829 xsave
->region
[0] = (uint32_t)(swd
<< 16) + cwd
;
830 xsave
->region
[1] = (uint32_t)(fop
<< 16) + twd
;
831 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
833 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
834 sizeof env
->xmm_regs
);
835 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
836 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
837 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
838 sizeof env
->ymmh_regs
);
839 kvm_set_xsave(env
, xsave
);
840 if (kvm_check_extension(kvm_state
, KVM_CAP_XCRS
)) {
841 struct kvm_xcrs xcrs
;
845 xcrs
.xcrs
[0].xcr
= 0;
846 xcrs
.xcrs
[0].value
= env
->xcr0
;
847 kvm_set_xcrs(env
, &xcrs
);
852 memset(&fpu
, 0, sizeof fpu
);
853 fpu
.fsw
= env
->fpus
& ~(7 << 11);
854 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
856 for (i
= 0; i
< 8; ++i
)
857 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
858 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
859 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
860 fpu
.mxcsr
= env
->mxcsr
;
861 kvm_set_fpu(env
, &fpu
);
866 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
867 if (env
->interrupt_injected
>= 0) {
868 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
869 (uint64_t)1 << (env
->interrupt_injected
% 64);
872 if ((env
->eflags
& VM_MASK
)) {
873 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
874 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
875 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
876 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
877 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
878 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
880 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
881 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
882 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
883 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
884 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
885 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
887 if (env
->cr
[0] & CR0_PE_MASK
) {
888 /* force ss cpl to cs cpl */
889 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
890 (sregs
.cs
.selector
& 3);
891 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
895 set_seg(&sregs
.tr
, &env
->tr
);
896 set_seg(&sregs
.ldt
, &env
->ldt
);
898 sregs
.idt
.limit
= env
->idt
.limit
;
899 sregs
.idt
.base
= env
->idt
.base
;
900 sregs
.gdt
.limit
= env
->gdt
.limit
;
901 sregs
.gdt
.base
= env
->gdt
.base
;
903 sregs
.cr0
= env
->cr
[0];
904 sregs
.cr2
= env
->cr
[2];
905 sregs
.cr3
= env
->cr
[3];
906 sregs
.cr4
= env
->cr
[4];
908 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
909 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
911 sregs
.efer
= env
->efer
;
913 kvm_set_sregs(env
, &sregs
);
917 /* Remember to increase msrs size if you add new registers below */
918 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
919 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
920 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
921 if (kvm_has_msr_star
)
922 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
923 if (kvm_has_vm_hsave_pa
)
924 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
926 if (lm_capable_kernel
) {
927 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
928 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
929 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
930 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
933 if (level
== KVM_PUT_FULL_STATE
) {
935 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
936 * writeback. Until this is fixed, we only write the offset to SMP
937 * guests after migration, desynchronizing the VCPUs, but avoiding
938 * huge jump-backs that would occur without any writeback at all.
940 if (smp_cpus
== 1 || env
->tsc
!= 0) {
941 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
943 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
944 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
948 if (level
== KVM_PUT_RESET_STATE
)
949 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
950 else if (level
== KVM_PUT_FULL_STATE
) {
951 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
952 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
953 for (i
= 0; i
< (env
->mcg_cap
& 0xff); i
++)
954 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
959 rc
= kvm_set_msrs(env
, msrs
, n
);
961 perror("kvm_set_msrs FAILED");
963 if (level
>= KVM_PUT_RESET_STATE
) {
964 kvm_arch_load_mpstate(env
);
967 if (level
== KVM_PUT_FULL_STATE
) {
968 if (env
->kvm_vcpu_update_vapic
)
969 kvm_tpr_enable_vapic(env
);
972 kvm_put_vcpu_events(env
, level
);
973 kvm_put_debugregs(env
);
976 kvm_guest_debug_workarounds(env
);
979 void kvm_arch_save_regs(CPUState
*env
)
981 struct kvm_regs regs
;
983 struct kvm_sregs sregs
;
984 struct kvm_msr_entry msrs
[100];
986 uint32_t i
, n
, rc
, bit
;
988 assert(kvm_cpu_is_stopped(env
) || env
->thread_id
== kvm_get_thread_id());
990 kvm_get_regs(env
, ®s
);
992 env
->regs
[R_EAX
] = regs
.rax
;
993 env
->regs
[R_EBX
] = regs
.rbx
;
994 env
->regs
[R_ECX
] = regs
.rcx
;
995 env
->regs
[R_EDX
] = regs
.rdx
;
996 env
->regs
[R_ESI
] = regs
.rsi
;
997 env
->regs
[R_EDI
] = regs
.rdi
;
998 env
->regs
[R_ESP
] = regs
.rsp
;
999 env
->regs
[R_EBP
] = regs
.rbp
;
1000 #ifdef TARGET_X86_64
1001 env
->regs
[8] = regs
.r8
;
1002 env
->regs
[9] = regs
.r9
;
1003 env
->regs
[10] = regs
.r10
;
1004 env
->regs
[11] = regs
.r11
;
1005 env
->regs
[12] = regs
.r12
;
1006 env
->regs
[13] = regs
.r13
;
1007 env
->regs
[14] = regs
.r14
;
1008 env
->regs
[15] = regs
.r15
;
1011 env
->eflags
= regs
.rflags
;
1012 env
->eip
= regs
.rip
;
1014 #ifdef KVM_CAP_XSAVE
1015 if (kvm_check_extension(kvm_state
, KVM_CAP_XSAVE
)) {
1016 struct kvm_xsave
* xsave
;
1017 uint16_t cwd
, swd
, twd
, fop
;
1018 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
1019 kvm_get_xsave(env
, xsave
);
1020 cwd
= (uint16_t)xsave
->region
[0];
1021 swd
= (uint16_t)(xsave
->region
[0] >> 16);
1022 twd
= (uint16_t)xsave
->region
[1];
1023 fop
= (uint16_t)(xsave
->region
[1] >> 16);
1024 env
->fpstt
= (swd
>> 11) & 7;
1027 for (i
= 0; i
< 8; ++i
)
1028 env
->fptags
[i
] = !((twd
>> i
) & 1);
1029 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
1030 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
1031 sizeof env
->fpregs
);
1032 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
1033 sizeof env
->xmm_regs
);
1034 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
1035 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
1036 sizeof env
->ymmh_regs
);
1037 if (kvm_check_extension(kvm_state
, KVM_CAP_XCRS
)) {
1038 struct kvm_xcrs xcrs
;
1040 kvm_get_xcrs(env
, &xcrs
);
1041 if (xcrs
.xcrs
[0].xcr
== 0)
1042 env
->xcr0
= xcrs
.xcrs
[0].value
;
1047 kvm_get_fpu(env
, &fpu
);
1048 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1049 env
->fpus
= fpu
.fsw
;
1050 env
->fpuc
= fpu
.fcw
;
1051 for (i
= 0; i
< 8; ++i
)
1052 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1053 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1054 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
1055 env
->mxcsr
= fpu
.mxcsr
;
1056 #ifdef KVM_CAP_XSAVE
1060 kvm_get_sregs(env
, &sregs
);
1062 /* There can only be one pending IRQ set in the bitmap at a time, so try
1063 to find it and save its number instead (-1 for none). */
1064 env
->interrupt_injected
= -1;
1065 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1066 if (sregs
.interrupt_bitmap
[i
]) {
1067 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1068 env
->interrupt_injected
= i
* 64 + bit
;
1073 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1074 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1075 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1076 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1077 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1078 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1080 get_seg(&env
->tr
, &sregs
.tr
);
1081 get_seg(&env
->ldt
, &sregs
.ldt
);
1083 env
->idt
.limit
= sregs
.idt
.limit
;
1084 env
->idt
.base
= sregs
.idt
.base
;
1085 env
->gdt
.limit
= sregs
.gdt
.limit
;
1086 env
->gdt
.base
= sregs
.gdt
.base
;
1088 env
->cr
[0] = sregs
.cr0
;
1089 env
->cr
[2] = sregs
.cr2
;
1090 env
->cr
[3] = sregs
.cr3
;
1091 env
->cr
[4] = sregs
.cr4
;
1093 cpu_set_apic_base(env
->apic_state
, sregs
.apic_base
);
1095 env
->efer
= sregs
.efer
;
1096 //cpu_set_apic_tpr(env, sregs.cr8);
1098 #define HFLAG_COPY_MASK ~( \
1099 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1100 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1101 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1102 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1104 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1105 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1106 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1107 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1108 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1109 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1110 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1112 if (env
->efer
& MSR_EFER_LMA
) {
1113 hflags
|= HF_LMA_MASK
;
1116 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1117 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1119 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1120 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1121 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1122 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1123 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
1124 (env
->eflags
& VM_MASK
) ||
1125 !(hflags
& HF_CS32_MASK
)) {
1126 hflags
|= HF_ADDSEG_MASK
;
1128 hflags
|= ((env
->segs
[R_DS
].base
|
1129 env
->segs
[R_ES
].base
|
1130 env
->segs
[R_SS
].base
) != 0) <<
1134 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1138 /* Remember to increase msrs size if you add new registers below */
1139 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1140 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1141 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1142 if (kvm_has_msr_star
)
1143 msrs
[n
++].index
= MSR_STAR
;
1144 msrs
[n
++].index
= MSR_IA32_TSC
;
1145 if (kvm_has_vm_hsave_pa
)
1146 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1147 #ifdef TARGET_X86_64
1148 if (lm_capable_kernel
) {
1149 msrs
[n
++].index
= MSR_CSTAR
;
1150 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1151 msrs
[n
++].index
= MSR_FMASK
;
1152 msrs
[n
++].index
= MSR_LSTAR
;
1155 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1156 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1160 msrs
[n
++].index
= MSR_MCG_STATUS
;
1161 msrs
[n
++].index
= MSR_MCG_CTL
;
1162 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++)
1163 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1167 rc
= kvm_get_msrs(env
, msrs
, n
);
1169 perror("kvm_get_msrs FAILED");
1172 n
= rc
; /* actual number of MSRs */
1173 for (i
=0 ; i
<n
; i
++) {
1174 if (get_msr_entry(&msrs
[i
], env
))
1178 kvm_arch_save_mpstate(env
);
1179 kvm_save_lapic(env
);
1180 kvm_get_vcpu_events(env
);
1181 kvm_get_debugregs(env
);
1184 static int _kvm_arch_init_vcpu(CPUState
*env
)
1186 kvm_arch_reset_vcpu(env
);
1189 if (((env
->cpuid_version
>> 8)&0xF) >= 6
1190 && (env
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
1191 && kvm_check_extension(kvm_state
, KVM_CAP_MCE
) > 0) {
1195 if (kvm_get_mce_cap_supported(kvm_context
, &mcg_cap
, &banks
))
1196 perror("kvm_get_mce_cap_supported FAILED");
1198 if (banks
> MCE_BANKS_DEF
)
1199 banks
= MCE_BANKS_DEF
;
1200 mcg_cap
&= MCE_CAP_DEF
;
1202 if (kvm_setup_mce(env
, &mcg_cap
))
1203 perror("kvm_setup_mce FAILED");
1205 env
->mcg_cap
= mcg_cap
;
1210 #ifdef KVM_EXIT_TPR_ACCESS
1211 kvm_enable_tpr_access_reporting(env
);
1213 kvm_reset_mpstate(env
);
1217 int kvm_arch_halt(CPUState
*env
)
1220 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1221 (env
->eflags
& IF_MASK
)) &&
1222 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1228 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1230 if (!kvm_irqchip_in_kernel())
1231 kvm_set_cr8(env
, cpu_get_apic_tpr(env
->apic_state
));
1235 int kvm_arch_has_work(CPUState
*env
)
1237 if (((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1238 (env
->eflags
& IF_MASK
)) ||
1239 (env
->interrupt_request
& CPU_INTERRUPT_NMI
))
1244 int kvm_arch_try_push_interrupts(void *opaque
)
1246 CPUState
*env
= cpu_single_env
;
1249 if (kvm_is_ready_for_interrupt_injection(env
) &&
1250 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1251 (env
->eflags
& IF_MASK
)) {
1252 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1253 irq
= cpu_get_pic_interrupt(env
);
1255 r
= kvm_inject_irq(env
, irq
);
1257 printf("cpu %d fail inject %x\n", env
->cpu_index
, irq
);
1261 return (env
->interrupt_request
& CPU_INTERRUPT_HARD
) != 0;
1264 #ifdef KVM_CAP_USER_NMI
1265 void kvm_arch_push_nmi(void *opaque
)
1267 CPUState
*env
= cpu_single_env
;
1270 if (likely(!(env
->interrupt_request
& CPU_INTERRUPT_NMI
)))
1273 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1274 r
= kvm_inject_nmi(env
);
1276 printf("cpu %d fail inject NMI\n", env
->cpu_index
);
1278 #endif /* KVM_CAP_USER_NMI */
1280 static int kvm_reset_msrs(CPUState
*env
)
1283 struct kvm_msrs info
;
1284 struct kvm_msr_entry entries
[100];
1287 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1292 for (n
= 0; n
< kvm_msr_list
->nmsrs
; n
++) {
1293 kvm_msr_entry_set(&msrs
[n
], kvm_msr_list
->indices
[n
], 0);
1296 msr_data
.info
.nmsrs
= n
;
1298 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
1302 void kvm_arch_cpu_reset(CPUState
*env
)
1304 kvm_reset_msrs(env
);
1305 kvm_arch_reset_vcpu(env
);
1306 kvm_reset_mpstate(env
);
1309 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1310 void kvm_arch_do_ioperm(void *_data
)
1312 struct ioperm_data
*data
= _data
;
1313 ioperm(data
->start_port
, data
->num
, data
->turn_on
);
1318 * Setup x86 specific IRQ routing
1320 int kvm_arch_init_irq_routing(void)
1324 if (kvm_irqchip
&& kvm_has_gsi_routing(kvm_context
)) {
1325 kvm_clear_gsi_routes(kvm_context
);
1326 for (i
= 0; i
< 8; ++i
) {
1329 r
= kvm_add_irq_route(kvm_context
, i
, KVM_IRQCHIP_PIC_MASTER
, i
);
1333 for (i
= 8; i
< 16; ++i
) {
1334 r
= kvm_add_irq_route(kvm_context
, i
, KVM_IRQCHIP_PIC_SLAVE
, i
- 8);
1338 for (i
= 0; i
< 24; ++i
) {
1340 r
= kvm_add_irq_route(kvm_context
, i
, KVM_IRQCHIP_IOAPIC
, 2);
1341 } else if (i
!= 2) {
1342 r
= kvm_add_irq_route(kvm_context
, i
, KVM_IRQCHIP_IOAPIC
, i
);
1347 kvm_commit_irq_routes(kvm_context
);
1352 void kvm_arch_process_irqchip_events(CPUState
*env
)
1354 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1355 kvm_cpu_synchronize_state(env
);
1358 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1359 kvm_cpu_synchronize_state(env
);