target-sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "hw/sh_intc.h"
  31
  32 #if defined(CONFIG_USER_ONLY)
  33
  34 void do_interrupt (CPUState *env)
  35 {
  36   env->exception_index = -1;
  37 }
  38
  39 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
  40                              int mmu_idx, int is_softmmu)
  41 {
  42     env->tea = address;
  43     env->exception_index = 0;
  44     switch (rw) {
  45     case 0:
  46         env->tea = address;
  47         env->exception_index = 0x0a0;
  48         break;
  49     case 1:
  50         env->tea = address;
  51         env->exception_index = 0x0c0;
  52         break;
  53     }
  54     return 1;
  55 }
  56
  57 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
  58 {
  59     return addr;
  60 }
  61
  62 #else /* !CONFIG_USER_ONLY */
  63
  64 #define MMU_OK                   0
  65 #define MMU_ITLB_MISS            (-1)
  66 #define MMU_ITLB_MULTIPLE        (-2)
  67 #define MMU_ITLB_VIOLATION       (-3)
  68 #define MMU_DTLB_MISS_READ       (-4)
  69 #define MMU_DTLB_MISS_WRITE      (-5)
  70 #define MMU_DTLB_INITIAL_WRITE   (-6)
  71 #define MMU_DTLB_VIOLATION_READ  (-7)
  72 #define MMU_DTLB_VIOLATION_WRITE (-8)
  73 #define MMU_DTLB_MULTIPLE        (-9)
  74 #define MMU_DTLB_MISS            (-10)
  75
  76 void do_interrupt(CPUState * env)
  77 {
  78     int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
  79     int do_exp, irq_vector = env->exception_index;
  80
  81     /* prioritize exceptions over interrupts */
  82
  83     do_exp = env->exception_index != -1;
  84     do_irq = do_irq && (env->exception_index == -1);
  85
  86     if (env->sr & SR_BL) {
  87         if (do_exp && env->exception_index != 0x1e0) {
  88             env->exception_index = 0x000; /* masked exception -> reset */
  89         }
  90         if (do_irq && !env->intr_at_halt) {
  91             return; /* masked */
  92         }
  93         env->intr_at_halt = 0;
  94     }
  95
  96     if (do_irq) {
  97         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
  98                                                 (env->sr >> 4) & 0xf);
  99         if (irq_vector == -1) {
 100             return; /* masked */
 101         }
 102     }
 103
 104     if (loglevel & CPU_LOG_INT) {
 105         const char *expname;
 106         switch (env->exception_index) {
 107         case 0x0e0:
 108             expname = "addr_error";
 109             break;
 110         case 0x040:
 111             expname = "tlb_miss";
 112             break;
 113         case 0x0a0:
 114             expname = "tlb_violation";
 115             break;
 116         case 0x180:
 117             expname = "illegal_instruction";
 118             break;
 119         case 0x1a0:
 120             expname = "slot_illegal_instruction";
 121             break;
 122         case 0x800:
 123             expname = "fpu_disable";
 124             break;
 125         case 0x820:
 126             expname = "slot_fpu";
 127             break;
 128         case 0x100:
 129             expname = "data_write";
 130             break;
 131         case 0x060:
 132             expname = "dtlb_miss_write";
 133             break;
 134         case 0x0c0:
 135             expname = "dtlb_violation_write";
 136             break;
 137         case 0x120:
 138             expname = "fpu_exception";
 139             break;
 140         case 0x080:
 141             expname = "initial_page_write";
 142             break;
 143         case 0x160:
 144             expname = "trapa";
 145             break;
 146         default:
 147             expname = do_irq ? "interrupt" : "???";
 148             break;
 149         }
 150         fprintf(logfile, "exception 0x%03x [%s] raised\n",
 151                 irq_vector, expname);
 152         cpu_dump_state(env, logfile, fprintf, 0);
 153     }
 154
 155     env->ssr = env->sr;
 156     env->spc = env->pc;
 157     env->sgr = env->gregs[15];
 158     env->sr |= SR_BL | SR_MD | SR_RB;
 159
 160     if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
 161         /* Branch instruction should be executed again before delay slot. */
 162         env->spc -= 2;
 163         /* Clear flags for exception/interrupt routine. */
 164         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
 165     }
 166     if (env->flags & DELAY_SLOT_CLEARME)
 167         env->flags = 0;
 168
 169     if (do_exp) {
 170         env->expevt = env->exception_index;
 171         switch (env->exception_index) {
 172         case 0x000:
 173         case 0x020:
 174         case 0x140:
 175             env->sr &= ~SR_FD;
 176             env->sr |= 0xf << 4; /* IMASK */
 177             env->pc = 0xa0000000;
 178             break;
 179         case 0x040:
 180         case 0x060:
 181             env->pc = env->vbr + 0x400;
 182             break;
 183         case 0x160:
 184             env->spc += 2; /* special case for TRAPA */
 185             /* fall through */
 186         default:
 187             env->pc = env->vbr + 0x100;
 188             break;
 189         }
 190         return;
 191     }
 192
 193     if (do_irq) {
 194         env->intevt = irq_vector;
 195         env->pc = env->vbr + 0x600;
 196         return;
 197     }
 198 }
 199
 200 static void update_itlb_use(CPUState * env, int itlbnb)
 201 {
 202     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 203
 204     switch (itlbnb) {
 205     case 0:
 206         and_mask = 0x1f;
 207         break;
 208     case 1:
 209         and_mask = 0xe7;
 210         or_mask = 0x80;
 211         break;
 212     case 2:
 213         and_mask = 0xfb;
 214         or_mask = 0x50;
 215         break;
 216     case 3:
 217         or_mask = 0x2c;
 218         break;
 219     }
 220
 221     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 222     env->mmucr |= (or_mask << 24);
 223 }
 224
 225 static int itlb_replacement(CPUState * env)
 226 {
 227     if ((env->mmucr & 0xe0000000) == 0xe0000000)
 228         return 0;
 229     if ((env->mmucr & 0x98000000) == 0x18000000)
 230         return 1;
 231     if ((env->mmucr & 0x54000000) == 0x04000000)
 232         return 2;
 233     if ((env->mmucr & 0x2c000000) == 0x00000000)
 234         return 3;
 235     assert(0);
 236 }
 237
 238 /* Find the corresponding entry in the right TLB
 239    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 240 */
 241 static int find_tlb_entry(CPUState * env, target_ulong address,
 242                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 243 {
 244     int match = MMU_DTLB_MISS;
 245     uint32_t start, end;
 246     uint8_t asid;
 247     int i;
 248
 249     asid = env->pteh & 0xff;
 250
 251     for (i = 0; i < nbtlb; i++) {
 252         if (!entries[i].v)
 253             continue;           /* Invalid entry */
 254         if (use_asid && entries[i].asid != asid)
 255             continue;           /* Bad ASID */
 256 #if 0
 257         switch (entries[i].sz) {
 258         case 0:
 259             size = 1024;        /* 1kB */
 260             break;
 261         case 1:
 262             size = 4 * 1024;    /* 4kB */
 263             break;
 264         case 2:
 265             size = 64 * 1024;   /* 64kB */
 266             break;
 267         case 3:
 268             size = 1024 * 1024; /* 1MB */
 269             break;
 270         default:
 271             assert(0);
 272         }
 273 #endif
 274         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 275         end = start + entries[i].size - 1;
 276         if (address >= start && address <= end) {       /* Match */
 277             if (match != MMU_DTLB_MISS)
 278                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 279             match = i;
 280         }
 281     }
 282     return match;
 283 }
 284
 285 static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
 286                                  const tlb_t * needle)
 287 {
 288     int i;
 289     for (i = 0; i < nbtlb; i++)
 290         if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
 291             return 1;
 292     return 0;
 293 }
 294
 295 static void increment_urc(CPUState * env)
 296 {
 297     uint8_t urb, urc;
 298
 299     /* Increment URC */
 300     urb = ((env->mmucr) >> 18) & 0x3f;
 301     urc = ((env->mmucr) >> 10) & 0x3f;
 302     urc++;
 303     if (urc == urb || urc == UTLB_SIZE - 1)
 304         urc = 0;
 305     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 306 }
 307
 308 /* Find itlb entry - update itlb from utlb if necessary and asked for
 309    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 310    Update the itlb from utlb if update is not 0
 311 */
 312 int find_itlb_entry(CPUState * env, target_ulong address,
 313                     int use_asid, int update)
 314 {
 315     int e, n;
 316
 317     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 318     if (e == MMU_DTLB_MULTIPLE)
 319         e = MMU_ITLB_MULTIPLE;
 320     else if (e == MMU_DTLB_MISS && update) {
 321         e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 322         if (e >= 0) {
 323             tlb_t * ientry;
 324             n = itlb_replacement(env);
 325             ientry = &env->itlb[n];
 326             if (ientry->v) {
 327                 if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
 328                     tlb_flush_page(env, ientry->vpn << 10);
 329             }
 330             *ientry = env->utlb[e];
 331             e = n;
 332         } else if (e == MMU_DTLB_MISS)
 333             e = MMU_ITLB_MISS;
 334     } else if (e == MMU_DTLB_MISS)
 335         e = MMU_ITLB_MISS;
 336     if (e >= 0)
 337         update_itlb_use(env, e);
 338     return e;
 339 }
 340
 341 /* Find utlb entry
 342    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 343 int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
 344 {
 345     /* per utlb access */
 346     increment_urc(env);
 347
 348     /* Return entry */
 349     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 350 }
 351
 352 /* Match address against MMU
 353    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 354    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 355    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 356    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
 357 */
 358 static int get_mmu_address(CPUState * env, target_ulong * physical,
 359                            int *prot, target_ulong address,
 360                            int rw, int access_type)
 361 {
 362     int use_asid, is_code, n;
 363     tlb_t *matching = NULL;
 364
 365     use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 366     is_code = env->pc == address;       /* Hack */
 367
 368     /* Use a hack to find if this is an instruction or data access */
 369     if (env->pc == address && !(rw & PAGE_WRITE)) {
 370         n = find_itlb_entry(env, address, use_asid, 1);
 371         if (n >= 0) {
 372             matching = &env->itlb[n];
 373             if ((env->sr & SR_MD) & !(matching->pr & 2))
 374                 n = MMU_ITLB_VIOLATION;
 375             else
 376                 *prot = PAGE_READ;
 377         }
 378     } else {
 379         n = find_utlb_entry(env, address, use_asid);
 380         if (n >= 0) {
 381             matching = &env->utlb[n];
 382             switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
 383             case 0:             /* 000 */
 384             case 2:             /* 010 */
 385                 n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
 386                     MMU_DTLB_VIOLATION_READ;
 387                 break;
 388             case 1:             /* 001 */
 389             case 4:             /* 100 */
 390             case 5:             /* 101 */
 391                 if (rw & PAGE_WRITE)
 392                     n = MMU_DTLB_VIOLATION_WRITE;
 393                 else
 394                     *prot = PAGE_READ;
 395                 break;
 396             case 3:             /* 011 */
 397             case 6:             /* 110 */
 398             case 7:             /* 111 */
 399                 *prot = rw & (PAGE_READ | PAGE_WRITE);
 400                 break;
 401             }
 402         } else if (n == MMU_DTLB_MISS) {
 403             n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
 404                 MMU_DTLB_MISS_READ;
 405         }
 406     }
 407     if (n >= 0) {
 408         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 409             (address & (matching->size - 1));
 410         if ((rw & PAGE_WRITE) & !matching->d)
 411             n = MMU_DTLB_INITIAL_WRITE;
 412         else
 413             n = MMU_OK;
 414     }
 415     return n;
 416 }
 417
 418 int get_physical_address(CPUState * env, target_ulong * physical,
 419                          int *prot, target_ulong address,
 420                          int rw, int access_type)
 421 {
 422     /* P1, P2 and P4 areas do not use translation */
 423     if ((address >= 0x80000000 && address < 0xc0000000) ||
 424         address >= 0xe0000000) {
 425         if (!(env->sr & SR_MD)
 426             && (address < 0xe0000000 || address > 0xe4000000)) {
 427             /* Unauthorized access in user mode (only store queues are available) */
 428             fprintf(stderr, "Unauthorized access\n");
 429             return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
 430                 MMU_DTLB_MISS_READ;
 431         }
 432         if (address >= 0x80000000 && address < 0xc0000000) {
 433             /* Mask upper 3 bits for P1 and P2 areas */
 434             *physical = address & 0x1fffffff;
 435         } else if (address >= 0xfc000000) {
 436             /*
 437              * Mask upper 3 bits for control registers in P4 area,
 438              * to unify access to control registers via P0-P3 area.
 439              * The addresses for cache store queue, TLB address array
 440              * are not masked.
 441              */
 442         *physical = address & 0x1fffffff;
 443         } else {
 444             /* access to cache store queue, or TLB address array. */
 445             *physical = address;
 446         }
 447         *prot = PAGE_READ | PAGE_WRITE;
 448         return MMU_OK;
 449     }
 450
 451     /* If MMU is disabled, return the corresponding physical page */
 452     if (!env->mmucr & MMUCR_AT) {
 453         *physical = address & 0x1FFFFFFF;
 454         *prot = PAGE_READ | PAGE_WRITE;
 455         return MMU_OK;
 456     }
 457
 458     /* We need to resort to the MMU */
 459     return get_mmu_address(env, physical, prot, address, rw, access_type);
 460 }
 461
 462 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
 463                              int mmu_idx, int is_softmmu)
 464 {
 465     target_ulong physical, page_offset, page_size;
 466     int prot, ret, access_type;
 467
 468     switch (rw) {
 469     case 0:
 470         rw = PAGE_READ;
 471         break;
 472     case 1:
 473         rw = PAGE_WRITE;
 474         break;
 475     case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */
 476         rw = PAGE_READ;
 477         break;
 478     default:
 479         /* fatal error */
 480         assert(0);
 481     }
 482
 483     /* XXXXX */
 484 #if 0
 485     fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
 486             __func__, env->pc, address, rw, mmu_idx, is_softmmu);
 487 #endif
 488
 489     access_type = ACCESS_INT;
 490     ret =
 491         get_physical_address(env, &physical, &prot, address, rw,
 492                              access_type);
 493
 494     if (ret != MMU_OK) {
 495         env->tea = address;
 496         switch (ret) {
 497         case MMU_ITLB_MISS:
 498         case MMU_DTLB_MISS_READ:
 499             env->exception_index = 0x040;
 500             break;
 501         case MMU_DTLB_MULTIPLE:
 502         case MMU_ITLB_MULTIPLE:
 503             env->exception_index = 0x140;
 504             break;
 505         case MMU_ITLB_VIOLATION:
 506             env->exception_index = 0x0a0;
 507             break;
 508         case MMU_DTLB_MISS_WRITE:
 509             env->exception_index = 0x060;
 510             break;
 511         case MMU_DTLB_INITIAL_WRITE:
 512             env->exception_index = 0x080;
 513             break;
 514         case MMU_DTLB_VIOLATION_READ:
 515             env->exception_index = 0x0a0;
 516             break;
 517         case MMU_DTLB_VIOLATION_WRITE:
 518             env->exception_index = 0x0c0;
 519             break;
 520         default:
 521             assert(0);
 522         }
 523         return 1;
 524     }
 525
 526     page_size = TARGET_PAGE_SIZE;
 527     page_offset =
 528         (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
 529     address = (address & TARGET_PAGE_MASK) + page_offset;
 530     physical = (physical & TARGET_PAGE_MASK) + page_offset;
 531
 532     return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
 533 }
 534
 535 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
 536 {
 537     target_ulong physical;
 538     int prot;
 539
 540     get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
 541     return physical;
 542 }
 543
 544 void cpu_load_tlb(CPUState * env)
 545 {
 546     int n = cpu_mmucr_urc(env->mmucr);
 547     tlb_t * entry = &env->utlb[n];
 548
 549     if (entry->v) {
 550         /* Overwriting valid entry in utlb. */
 551         target_ulong address = entry->vpn << 10;
 552         if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
 553             tlb_flush_page(env, address);
 554         }
 555     }
 556
 557     /* per utlb access cannot implemented. */
 558     increment_urc(env);
 559
 560     /* Take values into cpu status from registers. */
 561     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 562     entry->vpn  = cpu_pteh_vpn(env->pteh);
 563     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 564     entry->ppn  = cpu_ptel_ppn(env->ptel);
 565     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 566     switch (entry->sz) {
 567     case 0: /* 00 */
 568         entry->size = 1024; /* 1K */
 569         break;
 570     case 1: /* 01 */
 571         entry->size = 1024 * 4; /* 4K */
 572         break;
 573     case 2: /* 10 */
 574         entry->size = 1024 * 64; /* 64K */
 575         break;
 576     case 3: /* 11 */
 577         entry->size = 1024 * 1024; /* 1M */
 578         break;
 579     default:
 580         assert(0);
 581         break;
 582     }
 583     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 584     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 585     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 586     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 587     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 588     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 589     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 590 }
 591
 592 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
 593                                     uint32_t mem_value)
 594 {
 595     int associate = addr & 0x0000080;
 596     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 597     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 598     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 599     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 600
 601     if (associate) {
 602         int i;
 603         tlb_t * utlb_match_entry = NULL;
 604         int needs_tlb_flush = 0;
 605
 606         /* search UTLB */
 607         for (i = 0; i < UTLB_SIZE; i++) {
 608             tlb_t * entry = &s->utlb[i];
 609             if (!entry->v)
 610                 continue;
 611
 612             if (entry->vpn == vpn && entry->asid == asid) {
 613                 if (utlb_match_entry) {
 614                     /* Multiple TLB Exception */
 615                     s->exception_index = 0x140;
 616                     s->tea = addr;
 617                     break;
 618                 }
 619                 if (entry->v && !v)
 620                     needs_tlb_flush = 1;
 621                 entry->v = v;
 622                 entry->d = d;
 623                 utlb_match_entry = entry;
 624             }
 625             increment_urc(s); /* per utlb access */
 626         }
 627
 628         /* search ITLB */
 629         for (i = 0; i < ITLB_SIZE; i++) {
 630             tlb_t * entry = &s->itlb[i];
 631             if (entry->vpn == vpn && entry->asid == asid) {
 632                 if (entry->v && !v)
 633                     needs_tlb_flush = 1;
 634                 if (utlb_match_entry)
 635                     *entry = *utlb_match_entry;
 636                 else
 637                     entry->v = v;
 638                 break;
 639             }
 640         }
 641
 642         if (needs_tlb_flush)
 643             tlb_flush_page(s, vpn << 10);
 644
 645     } else {
 646         int index = (addr & 0x00003f00) >> 8;
 647         tlb_t * entry = &s->utlb[index];
 648         if (entry->v) {
 649             /* Overwriting valid entry in utlb. */
 650             target_ulong address = entry->vpn << 10;
 651             if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
 652                 tlb_flush_page(s, address);
 653             }
 654         }
 655         entry->asid = asid;
 656         entry->vpn = vpn;
 657         entry->d = d;
 658         entry->v = v;
 659         increment_urc(s);
 660     }
 661 }
 662
 663 #endif