2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-timer.h"
28 #include "sparc32_dma.h"
33 #include "firmware_abi.h"
39 #include "qdev-addr.h"
44 * Sun4m architecture was used in the following machines:
46 * SPARCserver 6xxMP/xx
47 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
48 * SPARCclassic X (4/10)
49 * SPARCstation LX/ZX (4/30)
50 * SPARCstation Voyager
51 * SPARCstation 10/xx, SPARCserver 10/xx
52 * SPARCstation 5, SPARCserver 5
53 * SPARCstation 20/xx, SPARCserver 20
56 * Sun4d architecture was used in the following machines:
61 * Sun4c architecture was used in the following machines:
62 * SPARCstation 1/1+, SPARCserver 1/1+
68 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 #define DPRINTF(fmt, ...) \
73 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
75 #define DPRINTF(fmt, ...)
78 #define KERNEL_LOAD_ADDR 0x00004000
79 #define CMDLINE_ADDR 0x007ff000
80 #define INITRD_LOAD_ADDR 0x00800000
81 #define PROM_SIZE_MAX (1024 * 1024)
82 #define PROM_VADDR 0xffd00000
83 #define PROM_FILENAME "openbios-sparc32"
84 #define CFG_ADDR 0xd00000510ULL
85 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
90 #define ESCC_CLOCK 4915200
93 target_phys_addr_t iommu_base
, slavio_base
;
94 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
95 target_phys_addr_t serial_base
, fd_base
;
96 target_phys_addr_t idreg_base
, dma_base
, esp_base
, le_base
;
97 target_phys_addr_t tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
98 target_phys_addr_t ecc_base
;
100 uint8_t nvram_machine_id
;
102 uint32_t iommu_version
;
104 const char * const default_cpu_model
;
107 #define MAX_IOUNITS 5
110 target_phys_addr_t iounit_bases
[MAX_IOUNITS
], slavio_base
;
111 target_phys_addr_t counter_base
, nvram_base
, ms_kb_base
;
112 target_phys_addr_t serial_base
;
113 target_phys_addr_t espdma_base
, esp_base
;
114 target_phys_addr_t ledma_base
, le_base
;
115 target_phys_addr_t tcx_base
;
116 target_phys_addr_t sbi_base
;
117 uint8_t nvram_machine_id
;
119 uint32_t iounit_version
;
121 const char * const default_cpu_model
;
125 target_phys_addr_t iommu_base
, slavio_base
;
126 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
127 target_phys_addr_t serial_base
, fd_base
;
128 target_phys_addr_t idreg_base
, dma_base
, esp_base
, le_base
;
129 target_phys_addr_t tcx_base
, aux1_base
;
130 uint8_t nvram_machine_id
;
132 uint32_t iommu_version
;
134 const char * const default_cpu_model
;
137 int DMA_get_channel_mode (int nchan
)
141 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
145 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
149 void DMA_hold_DREQ (int nchan
) {}
150 void DMA_release_DREQ (int nchan
) {}
151 void DMA_schedule(int nchan
) {}
152 void DMA_init (int high_page_enable
) {}
153 void DMA_register_channel (int nchan
,
154 DMA_transfer_handler transfer_handler
,
159 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
161 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
165 static void nvram_init(m48t59_t
*nvram
, uint8_t *macaddr
, const char *cmdline
,
166 const char *boot_devices
, ram_addr_t RAM_size
,
167 uint32_t kernel_size
,
168 int width
, int height
, int depth
,
169 int nvram_machine_id
, const char *arch
)
173 uint8_t image
[0x1ff0];
174 struct OpenBIOS_nvpart_v1
*part_header
;
176 memset(image
, '\0', sizeof(image
));
180 // OpenBIOS nvram variables
181 // Variable partition
182 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
183 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
184 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
186 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
187 for (i
= 0; i
< nb_prom_envs
; i
++)
188 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
193 end
= start
+ ((end
- start
+ 15) & ~15);
194 OpenBIOS_finish_partition(part_header
, end
- start
);
198 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
199 part_header
->signature
= OPENBIOS_PART_FREE
;
200 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
203 OpenBIOS_finish_partition(part_header
, end
- start
);
205 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
208 for (i
= 0; i
< sizeof(image
); i
++)
209 m48t59_write(nvram
, i
, image
[i
]);
212 static void *slavio_intctl
;
214 void pic_info(Monitor
*mon
)
217 slavio_pic_info(mon
, slavio_intctl
);
220 void irq_info(Monitor
*mon
)
223 slavio_irq_info(mon
, slavio_intctl
);
226 void cpu_check_irqs(CPUState
*env
)
228 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
229 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
232 for (i
= 15; i
> 0; i
--) {
233 if (env
->pil_in
& (1 << i
)) {
234 int old_interrupt
= env
->interrupt_index
;
236 env
->interrupt_index
= TT_EXTINT
| i
;
237 if (old_interrupt
!= env
->interrupt_index
) {
238 DPRINTF("Set CPU IRQ %d\n", i
);
239 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
244 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
245 DPRINTF("Reset CPU IRQ %d\n", env
->interrupt_index
& 15);
246 env
->interrupt_index
= 0;
247 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
251 static void cpu_set_irq(void *opaque
, int irq
, int level
)
253 CPUState
*env
= opaque
;
256 DPRINTF("Raise CPU IRQ %d\n", irq
);
258 env
->pil_in
|= 1 << irq
;
261 DPRINTF("Lower CPU IRQ %d\n", irq
);
262 env
->pil_in
&= ~(1 << irq
);
267 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
271 static void main_cpu_reset(void *opaque
)
273 CPUState
*env
= opaque
;
279 static void secondary_cpu_reset(void *opaque
)
281 CPUState
*env
= opaque
;
287 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
289 if (level
&& cpu_single_env
)
290 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
293 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
294 const char *initrd_filename
,
299 long initrd_size
, kernel_size
;
301 linux_boot
= (kernel_filename
!= NULL
);
305 kernel_size
= load_elf(kernel_filename
, -0xf0000000ULL
, NULL
, NULL
,
308 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
309 RAM_size
- KERNEL_LOAD_ADDR
);
311 kernel_size
= load_image_targphys(kernel_filename
,
313 RAM_size
- KERNEL_LOAD_ADDR
);
314 if (kernel_size
< 0) {
315 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
322 if (initrd_filename
) {
323 initrd_size
= load_image_targphys(initrd_filename
,
325 RAM_size
- INITRD_LOAD_ADDR
);
326 if (initrd_size
< 0) {
327 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
332 if (initrd_size
> 0) {
333 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
334 if (ldl_phys(KERNEL_LOAD_ADDR
+ i
) == 0x48647253) { // HdrS
335 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 16, INITRD_LOAD_ADDR
);
336 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 20, initrd_size
);
345 static void *iommu_init(target_phys_addr_t addr
, uint32_t version
, qemu_irq irq
)
350 dev
= qdev_create(NULL
, "iommu");
351 qdev_prop_set_uint32(dev
, "version", version
);
353 s
= sysbus_from_qdev(dev
);
354 sysbus_connect_irq(s
, 0, irq
);
355 sysbus_mmio_map(s
, 0, addr
);
360 static void *sparc32_dma_init(target_phys_addr_t daddr
, qemu_irq parent_irq
,
361 void *iommu
, qemu_irq
*dev_irq
)
366 dev
= qdev_create(NULL
, "sparc32_dma");
367 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
369 s
= sysbus_from_qdev(dev
);
370 sysbus_connect_irq(s
, 0, parent_irq
);
371 *dev_irq
= qdev_get_gpio_in(dev
, 0);
372 sysbus_mmio_map(s
, 0, daddr
);
377 static void lance_init(NICInfo
*nd
, target_phys_addr_t leaddr
,
378 void *dma_opaque
, qemu_irq irq
)
384 qemu_check_nic_model(&nd_table
[0], "lance");
386 dev
= qdev_create(NULL
, "lance");
388 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
390 s
= sysbus_from_qdev(dev
);
391 sysbus_mmio_map(s
, 0, leaddr
);
392 sysbus_connect_irq(s
, 0, irq
);
393 reset
= qdev_get_gpio_in(dev
, 0);
394 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
397 static DeviceState
*slavio_intctl_init(target_phys_addr_t addr
,
398 target_phys_addr_t addrg
,
399 qemu_irq
**parent_irq
,
400 unsigned int cputimer
)
406 dev
= qdev_create(NULL
, "slavio_intctl");
407 qdev_prop_set_uint32(dev
, "cputimer_bit", cputimer
);
410 s
= sysbus_from_qdev(dev
);
412 for (i
= 0; i
< MAX_CPUS
; i
++) {
413 for (j
= 0; j
< MAX_PILS
; j
++) {
414 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
417 sysbus_mmio_map(s
, 0, addrg
);
418 for (i
= 0; i
< MAX_CPUS
; i
++) {
419 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
425 #define SYS_TIMER_OFFSET 0x10000ULL
426 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
428 static void slavio_timer_init_all(target_phys_addr_t addr
, qemu_irq master_irq
,
429 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
435 dev
= qdev_create(NULL
, "slavio_timer");
436 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
438 s
= sysbus_from_qdev(dev
);
439 sysbus_connect_irq(s
, 0, master_irq
);
440 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
442 for (i
= 0; i
< MAX_CPUS
; i
++) {
443 sysbus_mmio_map(s
, i
+ 1, addr
+ (target_phys_addr_t
)CPU_TIMER_OFFSET(i
));
444 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
448 #define MISC_LEDS 0x01600000
449 #define MISC_CFG 0x01800000
450 #define MISC_DIAG 0x01a00000
451 #define MISC_MDM 0x01b00000
452 #define MISC_SYS 0x01f00000
454 static void slavio_misc_init(target_phys_addr_t base
,
455 target_phys_addr_t aux1_base
,
456 target_phys_addr_t aux2_base
, qemu_irq irq
,
462 dev
= qdev_create(NULL
, "slavio_misc");
464 s
= sysbus_from_qdev(dev
);
466 /* 8 bit registers */
468 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
470 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
472 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
473 /* 16 bit registers */
474 /* ss600mp diag LEDs */
475 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
476 /* 32 bit registers */
478 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
481 /* AUX 1 (Misc System Functions) */
482 sysbus_mmio_map(s
, 5, aux1_base
);
485 /* AUX 2 (Software Powerdown Control) */
486 sysbus_mmio_map(s
, 6, aux2_base
);
488 sysbus_connect_irq(s
, 0, irq
);
489 sysbus_connect_irq(s
, 1, fdc_tc
);
490 qemu_system_powerdown
= qdev_get_gpio_in(dev
, 0);
493 static void ecc_init(target_phys_addr_t base
, qemu_irq irq
, uint32_t version
)
498 dev
= qdev_create(NULL
, "eccmemctl");
499 qdev_prop_set_uint32(dev
, "version", version
);
501 s
= sysbus_from_qdev(dev
);
502 sysbus_connect_irq(s
, 0, irq
);
503 sysbus_mmio_map(s
, 0, base
);
504 if (version
== 0) { // SS-600MP only
505 sysbus_mmio_map(s
, 1, base
+ 0x1000);
509 static void apc_init(target_phys_addr_t power_base
, qemu_irq cpu_halt
)
514 dev
= qdev_create(NULL
, "apc");
516 s
= sysbus_from_qdev(dev
);
517 /* Power management (APC) XXX: not a Slavio device */
518 sysbus_mmio_map(s
, 0, power_base
);
519 sysbus_connect_irq(s
, 0, cpu_halt
);
522 static void tcx_init(target_phys_addr_t addr
, int vram_size
, int width
,
523 int height
, int depth
)
528 dev
= qdev_create(NULL
, "SUNW,tcx");
529 qdev_prop_set_taddr(dev
, "addr", addr
);
530 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
531 qdev_prop_set_uint16(dev
, "width", width
);
532 qdev_prop_set_uint16(dev
, "height", height
);
533 qdev_prop_set_uint16(dev
, "depth", depth
);
535 s
= sysbus_from_qdev(dev
);
537 sysbus_mmio_map(s
, 0, addr
+ 0x00800000ULL
);
539 sysbus_mmio_map(s
, 1, addr
+ 0x00200000ULL
);
541 sysbus_mmio_map(s
, 2, addr
+ 0x00700000ULL
);
542 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
543 sysbus_mmio_map(s
, 3, addr
+ 0x00301000ULL
);
546 sysbus_mmio_map(s
, 4, addr
+ 0x02000000ULL
);
548 sysbus_mmio_map(s
, 5, addr
+ 0x0a000000ULL
);
550 /* THC 8 bit (dummy) */
551 sysbus_mmio_map(s
, 4, addr
+ 0x00300000ULL
);
555 /* NCR89C100/MACIO Internal ID register */
556 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
558 static void idreg_init(target_phys_addr_t addr
)
563 dev
= qdev_create(NULL
, "macio_idreg");
565 s
= sysbus_from_qdev(dev
);
567 sysbus_mmio_map(s
, 0, addr
);
568 cpu_physical_memory_write_rom(addr
, idreg_data
, sizeof(idreg_data
));
571 static void idreg_init1(SysBusDevice
*dev
)
573 ram_addr_t idreg_offset
;
575 idreg_offset
= qemu_ram_alloc(sizeof(idreg_data
));
576 sysbus_init_mmio(dev
, sizeof(idreg_data
), idreg_offset
| IO_MEM_ROM
);
579 static SysBusDeviceInfo idreg_info
= {
581 .qdev
.name
= "macio_idreg",
582 .qdev
.size
= sizeof(SysBusDevice
),
585 static void idreg_register_devices(void)
587 sysbus_register_withprop(&idreg_info
);
590 device_init(idreg_register_devices
);
592 /* Boot PROM (OpenBIOS) */
593 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
600 dev
= qdev_create(NULL
, "openprom");
602 s
= sysbus_from_qdev(dev
);
604 sysbus_mmio_map(s
, 0, addr
);
607 if (bios_name
== NULL
) {
608 bios_name
= PROM_FILENAME
;
610 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
612 ret
= load_elf(filename
, addr
- PROM_VADDR
, NULL
, NULL
, NULL
);
613 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
614 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
620 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
621 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
626 static void prom_init1(SysBusDevice
*dev
)
628 ram_addr_t prom_offset
;
630 prom_offset
= qemu_ram_alloc(PROM_SIZE_MAX
);
631 sysbus_init_mmio(dev
, PROM_SIZE_MAX
, prom_offset
| IO_MEM_ROM
);
634 static SysBusDeviceInfo prom_info
= {
636 .qdev
.name
= "openprom",
637 .qdev
.size
= sizeof(SysBusDevice
),
638 .qdev
.props
= (Property
[]) {
639 {/* end of property list */}
643 static void prom_register_devices(void)
645 sysbus_register_withprop(&prom_info
);
648 device_init(prom_register_devices
);
650 typedef struct RamDevice
657 static void ram_init1(SysBusDevice
*dev
)
659 ram_addr_t RAM_size
, ram_offset
;
660 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
664 ram_offset
= qemu_ram_alloc(RAM_size
);
665 sysbus_init_mmio(dev
, RAM_size
, ram_offset
);
668 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
,
676 if ((uint64_t)RAM_size
> max_mem
) {
678 "qemu: Too much memory for this machine: %d, maximum %d\n",
679 (unsigned int)(RAM_size
/ (1024 * 1024)),
680 (unsigned int)(max_mem
/ (1024 * 1024)));
683 dev
= qdev_create(NULL
, "memory");
684 s
= sysbus_from_qdev(dev
);
686 d
= FROM_SYSBUS(RamDevice
, s
);
690 sysbus_mmio_map(s
, 0, addr
);
693 static SysBusDeviceInfo ram_info
= {
695 .qdev
.name
= "memory",
696 .qdev
.size
= sizeof(RamDevice
),
697 .qdev
.props
= (Property
[]) {
700 .info
= &qdev_prop_uint64
,
701 .offset
= offsetof(RamDevice
, size
),
703 {/* end of property list */}
707 static void ram_register_devices(void)
709 sysbus_register_withprop(&ram_info
);
712 device_init(ram_register_devices
);
714 static CPUState
*cpu_devinit(const char *cpu_model
, unsigned int id
,
715 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
719 env
= cpu_init(cpu_model
);
721 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
725 cpu_sparc_set_id(env
, id
);
727 qemu_register_reset(main_cpu_reset
, env
);
729 qemu_register_reset(secondary_cpu_reset
, env
);
732 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
733 env
->prom_addr
= prom_addr
;
738 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
, ram_addr_t RAM_size
,
739 const char *boot_device
,
740 const char *kernel_filename
,
741 const char *kernel_cmdline
,
742 const char *initrd_filename
, const char *cpu_model
)
744 CPUState
*envs
[MAX_CPUS
];
746 void *iommu
, *espdma
, *ledma
, *nvram
;
747 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
748 espdma_irq
, ledma_irq
;
752 unsigned long kernel_size
;
753 BlockDriverState
*fd
[MAX_FD
];
760 cpu_model
= hwdef
->default_cpu_model
;
762 for(i
= 0; i
< smp_cpus
; i
++) {
763 envs
[i
] = cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
766 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
767 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
771 ram_init(0, RAM_size
, hwdef
->max_mem
);
773 prom_init(hwdef
->slavio_base
, bios_name
);
775 dev
= slavio_intctl_init(hwdef
->intctl_base
,
776 hwdef
->intctl_base
+ 0x10000ULL
,
780 for (i
= 0; i
< 32; i
++) {
781 slavio_irq
[i
] = qdev_get_gpio_in(dev
, i
);
783 for (i
= 0; i
< MAX_CPUS
; i
++) {
784 slavio_cpu_irq
[i
] = qdev_get_gpio_in(dev
, 32 + i
);
787 if (hwdef
->idreg_base
) {
788 idreg_init(hwdef
->idreg_base
);
791 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
794 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
797 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
798 slavio_irq
[16], iommu
, &ledma_irq
);
800 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
801 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
804 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
807 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
809 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
811 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
813 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
814 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
815 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
816 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
817 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
818 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
820 cpu_halt
= qemu_allocate_irqs(cpu_halt_signal
, NULL
, 1);
821 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
822 slavio_irq
[30], fdc_tc
);
824 if (hwdef
->apc_base
) {
825 apc_init(hwdef
->apc_base
, cpu_halt
[0]);
828 if (hwdef
->fd_base
) {
829 /* there is zero or one floppy drive */
830 memset(fd
, 0, sizeof(fd
));
831 dinfo
= drive_get(IF_FLOPPY
, 0, 0);
835 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
839 if (drive_get_max_bus(IF_SCSI
) > 0) {
840 fprintf(stderr
, "qemu: too many SCSI bus\n");
844 esp_reset
= qdev_get_gpio_in(espdma
, 0);
845 esp_init(hwdef
->esp_base
, 2,
846 espdma_memory_read
, espdma_memory_write
,
847 espdma
, espdma_irq
, &esp_reset
);
850 if (hwdef
->cs_base
) {
851 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
855 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
858 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
859 boot_device
, RAM_size
, kernel_size
, graphic_width
,
860 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
864 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
867 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
868 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
869 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
870 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
871 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
872 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
873 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
874 if (kernel_cmdline
) {
875 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
876 pstrcpy_targphys(CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
878 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
880 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
881 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
882 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
883 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
901 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
904 .iommu_base
= 0x10000000,
905 .tcx_base
= 0x50000000,
906 .cs_base
= 0x6c000000,
907 .slavio_base
= 0x70000000,
908 .ms_kb_base
= 0x71000000,
909 .serial_base
= 0x71100000,
910 .nvram_base
= 0x71200000,
911 .fd_base
= 0x71400000,
912 .counter_base
= 0x71d00000,
913 .intctl_base
= 0x71e00000,
914 .idreg_base
= 0x78000000,
915 .dma_base
= 0x78400000,
916 .esp_base
= 0x78800000,
917 .le_base
= 0x78c00000,
918 .apc_base
= 0x6a000000,
919 .aux1_base
= 0x71900000,
920 .aux2_base
= 0x71910000,
921 .nvram_machine_id
= 0x80,
922 .machine_id
= ss5_id
,
923 .iommu_version
= 0x05000000,
924 .max_mem
= 0x10000000,
925 .default_cpu_model
= "Fujitsu MB86904",
929 .iommu_base
= 0xfe0000000ULL
,
930 .tcx_base
= 0xe20000000ULL
,
931 .slavio_base
= 0xff0000000ULL
,
932 .ms_kb_base
= 0xff1000000ULL
,
933 .serial_base
= 0xff1100000ULL
,
934 .nvram_base
= 0xff1200000ULL
,
935 .fd_base
= 0xff1700000ULL
,
936 .counter_base
= 0xff1300000ULL
,
937 .intctl_base
= 0xff1400000ULL
,
938 .idreg_base
= 0xef0000000ULL
,
939 .dma_base
= 0xef0400000ULL
,
940 .esp_base
= 0xef0800000ULL
,
941 .le_base
= 0xef0c00000ULL
,
942 .apc_base
= 0xefa000000ULL
, // XXX should not exist
943 .aux1_base
= 0xff1800000ULL
,
944 .aux2_base
= 0xff1a01000ULL
,
945 .ecc_base
= 0xf00000000ULL
,
946 .ecc_version
= 0x10000000, // version 0, implementation 1
947 .nvram_machine_id
= 0x72,
948 .machine_id
= ss10_id
,
949 .iommu_version
= 0x03000000,
950 .max_mem
= 0xf00000000ULL
,
951 .default_cpu_model
= "TI SuperSparc II",
955 .iommu_base
= 0xfe0000000ULL
,
956 .tcx_base
= 0xe20000000ULL
,
957 .slavio_base
= 0xff0000000ULL
,
958 .ms_kb_base
= 0xff1000000ULL
,
959 .serial_base
= 0xff1100000ULL
,
960 .nvram_base
= 0xff1200000ULL
,
961 .counter_base
= 0xff1300000ULL
,
962 .intctl_base
= 0xff1400000ULL
,
963 .dma_base
= 0xef0081000ULL
,
964 .esp_base
= 0xef0080000ULL
,
965 .le_base
= 0xef0060000ULL
,
966 .apc_base
= 0xefa000000ULL
, // XXX should not exist
967 .aux1_base
= 0xff1800000ULL
,
968 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
969 .ecc_base
= 0xf00000000ULL
,
970 .ecc_version
= 0x00000000, // version 0, implementation 0
971 .nvram_machine_id
= 0x71,
972 .machine_id
= ss600mp_id
,
973 .iommu_version
= 0x01000000,
974 .max_mem
= 0xf00000000ULL
,
975 .default_cpu_model
= "TI SuperSparc II",
979 .iommu_base
= 0xfe0000000ULL
,
980 .tcx_base
= 0xe20000000ULL
,
981 .slavio_base
= 0xff0000000ULL
,
982 .ms_kb_base
= 0xff1000000ULL
,
983 .serial_base
= 0xff1100000ULL
,
984 .nvram_base
= 0xff1200000ULL
,
985 .fd_base
= 0xff1700000ULL
,
986 .counter_base
= 0xff1300000ULL
,
987 .intctl_base
= 0xff1400000ULL
,
988 .idreg_base
= 0xef0000000ULL
,
989 .dma_base
= 0xef0400000ULL
,
990 .esp_base
= 0xef0800000ULL
,
991 .le_base
= 0xef0c00000ULL
,
992 .apc_base
= 0xefa000000ULL
, // XXX should not exist
993 .aux1_base
= 0xff1800000ULL
,
994 .aux2_base
= 0xff1a01000ULL
,
995 .ecc_base
= 0xf00000000ULL
,
996 .ecc_version
= 0x20000000, // version 0, implementation 2
997 .nvram_machine_id
= 0x72,
998 .machine_id
= ss20_id
,
999 .iommu_version
= 0x13000000,
1000 .max_mem
= 0xf00000000ULL
,
1001 .default_cpu_model
= "TI SuperSparc II",
1005 .iommu_base
= 0x10000000,
1006 .tcx_base
= 0x50000000,
1007 .slavio_base
= 0x70000000,
1008 .ms_kb_base
= 0x71000000,
1009 .serial_base
= 0x71100000,
1010 .nvram_base
= 0x71200000,
1011 .fd_base
= 0x71400000,
1012 .counter_base
= 0x71d00000,
1013 .intctl_base
= 0x71e00000,
1014 .idreg_base
= 0x78000000,
1015 .dma_base
= 0x78400000,
1016 .esp_base
= 0x78800000,
1017 .le_base
= 0x78c00000,
1018 .apc_base
= 0x71300000, // pmc
1019 .aux1_base
= 0x71900000,
1020 .aux2_base
= 0x71910000,
1021 .nvram_machine_id
= 0x80,
1022 .machine_id
= vger_id
,
1023 .iommu_version
= 0x05000000,
1024 .max_mem
= 0x10000000,
1025 .default_cpu_model
= "Fujitsu MB86904",
1029 .iommu_base
= 0x10000000,
1030 .tcx_base
= 0x50000000,
1031 .slavio_base
= 0x70000000,
1032 .ms_kb_base
= 0x71000000,
1033 .serial_base
= 0x71100000,
1034 .nvram_base
= 0x71200000,
1035 .fd_base
= 0x71400000,
1036 .counter_base
= 0x71d00000,
1037 .intctl_base
= 0x71e00000,
1038 .idreg_base
= 0x78000000,
1039 .dma_base
= 0x78400000,
1040 .esp_base
= 0x78800000,
1041 .le_base
= 0x78c00000,
1042 .aux1_base
= 0x71900000,
1043 .aux2_base
= 0x71910000,
1044 .nvram_machine_id
= 0x80,
1045 .machine_id
= lx_id
,
1046 .iommu_version
= 0x04000000,
1047 .max_mem
= 0x10000000,
1048 .default_cpu_model
= "TI MicroSparc I",
1052 .iommu_base
= 0x10000000,
1053 .tcx_base
= 0x50000000,
1054 .cs_base
= 0x6c000000,
1055 .slavio_base
= 0x70000000,
1056 .ms_kb_base
= 0x71000000,
1057 .serial_base
= 0x71100000,
1058 .nvram_base
= 0x71200000,
1059 .fd_base
= 0x71400000,
1060 .counter_base
= 0x71d00000,
1061 .intctl_base
= 0x71e00000,
1062 .idreg_base
= 0x78000000,
1063 .dma_base
= 0x78400000,
1064 .esp_base
= 0x78800000,
1065 .le_base
= 0x78c00000,
1066 .apc_base
= 0x6a000000,
1067 .aux1_base
= 0x71900000,
1068 .aux2_base
= 0x71910000,
1069 .nvram_machine_id
= 0x80,
1070 .machine_id
= ss4_id
,
1071 .iommu_version
= 0x05000000,
1072 .max_mem
= 0x10000000,
1073 .default_cpu_model
= "Fujitsu MB86904",
1077 .iommu_base
= 0x10000000,
1078 .tcx_base
= 0x50000000,
1079 .slavio_base
= 0x70000000,
1080 .ms_kb_base
= 0x71000000,
1081 .serial_base
= 0x71100000,
1082 .nvram_base
= 0x71200000,
1083 .fd_base
= 0x71400000,
1084 .counter_base
= 0x71d00000,
1085 .intctl_base
= 0x71e00000,
1086 .idreg_base
= 0x78000000,
1087 .dma_base
= 0x78400000,
1088 .esp_base
= 0x78800000,
1089 .le_base
= 0x78c00000,
1090 .apc_base
= 0x6a000000,
1091 .aux1_base
= 0x71900000,
1092 .aux2_base
= 0x71910000,
1093 .nvram_machine_id
= 0x80,
1094 .machine_id
= scls_id
,
1095 .iommu_version
= 0x05000000,
1096 .max_mem
= 0x10000000,
1097 .default_cpu_model
= "TI MicroSparc I",
1101 .iommu_base
= 0x10000000,
1102 .tcx_base
= 0x50000000, // XXX
1103 .slavio_base
= 0x70000000,
1104 .ms_kb_base
= 0x71000000,
1105 .serial_base
= 0x71100000,
1106 .nvram_base
= 0x71200000,
1107 .fd_base
= 0x71400000,
1108 .counter_base
= 0x71d00000,
1109 .intctl_base
= 0x71e00000,
1110 .idreg_base
= 0x78000000,
1111 .dma_base
= 0x78400000,
1112 .esp_base
= 0x78800000,
1113 .le_base
= 0x78c00000,
1114 .apc_base
= 0x6a000000,
1115 .aux1_base
= 0x71900000,
1116 .aux2_base
= 0x71910000,
1117 .nvram_machine_id
= 0x80,
1118 .machine_id
= sbook_id
,
1119 .iommu_version
= 0x05000000,
1120 .max_mem
= 0x10000000,
1121 .default_cpu_model
= "TI MicroSparc I",
1125 /* SPARCstation 5 hardware initialisation */
1126 static void ss5_init(ram_addr_t RAM_size
,
1127 const char *boot_device
,
1128 const char *kernel_filename
, const char *kernel_cmdline
,
1129 const char *initrd_filename
, const char *cpu_model
)
1131 sun4m_hw_init(&sun4m_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1132 kernel_cmdline
, initrd_filename
, cpu_model
);
1135 /* SPARCstation 10 hardware initialisation */
1136 static void ss10_init(ram_addr_t RAM_size
,
1137 const char *boot_device
,
1138 const char *kernel_filename
, const char *kernel_cmdline
,
1139 const char *initrd_filename
, const char *cpu_model
)
1141 sun4m_hw_init(&sun4m_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1142 kernel_cmdline
, initrd_filename
, cpu_model
);
1145 /* SPARCserver 600MP hardware initialisation */
1146 static void ss600mp_init(ram_addr_t RAM_size
,
1147 const char *boot_device
,
1148 const char *kernel_filename
,
1149 const char *kernel_cmdline
,
1150 const char *initrd_filename
, const char *cpu_model
)
1152 sun4m_hw_init(&sun4m_hwdefs
[2], RAM_size
, boot_device
, kernel_filename
,
1153 kernel_cmdline
, initrd_filename
, cpu_model
);
1156 /* SPARCstation 20 hardware initialisation */
1157 static void ss20_init(ram_addr_t RAM_size
,
1158 const char *boot_device
,
1159 const char *kernel_filename
, const char *kernel_cmdline
,
1160 const char *initrd_filename
, const char *cpu_model
)
1162 sun4m_hw_init(&sun4m_hwdefs
[3], RAM_size
, boot_device
, kernel_filename
,
1163 kernel_cmdline
, initrd_filename
, cpu_model
);
1166 /* SPARCstation Voyager hardware initialisation */
1167 static void vger_init(ram_addr_t RAM_size
,
1168 const char *boot_device
,
1169 const char *kernel_filename
, const char *kernel_cmdline
,
1170 const char *initrd_filename
, const char *cpu_model
)
1172 sun4m_hw_init(&sun4m_hwdefs
[4], RAM_size
, boot_device
, kernel_filename
,
1173 kernel_cmdline
, initrd_filename
, cpu_model
);
1176 /* SPARCstation LX hardware initialisation */
1177 static void ss_lx_init(ram_addr_t RAM_size
,
1178 const char *boot_device
,
1179 const char *kernel_filename
, const char *kernel_cmdline
,
1180 const char *initrd_filename
, const char *cpu_model
)
1182 sun4m_hw_init(&sun4m_hwdefs
[5], RAM_size
, boot_device
, kernel_filename
,
1183 kernel_cmdline
, initrd_filename
, cpu_model
);
1186 /* SPARCstation 4 hardware initialisation */
1187 static void ss4_init(ram_addr_t RAM_size
,
1188 const char *boot_device
,
1189 const char *kernel_filename
, const char *kernel_cmdline
,
1190 const char *initrd_filename
, const char *cpu_model
)
1192 sun4m_hw_init(&sun4m_hwdefs
[6], RAM_size
, boot_device
, kernel_filename
,
1193 kernel_cmdline
, initrd_filename
, cpu_model
);
1196 /* SPARCClassic hardware initialisation */
1197 static void scls_init(ram_addr_t RAM_size
,
1198 const char *boot_device
,
1199 const char *kernel_filename
, const char *kernel_cmdline
,
1200 const char *initrd_filename
, const char *cpu_model
)
1202 sun4m_hw_init(&sun4m_hwdefs
[7], RAM_size
, boot_device
, kernel_filename
,
1203 kernel_cmdline
, initrd_filename
, cpu_model
);
1206 /* SPARCbook hardware initialisation */
1207 static void sbook_init(ram_addr_t RAM_size
,
1208 const char *boot_device
,
1209 const char *kernel_filename
, const char *kernel_cmdline
,
1210 const char *initrd_filename
, const char *cpu_model
)
1212 sun4m_hw_init(&sun4m_hwdefs
[8], RAM_size
, boot_device
, kernel_filename
,
1213 kernel_cmdline
, initrd_filename
, cpu_model
);
1216 static QEMUMachine ss5_machine
= {
1218 .desc
= "Sun4m platform, SPARCstation 5",
1224 static QEMUMachine ss10_machine
= {
1226 .desc
= "Sun4m platform, SPARCstation 10",
1232 static QEMUMachine ss600mp_machine
= {
1234 .desc
= "Sun4m platform, SPARCserver 600MP",
1235 .init
= ss600mp_init
,
1240 static QEMUMachine ss20_machine
= {
1242 .desc
= "Sun4m platform, SPARCstation 20",
1248 static QEMUMachine voyager_machine
= {
1250 .desc
= "Sun4m platform, SPARCstation Voyager",
1255 static QEMUMachine ss_lx_machine
= {
1257 .desc
= "Sun4m platform, SPARCstation LX",
1262 static QEMUMachine ss4_machine
= {
1264 .desc
= "Sun4m platform, SPARCstation 4",
1269 static QEMUMachine scls_machine
= {
1270 .name
= "SPARCClassic",
1271 .desc
= "Sun4m platform, SPARCClassic",
1276 static QEMUMachine sbook_machine
= {
1277 .name
= "SPARCbook",
1278 .desc
= "Sun4m platform, SPARCbook",
1283 static const struct sun4d_hwdef sun4d_hwdefs
[] = {
1293 .tcx_base
= 0x820000000ULL
,
1294 .slavio_base
= 0xf00000000ULL
,
1295 .ms_kb_base
= 0xf00240000ULL
,
1296 .serial_base
= 0xf00200000ULL
,
1297 .nvram_base
= 0xf00280000ULL
,
1298 .counter_base
= 0xf00300000ULL
,
1299 .espdma_base
= 0x800081000ULL
,
1300 .esp_base
= 0x800080000ULL
,
1301 .ledma_base
= 0x800040000ULL
,
1302 .le_base
= 0x800060000ULL
,
1303 .sbi_base
= 0xf02800000ULL
,
1304 .nvram_machine_id
= 0x80,
1305 .machine_id
= ss1000_id
,
1306 .iounit_version
= 0x03000000,
1307 .max_mem
= 0xf00000000ULL
,
1308 .default_cpu_model
= "TI SuperSparc II",
1319 .tcx_base
= 0x820000000ULL
,
1320 .slavio_base
= 0xf00000000ULL
,
1321 .ms_kb_base
= 0xf00240000ULL
,
1322 .serial_base
= 0xf00200000ULL
,
1323 .nvram_base
= 0xf00280000ULL
,
1324 .counter_base
= 0xf00300000ULL
,
1325 .espdma_base
= 0x800081000ULL
,
1326 .esp_base
= 0x800080000ULL
,
1327 .ledma_base
= 0x800040000ULL
,
1328 .le_base
= 0x800060000ULL
,
1329 .sbi_base
= 0xf02800000ULL
,
1330 .nvram_machine_id
= 0x80,
1331 .machine_id
= ss2000_id
,
1332 .iounit_version
= 0x03000000,
1333 .max_mem
= 0xf00000000ULL
,
1334 .default_cpu_model
= "TI SuperSparc II",
1338 static DeviceState
*sbi_init(target_phys_addr_t addr
, qemu_irq
**parent_irq
)
1344 dev
= qdev_create(NULL
, "sbi");
1347 s
= sysbus_from_qdev(dev
);
1349 for (i
= 0; i
< MAX_CPUS
; i
++) {
1350 sysbus_connect_irq(s
, i
, *parent_irq
[i
]);
1353 sysbus_mmio_map(s
, 0, addr
);
1358 static void sun4d_hw_init(const struct sun4d_hwdef
*hwdef
, ram_addr_t RAM_size
,
1359 const char *boot_device
,
1360 const char *kernel_filename
,
1361 const char *kernel_cmdline
,
1362 const char *initrd_filename
, const char *cpu_model
)
1364 CPUState
*envs
[MAX_CPUS
];
1366 void *iounits
[MAX_IOUNITS
], *espdma
, *ledma
, *nvram
;
1367 qemu_irq
*cpu_irqs
[MAX_CPUS
], sbi_irq
[32], sbi_cpu_irq
[MAX_CPUS
],
1368 espdma_irq
, ledma_irq
;
1370 unsigned long kernel_size
;
1376 cpu_model
= hwdef
->default_cpu_model
;
1378 for(i
= 0; i
< smp_cpus
; i
++) {
1379 envs
[i
] = cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
1382 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
1383 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
1385 /* set up devices */
1386 ram_init(0, RAM_size
, hwdef
->max_mem
);
1388 prom_init(hwdef
->slavio_base
, bios_name
);
1390 dev
= sbi_init(hwdef
->sbi_base
, cpu_irqs
);
1392 for (i
= 0; i
< 32; i
++) {
1393 sbi_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1395 for (i
= 0; i
< MAX_CPUS
; i
++) {
1396 sbi_cpu_irq
[i
] = qdev_get_gpio_in(dev
, 32 + i
);
1399 for (i
= 0; i
< MAX_IOUNITS
; i
++)
1400 if (hwdef
->iounit_bases
[i
] != (target_phys_addr_t
)-1)
1401 iounits
[i
] = iommu_init(hwdef
->iounit_bases
[i
],
1402 hwdef
->iounit_version
,
1405 espdma
= sparc32_dma_init(hwdef
->espdma_base
, sbi_irq
[3],
1406 iounits
[0], &espdma_irq
);
1408 ledma
= sparc32_dma_init(hwdef
->ledma_base
, sbi_irq
[4],
1409 iounits
[0], &ledma_irq
);
1411 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1412 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1415 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1418 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1420 nvram
= m48t59_init(sbi_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
1422 slavio_timer_init_all(hwdef
->counter_base
, sbi_irq
[10], sbi_cpu_irq
, smp_cpus
);
1424 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, sbi_irq
[12],
1425 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1426 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1427 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1428 escc_init(hwdef
->serial_base
, sbi_irq
[12], sbi_irq
[12],
1429 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
1431 if (drive_get_max_bus(IF_SCSI
) > 0) {
1432 fprintf(stderr
, "qemu: too many SCSI bus\n");
1436 esp_reset
= qdev_get_gpio_in(espdma
, 0);
1437 esp_init(hwdef
->esp_base
, 2,
1438 espdma_memory_read
, espdma_memory_write
,
1439 espdma
, espdma_irq
, &esp_reset
);
1441 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1444 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1445 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1446 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1449 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1450 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1451 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1452 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1453 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1454 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1455 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1456 if (kernel_cmdline
) {
1457 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1458 pstrcpy_targphys(CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1460 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1462 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1463 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1464 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1465 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1468 /* SPARCserver 1000 hardware initialisation */
1469 static void ss1000_init(ram_addr_t RAM_size
,
1470 const char *boot_device
,
1471 const char *kernel_filename
, const char *kernel_cmdline
,
1472 const char *initrd_filename
, const char *cpu_model
)
1474 sun4d_hw_init(&sun4d_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1475 kernel_cmdline
, initrd_filename
, cpu_model
);
1478 /* SPARCcenter 2000 hardware initialisation */
1479 static void ss2000_init(ram_addr_t RAM_size
,
1480 const char *boot_device
,
1481 const char *kernel_filename
, const char *kernel_cmdline
,
1482 const char *initrd_filename
, const char *cpu_model
)
1484 sun4d_hw_init(&sun4d_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1485 kernel_cmdline
, initrd_filename
, cpu_model
);
1488 static QEMUMachine ss1000_machine
= {
1490 .desc
= "Sun4d platform, SPARCserver 1000",
1491 .init
= ss1000_init
,
1496 static QEMUMachine ss2000_machine
= {
1498 .desc
= "Sun4d platform, SPARCcenter 2000",
1499 .init
= ss2000_init
,
1504 static const struct sun4c_hwdef sun4c_hwdefs
[] = {
1507 .iommu_base
= 0xf8000000,
1508 .tcx_base
= 0xfe000000,
1509 .slavio_base
= 0xf6000000,
1510 .intctl_base
= 0xf5000000,
1511 .counter_base
= 0xf3000000,
1512 .ms_kb_base
= 0xf0000000,
1513 .serial_base
= 0xf1000000,
1514 .nvram_base
= 0xf2000000,
1515 .fd_base
= 0xf7200000,
1516 .dma_base
= 0xf8400000,
1517 .esp_base
= 0xf8800000,
1518 .le_base
= 0xf8c00000,
1519 .aux1_base
= 0xf7400003,
1520 .nvram_machine_id
= 0x55,
1521 .machine_id
= ss2_id
,
1522 .max_mem
= 0x10000000,
1523 .default_cpu_model
= "Cypress CY7C601",
1527 static DeviceState
*sun4c_intctl_init(target_phys_addr_t addr
,
1528 qemu_irq
*parent_irq
)
1534 dev
= qdev_create(NULL
, "sun4c_intctl");
1537 s
= sysbus_from_qdev(dev
);
1539 for (i
= 0; i
< MAX_PILS
; i
++) {
1540 sysbus_connect_irq(s
, i
, parent_irq
[i
]);
1542 sysbus_mmio_map(s
, 0, addr
);
1547 static void sun4c_hw_init(const struct sun4c_hwdef
*hwdef
, ram_addr_t RAM_size
,
1548 const char *boot_device
,
1549 const char *kernel_filename
,
1550 const char *kernel_cmdline
,
1551 const char *initrd_filename
, const char *cpu_model
)
1554 void *iommu
, *espdma
, *ledma
, *nvram
;
1555 qemu_irq
*cpu_irqs
, slavio_irq
[8], espdma_irq
, ledma_irq
;
1558 unsigned long kernel_size
;
1559 BlockDriverState
*fd
[MAX_FD
];
1567 cpu_model
= hwdef
->default_cpu_model
;
1569 env
= cpu_devinit(cpu_model
, 0, hwdef
->slavio_base
, &cpu_irqs
);
1571 /* set up devices */
1572 ram_init(0, RAM_size
, hwdef
->max_mem
);
1574 prom_init(hwdef
->slavio_base
, bios_name
);
1576 dev
= sun4c_intctl_init(hwdef
->intctl_base
, cpu_irqs
);
1578 for (i
= 0; i
< 8; i
++) {
1579 slavio_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1582 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
1585 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[2],
1586 iommu
, &espdma_irq
);
1588 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
1589 slavio_irq
[3], iommu
, &ledma_irq
);
1591 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1592 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1595 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1598 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1600 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x800, 2);
1602 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[1],
1603 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1604 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1605 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1606 escc_init(hwdef
->serial_base
, slavio_irq
[1],
1607 slavio_irq
[1], serial_hds
[0], serial_hds
[1],
1610 slavio_misc_init(0, hwdef
->aux1_base
, 0, slavio_irq
[1], fdc_tc
);
1612 if (hwdef
->fd_base
!= (target_phys_addr_t
)-1) {
1613 /* there is zero or one floppy drive */
1614 memset(fd
, 0, sizeof(fd
));
1615 dinfo
= drive_get(IF_FLOPPY
, 0, 0);
1617 fd
[0] = dinfo
->bdrv
;
1619 sun4m_fdctrl_init(slavio_irq
[1], hwdef
->fd_base
, fd
,
1623 if (drive_get_max_bus(IF_SCSI
) > 0) {
1624 fprintf(stderr
, "qemu: too many SCSI bus\n");
1628 esp_reset
= qdev_get_gpio_in(espdma
, 0);
1629 esp_init(hwdef
->esp_base
, 2,
1630 espdma_memory_read
, espdma_memory_write
,
1631 espdma
, espdma_irq
, &esp_reset
);
1633 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1636 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1637 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1638 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1641 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1642 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1643 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1644 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1645 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1646 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1647 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1648 if (kernel_cmdline
) {
1649 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1650 pstrcpy_targphys(CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1652 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1654 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1655 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1656 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1657 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1660 /* SPARCstation 2 hardware initialisation */
1661 static void ss2_init(ram_addr_t RAM_size
,
1662 const char *boot_device
,
1663 const char *kernel_filename
, const char *kernel_cmdline
,
1664 const char *initrd_filename
, const char *cpu_model
)
1666 sun4c_hw_init(&sun4c_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1667 kernel_cmdline
, initrd_filename
, cpu_model
);
1670 static QEMUMachine ss2_machine
= {
1672 .desc
= "Sun4c platform, SPARCstation 2",
1677 static void ss2_machine_init(void)
1679 qemu_register_machine(&ss5_machine
);
1680 qemu_register_machine(&ss10_machine
);
1681 qemu_register_machine(&ss600mp_machine
);
1682 qemu_register_machine(&ss20_machine
);
1683 qemu_register_machine(&voyager_machine
);
1684 qemu_register_machine(&ss_lx_machine
);
1685 qemu_register_machine(&ss4_machine
);
1686 qemu_register_machine(&scls_machine
);
1687 qemu_register_machine(&sbook_machine
);
1688 qemu_register_machine(&ss1000_machine
);
1689 qemu_register_machine(&ss2000_machine
);
1690 qemu_register_machine(&ss2_machine
);
1693 machine_init(ss2_machine_init
);