hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "qemu-timer.h"
  22 #include "host-utils.h"
  23 #include "sysbus.h"
  24 #include "kvm.h"
  25
  26 //#define DEBUG_APIC
  27 //#define DEBUG_COALESCING
  28
  29 #ifdef DEBUG_APIC
  30 #define DPRINTF(fmt, ...)                                       \
  31     do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
  32 #else
  33 #define DPRINTF(fmt, ...)
  34 #endif
  35
  36 #ifdef DEBUG_COALESCING
  37 #define DPRINTF_C(fmt, ...)                                     \
  38     do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF_C(fmt, ...)
  41 #endif
  42
  43 /* APIC Local Vector Table */
  44 #define APIC_LVT_TIMER   0
  45 #define APIC_LVT_THERMAL 1
  46 #define APIC_LVT_PERFORM 2
  47 #define APIC_LVT_LINT0   3
  48 #define APIC_LVT_LINT1   4
  49 #define APIC_LVT_ERROR   5
  50 #define APIC_LVT_NB      6
  51
  52 /* APIC delivery modes */
  53 #define APIC_DM_FIXED   0
  54 #define APIC_DM_LOWPRI  1
  55 #define APIC_DM_SMI     2
  56 #define APIC_DM_NMI     4
  57 #define APIC_DM_INIT    5
  58 #define APIC_DM_SIPI    6
  59 #define APIC_DM_EXTINT  7
  60
  61 /* APIC destination mode */
  62 #define APIC_DESTMODE_FLAT      0xf
  63 #define APIC_DESTMODE_CLUSTER   1
  64
  65 #define APIC_TRIGGER_EDGE  0
  66 #define APIC_TRIGGER_LEVEL 1
  67
  68 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  69 #define APIC_LVT_MASKED                 (1<<16)
  70 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  71 #define APIC_LVT_REMOTE_IRR             (1<<14)
  72 #define APIC_INPUT_POLARITY             (1<<13)
  73 #define APIC_SEND_PENDING               (1<<12)
  74
  75 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  76
  77 #define APIC_SV_ENABLE (1 << 8)
  78
  79 #define MAX_APICS 255
  80 #define MAX_APIC_WORDS 8
  81
  82 /* Intel APIC constants: from include/asm/msidef.h */
  83 #define MSI_DATA_VECTOR_SHIFT           0
  84 #define MSI_DATA_VECTOR_MASK            0x000000ff
  85 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  86 #define MSI_DATA_TRIGGER_SHIFT          15
  87 #define MSI_DATA_LEVEL_SHIFT            14
  88 #define MSI_ADDR_DEST_MODE_SHIFT        2
  89 #define MSI_ADDR_DEST_ID_SHIFT          12
  90 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  91
  92 #define MSI_ADDR_SIZE                   0x100000
  93
  94 typedef struct APICState APICState;
  95
  96 struct APICState {
  97     SysBusDevice busdev;
  98     void *cpu_env;
  99     uint32_t apicbase;
 100     uint8_t id;
 101     uint8_t arb_id;
 102     uint8_t tpr;
 103     uint32_t spurious_vec;
 104     uint8_t log_dest;
 105     uint8_t dest_mode;
 106     uint32_t isr[8];  /* in service register */
 107     uint32_t tmr[8];  /* trigger mode register */
 108     uint32_t irr[8]; /* interrupt request register */
 109     uint32_t lvt[APIC_LVT_NB];
 110     uint32_t esr; /* error register */
 111     uint32_t icr[2];
 112
 113     uint32_t divide_conf;
 114     int count_shift;
 115     uint32_t initial_count;
 116     int64_t initial_count_load_time, next_time;
 117     uint32_t idx;
 118     QEMUTimer *timer;
 119     int sipi_vector;
 120     int wait_for_sipi;
 121 };
 122
 123 static APICState *local_apics[MAX_APICS + 1];
 124 static int apic_irq_delivered;
 125
 126 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 127 static void apic_update_irq(APICState *s);
 128 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 129                                       uint8_t dest, uint8_t dest_mode);
 130
 131 /* Find first bit starting from msb */
 132 static int fls_bit(uint32_t value)
 133 {
 134     return 31 - clz32(value);
 135 }
 136
 137 /* Find first bit starting from lsb */
 138 static int ffs_bit(uint32_t value)
 139 {
 140     return ctz32(value);
 141 }
 142
 143 static inline void set_bit(uint32_t *tab, int index)
 144 {
 145     int i, mask;
 146     i = index >> 5;
 147     mask = 1 << (index & 0x1f);
 148     tab[i] |= mask;
 149 }
 150
 151 static inline void reset_bit(uint32_t *tab, int index)
 152 {
 153     int i, mask;
 154     i = index >> 5;
 155     mask = 1 << (index & 0x1f);
 156     tab[i] &= ~mask;
 157 }
 158
 159 static inline int get_bit(uint32_t *tab, int index)
 160 {
 161     int i, mask;
 162     i = index >> 5;
 163     mask = 1 << (index & 0x1f);
 164     return !!(tab[i] & mask);
 165 }
 166
 167 static void apic_local_deliver(APICState *s, int vector)
 168 {
 169     uint32_t lvt = s->lvt[vector];
 170     int trigger_mode;
 171
 172     DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector,
 173             (lvt >> 8) & 7);
 174     if (lvt & APIC_LVT_MASKED)
 175         return;
 176
 177     switch ((lvt >> 8) & 7) {
 178     case APIC_DM_SMI:
 179         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 180         break;
 181
 182     case APIC_DM_NMI:
 183         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 184         break;
 185
 186     case APIC_DM_EXTINT:
 187         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 188         break;
 189
 190     case APIC_DM_FIXED:
 191         trigger_mode = APIC_TRIGGER_EDGE;
 192         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 193             (lvt & APIC_LVT_LEVEL_TRIGGER))
 194             trigger_mode = APIC_TRIGGER_LEVEL;
 195         apic_set_irq(s, lvt & 0xff, trigger_mode);
 196     }
 197 }
 198
 199 void apic_deliver_pic_intr(DeviceState *d, int level)
 200 {
 201     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 202
 203     if (level) {
 204         apic_local_deliver(s, APIC_LVT_LINT0);
 205     } else {
 206         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 207
 208         switch ((lvt >> 8) & 7) {
 209         case APIC_DM_FIXED:
 210             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 211                 break;
 212             reset_bit(s->irr, lvt & 0xff);
 213             /* fall through */
 214         case APIC_DM_EXTINT:
 215             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 216             break;
 217         }
 218     }
 219 }
 220
 221 #define foreach_apic(apic, deliver_bitmask, code) \
 222 {\
 223     int __i, __j, __mask;\
 224     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 225         __mask = deliver_bitmask[__i];\
 226         if (__mask) {\
 227             for(__j = 0; __j < 32; __j++) {\
 228                 if (__mask & (1 << __j)) {\
 229                     apic = local_apics[__i * 32 + __j];\
 230                     if (apic) {\
 231                         code;\
 232                     }\
 233                 }\
 234             }\
 235         }\
 236     }\
 237 }
 238
 239 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 240                              uint8_t delivery_mode,
 241                              uint8_t vector_num, uint8_t polarity,
 242                              uint8_t trigger_mode)
 243 {
 244     APICState *apic_iter;
 245
 246     switch (delivery_mode) {
 247         case APIC_DM_LOWPRI:
 248             /* XXX: search for focus processor, arbitration */
 249             {
 250                 int i, d;
 251                 d = -1;
 252                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 253                     if (deliver_bitmask[i]) {
 254                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 255                         break;
 256                     }
 257                 }
 258                 if (d >= 0) {
 259                     apic_iter = local_apics[d];
 260                     if (apic_iter) {
 261                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 262                     }
 263                 }
 264             }
 265             return;
 266
 267         case APIC_DM_FIXED:
 268             break;
 269
 270         case APIC_DM_SMI:
 271             foreach_apic(apic_iter, deliver_bitmask,
 272                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 273             return;
 274
 275         case APIC_DM_NMI:
 276             foreach_apic(apic_iter, deliver_bitmask,
 277                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 278             return;
 279
 280         case APIC_DM_INIT:
 281             /* normal INIT IPI sent to processors */
 282             foreach_apic(apic_iter, deliver_bitmask,
 283                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 284             return;
 285
 286         case APIC_DM_EXTINT:
 287             /* handled in I/O APIC code */
 288             break;
 289
 290         default:
 291             return;
 292     }
 293
 294     foreach_apic(apic_iter, deliver_bitmask,
 295                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 296 }
 297
 298 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 299                       uint8_t delivery_mode, uint8_t vector_num,
 300                       uint8_t polarity, uint8_t trigger_mode)
 301 {
 302     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 303
 304     DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d"
 305             " polarity %d trigger_mode %d\n", __func__, dest, dest_mode,
 306             delivery_mode, vector_num, polarity, trigger_mode);
 307     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 308     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 309                      trigger_mode);
 310 }
 311
 312 void cpu_set_apic_base(DeviceState *d, uint64_t val)
 313 {
 314     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 315
 316     DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val);
 317     if (!s)
 318         return;
 319     if (kvm_enabled() && kvm_irqchip_in_kernel())
 320         s->apicbase = val;
 321     else
 322         s->apicbase = (val & 0xfffff000) |
 323             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 324     /* if disabled, cannot be enabled again */
 325     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 326         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 327         cpu_clear_apic_feature(s->cpu_env);
 328         s->spurious_vec &= ~APIC_SV_ENABLE;
 329     }
 330 }
 331
 332 uint64_t cpu_get_apic_base(DeviceState *d)
 333 {
 334     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 335
 336     DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n",
 337             s ? (uint64_t)s->apicbase: 0);
 338     return s ? s->apicbase : 0;
 339 }
 340
 341 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
 342 {
 343     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 344
 345     if (!s)
 346         return;
 347     s->tpr = (val & 0x0f) << 4;
 348     apic_update_irq(s);
 349 }
 350
 351 uint8_t cpu_get_apic_tpr(DeviceState *d)
 352 {
 353     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 354
 355     return s ? s->tpr >> 4 : 0;
 356 }
 357
 358 /* return -1 if no bit is set */
 359 static int get_highest_priority_int(uint32_t *tab)
 360 {
 361     int i;
 362     for(i = 7; i >= 0; i--) {
 363         if (tab[i] != 0) {
 364             return i * 32 + fls_bit(tab[i]);
 365         }
 366     }
 367     return -1;
 368 }
 369
 370 static int apic_get_ppr(APICState *s)
 371 {
 372     int tpr, isrv, ppr;
 373
 374     tpr = (s->tpr >> 4);
 375     isrv = get_highest_priority_int(s->isr);
 376     if (isrv < 0)
 377         isrv = 0;
 378     isrv >>= 4;
 379     if (tpr >= isrv)
 380         ppr = s->tpr;
 381     else
 382         ppr = isrv << 4;
 383     return ppr;
 384 }
 385
 386 static int apic_get_arb_pri(APICState *s)
 387 {
 388     /* XXX: arbitration */
 389     return 0;
 390 }
 391
 392 /* signal the CPU if an irq is pending */
 393 static void apic_update_irq(APICState *s)
 394 {
 395     int irrv, ppr;
 396     if (!(s->spurious_vec & APIC_SV_ENABLE))
 397         return;
 398     irrv = get_highest_priority_int(s->irr);
 399     if (irrv < 0)
 400         return;
 401     ppr = apic_get_ppr(s);
 402     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 403         return;
 404     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 405 }
 406
 407 void apic_reset_irq_delivered(void)
 408 {
 409     DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered);
 410     apic_irq_delivered = 0;
 411 }
 412
 413 int apic_get_irq_delivered(void)
 414 {
 415     DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered);
 416     return apic_irq_delivered;
 417 }
 418
 419 void apic_set_irq_delivered(void)
 420 {
 421     apic_irq_delivered = 1;
 422 }
 423
 424 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 425 {
 426     apic_irq_delivered += !get_bit(s->irr, vector_num);
 427     DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered);
 428
 429     set_bit(s->irr, vector_num);
 430     if (trigger_mode)
 431         set_bit(s->tmr, vector_num);
 432     else
 433         reset_bit(s->tmr, vector_num);
 434     apic_update_irq(s);
 435 }
 436
 437 static void apic_eoi(APICState *s)
 438 {
 439     int isrv;
 440     isrv = get_highest_priority_int(s->isr);
 441     if (isrv < 0)
 442         return;
 443     reset_bit(s->isr, isrv);
 444     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 445             set the remote IRR bit for level triggered interrupts. */
 446     apic_update_irq(s);
 447 }
 448
 449 static int apic_find_dest(uint8_t dest)
 450 {
 451     APICState *apic = local_apics[dest];
 452     int i;
 453
 454     if (apic && apic->id == dest)
 455         return dest;  /* shortcut in case apic->id == apic->idx */
 456
 457     for (i = 0; i < MAX_APICS; i++) {
 458         apic = local_apics[i];
 459         if (apic && apic->id == dest)
 460             return i;
 461     }
 462
 463     return -1;
 464 }
 465
 466 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 467                                       uint8_t dest, uint8_t dest_mode)
 468 {
 469     APICState *apic_iter;
 470     int i;
 471
 472     if (dest_mode == 0) {
 473         if (dest == 0xff) {
 474             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 475         } else {
 476             int idx = apic_find_dest(dest);
 477             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 478             if (idx >= 0)
 479                 set_bit(deliver_bitmask, idx);
 480         }
 481     } else {
 482         /* XXX: cluster mode */
 483         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 484         for(i = 0; i < MAX_APICS; i++) {
 485             apic_iter = local_apics[i];
 486             if (apic_iter) {
 487                 if (apic_iter->dest_mode == 0xf) {
 488                     if (dest & apic_iter->log_dest)
 489                         set_bit(deliver_bitmask, i);
 490                 } else if (apic_iter->dest_mode == 0x0) {
 491                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 492                         (dest & apic_iter->log_dest & 0x0f)) {
 493                         set_bit(deliver_bitmask, i);
 494                     }
 495                 }
 496             }
 497         }
 498     }
 499 }
 500
 501 void apic_init_reset(DeviceState *d)
 502 {
 503     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 504     int i;
 505
 506     if (!s)
 507         return;
 508
 509     s->tpr = 0;
 510     s->spurious_vec = 0xff;
 511     s->log_dest = 0;
 512     s->dest_mode = 0xf;
 513     memset(s->isr, 0, sizeof(s->isr));
 514     memset(s->tmr, 0, sizeof(s->tmr));
 515     memset(s->irr, 0, sizeof(s->irr));
 516     for(i = 0; i < APIC_LVT_NB; i++)
 517         s->lvt[i] = 1 << 16; /* mask LVT */
 518     s->esr = 0;
 519     memset(s->icr, 0, sizeof(s->icr));
 520     s->divide_conf = 0;
 521     s->count_shift = 0;
 522     s->initial_count = 0;
 523     s->initial_count_load_time = 0;
 524     s->next_time = 0;
 525     s->wait_for_sipi = 1;
 526 }
 527
 528 static void apic_startup(APICState *s, int vector_num)
 529 {
 530     s->sipi_vector = vector_num;
 531     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 532 }
 533
 534 void apic_sipi(DeviceState *d)
 535 {
 536     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 537
 538     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 539
 540     if (!s->wait_for_sipi)
 541         return;
 542     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 543     s->wait_for_sipi = 0;
 544 }
 545
 546 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 547                          uint8_t delivery_mode, uint8_t vector_num,
 548                          uint8_t polarity, uint8_t trigger_mode)
 549 {
 550     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 551     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 552     int dest_shorthand = (s->icr[0] >> 18) & 3;
 553     APICState *apic_iter;
 554
 555     switch (dest_shorthand) {
 556     case 0:
 557         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 558         break;
 559     case 1:
 560         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 561         set_bit(deliver_bitmask, s->idx);
 562         break;
 563     case 2:
 564         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 565         break;
 566     case 3:
 567         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 568         reset_bit(deliver_bitmask, s->idx);
 569         break;
 570     }
 571
 572     switch (delivery_mode) {
 573         case APIC_DM_INIT:
 574             {
 575                 int trig_mode = (s->icr[0] >> 15) & 1;
 576                 int level = (s->icr[0] >> 14) & 1;
 577                 if (level == 0 && trig_mode == 1) {
 578                     foreach_apic(apic_iter, deliver_bitmask,
 579                                  apic_iter->arb_id = apic_iter->id );
 580                     return;
 581                 }
 582             }
 583             break;
 584
 585         case APIC_DM_SIPI:
 586             foreach_apic(apic_iter, deliver_bitmask,
 587                          apic_startup(apic_iter, vector_num) );
 588             return;
 589     }
 590
 591     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 592                      trigger_mode);
 593 }
 594
 595 int apic_get_interrupt(DeviceState *d)
 596 {
 597     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 598     int intno;
 599
 600     /* if the APIC is installed or enabled, we let the 8259 handle the
 601        IRQs */
 602     if (!s)
 603         return -1;
 604     if (!(s->spurious_vec & APIC_SV_ENABLE))
 605         return -1;
 606
 607     /* XXX: spurious IRQ handling */
 608     intno = get_highest_priority_int(s->irr);
 609     if (intno < 0)
 610         return -1;
 611     if (s->tpr && intno <= s->tpr)
 612         return s->spurious_vec & 0xff;
 613     reset_bit(s->irr, intno);
 614     set_bit(s->isr, intno);
 615     apic_update_irq(s);
 616     return intno;
 617 }
 618
 619 int apic_accept_pic_intr(DeviceState *d)
 620 {
 621     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 622     uint32_t lvt0;
 623
 624     if (!s)
 625         return -1;
 626
 627     lvt0 = s->lvt[APIC_LVT_LINT0];
 628
 629     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 630         (lvt0 & APIC_LVT_MASKED) == 0)
 631         return 1;
 632
 633     return 0;
 634 }
 635
 636 static uint32_t apic_get_current_count(APICState *s)
 637 {
 638     int64_t d;
 639     uint32_t val;
 640     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 641         s->count_shift;
 642     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 643         /* periodic */
 644         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 645     } else {
 646         if (d >= s->initial_count)
 647             val = 0;
 648         else
 649             val = s->initial_count - d;
 650     }
 651     return val;
 652 }
 653
 654 static void apic_timer_update(APICState *s, int64_t current_time)
 655 {
 656     int64_t next_time, d;
 657
 658     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 659         d = (current_time - s->initial_count_load_time) >>
 660             s->count_shift;
 661         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 662             if (!s->initial_count)
 663                 goto no_timer;
 664             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 665         } else {
 666             if (d >= s->initial_count)
 667                 goto no_timer;
 668             d = (uint64_t)s->initial_count + 1;
 669         }
 670         next_time = s->initial_count_load_time + (d << s->count_shift);
 671         qemu_mod_timer(s->timer, next_time);
 672         s->next_time = next_time;
 673     } else {
 674     no_timer:
 675         qemu_del_timer(s->timer);
 676     }
 677 }
 678
 679 static void apic_timer(void *opaque)
 680 {
 681     APICState *s = opaque;
 682
 683     apic_local_deliver(s, APIC_LVT_TIMER);
 684     apic_timer_update(s, s->next_time);
 685 }
 686
 687 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 688 {
 689     return 0;
 690 }
 691
 692 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 693 {
 694     return 0;
 695 }
 696
 697 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 698 {
 699 }
 700
 701 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 702 {
 703 }
 704
 705 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 706 {
 707     DeviceState *d;
 708     APICState *s;
 709     uint32_t val;
 710     int index;
 711
 712     d = cpu_get_current_apic();
 713     if (!d) {
 714         return 0;
 715     }
 716     s = DO_UPCAST(APICState, busdev.qdev, d);
 717
 718     index = (addr >> 4) & 0xff;
 719     switch(index) {
 720     case 0x02: /* id */
 721         val = s->id << 24;
 722         break;
 723     case 0x03: /* version */
 724         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 725         break;
 726     case 0x08:
 727         val = s->tpr;
 728         break;
 729     case 0x09:
 730         val = apic_get_arb_pri(s);
 731         break;
 732     case 0x0a:
 733         /* ppr */
 734         val = apic_get_ppr(s);
 735         break;
 736     case 0x0b:
 737         val = 0;
 738         break;
 739     case 0x0d:
 740         val = s->log_dest << 24;
 741         break;
 742     case 0x0e:
 743         val = s->dest_mode << 28;
 744         break;
 745     case 0x0f:
 746         val = s->spurious_vec;
 747         break;
 748     case 0x10 ... 0x17:
 749         val = s->isr[index & 7];
 750         break;
 751     case 0x18 ... 0x1f:
 752         val = s->tmr[index & 7];
 753         break;
 754     case 0x20 ... 0x27:
 755         val = s->irr[index & 7];
 756         break;
 757     case 0x28:
 758         val = s->esr;
 759         break;
 760     case 0x30:
 761     case 0x31:
 762         val = s->icr[index & 1];
 763         break;
 764     case 0x32 ... 0x37:
 765         val = s->lvt[index - 0x32];
 766         break;
 767     case 0x38:
 768         val = s->initial_count;
 769         break;
 770     case 0x39:
 771         val = apic_get_current_count(s);
 772         break;
 773     case 0x3e:
 774         val = s->divide_conf;
 775         break;
 776     default:
 777         s->esr |= ESR_ILLEGAL_ADDRESS;
 778         val = 0;
 779         break;
 780     }
 781     DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val);
 782     return val;
 783 }
 784
 785 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 786 {
 787     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 788     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 789     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 790     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 791     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 792     /* XXX: Ignore redirection hint. */
 793     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 794 }
 795
 796 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 797 {
 798     DeviceState *d;
 799     APICState *s;
 800     int index = (addr >> 4) & 0xff;
 801     if (addr > 0xfff || !index) {
 802         /* MSI and MMIO APIC are at the same memory location,
 803          * but actually not on the global bus: MSI is on PCI bus
 804          * APIC is connected directly to the CPU.
 805          * Mapping them on the global bus happens to work because
 806          * MSI registers are reserved in APIC MMIO and vice versa. */
 807         apic_send_msi(addr, val);
 808         return;
 809     }
 810
 811     d = cpu_get_current_apic();
 812     if (!d) {
 813         return;
 814     }
 815     s = DO_UPCAST(APICState, busdev.qdev, d);
 816
 817     DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val);
 818
 819     switch(index) {
 820     case 0x02:
 821         s->id = (val >> 24);
 822         break;
 823     case 0x03:
 824         break;
 825     case 0x08:
 826         s->tpr = val;
 827         apic_update_irq(s);
 828         break;
 829     case 0x09:
 830     case 0x0a:
 831         break;
 832     case 0x0b: /* EOI */
 833         apic_eoi(s);
 834         break;
 835     case 0x0d:
 836         s->log_dest = val >> 24;
 837         break;
 838     case 0x0e:
 839         s->dest_mode = val >> 28;
 840         break;
 841     case 0x0f:
 842         s->spurious_vec = val & 0x1ff;
 843         apic_update_irq(s);
 844         break;
 845     case 0x10 ... 0x17:
 846     case 0x18 ... 0x1f:
 847     case 0x20 ... 0x27:
 848     case 0x28:
 849         break;
 850     case 0x30:
 851         s->icr[0] = val;
 852         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 853                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 854                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 855         break;
 856     case 0x31:
 857         s->icr[1] = val;
 858         break;
 859     case 0x32 ... 0x37:
 860         {
 861             int n = index - 0x32;
 862             s->lvt[n] = val;
 863             if (n == APIC_LVT_TIMER)
 864                 apic_timer_update(s, qemu_get_clock(vm_clock));
 865         }
 866         break;
 867     case 0x38:
 868         s->initial_count = val;
 869         s->initial_count_load_time = qemu_get_clock(vm_clock);
 870         apic_timer_update(s, s->initial_count_load_time);
 871         break;
 872     case 0x39:
 873         break;
 874     case 0x3e:
 875         {
 876             int v;
 877             s->divide_conf = val & 0xb;
 878             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 879             s->count_shift = (v + 1) & 7;
 880         }
 881         break;
 882     default:
 883         s->esr |= ESR_ILLEGAL_ADDRESS;
 884         break;
 885     }
 886 }
 887
 888 #ifdef KVM_CAP_IRQCHIP
 889
 890 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 891 {
 892     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 893 }
 894
 895 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 896                                  int reg_id, uint32_t val)
 897 {
 898     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 899 }
 900
 901 static void kvm_kernel_lapic_save_to_user(APICState *s)
 902 {
 903     struct kvm_lapic_state apic;
 904     struct kvm_lapic_state *kapic = &apic;
 905     int i, v;
 906
 907     kvm_get_lapic(s->cpu_env, kapic);
 908
 909     s->id = kapic_reg(kapic, 0x2) >> 24;
 910     s->tpr = kapic_reg(kapic, 0x8);
 911     s->arb_id = kapic_reg(kapic, 0x9);
 912     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 913     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 914     s->spurious_vec = kapic_reg(kapic, 0xf);
 915     for (i = 0; i < 8; i++) {
 916         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 917         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 918         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 919     }
 920     s->esr = kapic_reg(kapic, 0x28);
 921     s->icr[0] = kapic_reg(kapic, 0x30);
 922     s->icr[1] = kapic_reg(kapic, 0x31);
 923     for (i = 0; i < APIC_LVT_NB; i++)
 924         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 925     s->initial_count = kapic_reg(kapic, 0x38);
 926     s->divide_conf = kapic_reg(kapic, 0x3e);
 927
 928     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 929     s->count_shift = (v + 1) & 7;
 930
 931     s->initial_count_load_time = qemu_get_clock(vm_clock);
 932     apic_timer_update(s, s->initial_count_load_time);
 933 }
 934
 935 static void kvm_kernel_lapic_load_from_user(APICState *s)
 936 {
 937     struct kvm_lapic_state apic;
 938     struct kvm_lapic_state *klapic = &apic;
 939     int i;
 940
 941     memset(klapic, 0, sizeof apic);
 942     kapic_set_reg(klapic, 0x2, s->id << 24);
 943     kapic_set_reg(klapic, 0x8, s->tpr);
 944     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 945     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 946     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 947     for (i = 0; i < 8; i++) {
 948         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 949         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 950         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 951     }
 952     kapic_set_reg(klapic, 0x28, s->esr);
 953     kapic_set_reg(klapic, 0x30, s->icr[0]);
 954     kapic_set_reg(klapic, 0x31, s->icr[1]);
 955     for (i = 0; i < APIC_LVT_NB; i++)
 956         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 957     kapic_set_reg(klapic, 0x38, s->initial_count);
 958     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 959
 960     kvm_set_lapic(s->cpu_env, klapic);
 961 }
 962
 963 #endif
 964
 965 void kvm_load_lapic(CPUState *env)
 966 {
 967     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 968
 969 #ifdef KVM_CAP_IRQCHIP
 970     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 971         kvm_kernel_lapic_load_from_user(s);
 972     }
 973 #endif
 974 }
 975
 976 void kvm_save_lapic(CPUState *env)
 977 {
 978     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 979
 980 #ifdef KVM_CAP_IRQCHIP
 981     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 982         kvm_kernel_lapic_save_to_user(s);
 983     }
 984 #endif
 985 }
 986
 987 /* This function is only used for old state version 1 and 2 */
 988 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 989 {
 990     APICState *s = opaque;
 991     int i;
 992
 993     if (version_id > 2)
 994         return -EINVAL;
 995
 996     /* XXX: what if the base changes? (registered memory regions) */
 997     qemu_get_be32s(f, &s->apicbase);
 998     qemu_get_8s(f, &s->id);
 999     qemu_get_8s(f, &s->arb_id);
1000     qemu_get_8s(f, &s->tpr);
1001     qemu_get_be32s(f, &s->spurious_vec);
1002     qemu_get_8s(f, &s->log_dest);
1003     qemu_get_8s(f, &s->dest_mode);
1004     for (i = 0; i < 8; i++) {
1005         qemu_get_be32s(f, &s->isr[i]);
1006         qemu_get_be32s(f, &s->tmr[i]);
1007         qemu_get_be32s(f, &s->irr[i]);
1008     }
1009     for (i = 0; i < APIC_LVT_NB; i++) {
1010         qemu_get_be32s(f, &s->lvt[i]);
1011     }
1012     qemu_get_be32s(f, &s->esr);
1013     qemu_get_be32s(f, &s->icr[0]);
1014     qemu_get_be32s(f, &s->icr[1]);
1015     qemu_get_be32s(f, &s->divide_conf);
1016     s->count_shift=qemu_get_be32(f);
1017     qemu_get_be32s(f, &s->initial_count);
1018     s->initial_count_load_time=qemu_get_be64(f);
1019     s->next_time=qemu_get_be64(f);
1020
1021     if (version_id >= 2)
1022         qemu_get_timer(f, s->timer);
1023     return 0;
1024 }
1025
1026 static const VMStateDescription vmstate_apic = {
1027     .name = "apic",
1028     .version_id = 3,
1029     .minimum_version_id = 3,
1030     .minimum_version_id_old = 1,
1031     .load_state_old = apic_load_old,
1032     .fields      = (VMStateField []) {
1033         VMSTATE_UINT32(apicbase, APICState),
1034         VMSTATE_UINT8(id, APICState),
1035         VMSTATE_UINT8(arb_id, APICState),
1036         VMSTATE_UINT8(tpr, APICState),
1037         VMSTATE_UINT32(spurious_vec, APICState),
1038         VMSTATE_UINT8(log_dest, APICState),
1039         VMSTATE_UINT8(dest_mode, APICState),
1040         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1041         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1042         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1043         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1044         VMSTATE_UINT32(esr, APICState),
1045         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1046         VMSTATE_UINT32(divide_conf, APICState),
1047         VMSTATE_INT32(count_shift, APICState),
1048         VMSTATE_UINT32(initial_count, APICState),
1049         VMSTATE_INT64(initial_count_load_time, APICState),
1050         VMSTATE_INT64(next_time, APICState),
1051         VMSTATE_TIMER(timer, APICState),
1052         VMSTATE_END_OF_LIST()
1053     }
1054 };
1055
1056 static void apic_reset(DeviceState *d)
1057 {
1058     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
1059     int bsp;
1060
1061     bsp = cpu_is_bsp(s->cpu_env);
1062     s->apicbase = 0xfee00000 |
1063         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1064
1065     apic_init_reset(d);
1066
1067     if (bsp) {
1068         /*
1069          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1070          * time typically by BIOS, so PIC interrupt can be delivered to the
1071          * processor when local APIC is enabled.
1072          */
1073         s->lvt[APIC_LVT_LINT0] = 0x700;
1074     }
1075 }
1076
1077 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1078     apic_mem_readb,
1079     apic_mem_readw,
1080     apic_mem_readl,
1081 };
1082
1083 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1084     apic_mem_writeb,
1085     apic_mem_writew,
1086     apic_mem_writel,
1087 };
1088
1089 static int apic_init1(SysBusDevice *dev)
1090 {
1091     APICState *s = FROM_SYSBUS(APICState, dev);
1092     int apic_io_memory;
1093     static int last_apic_idx;
1094
1095     if (last_apic_idx >= MAX_APICS) {
1096         return -1;
1097     }
1098     apic_io_memory = cpu_register_io_memory(apic_mem_read,
1099                                             apic_mem_write, NULL);
1100     sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
1101
1102     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1103     s->idx = last_apic_idx++;
1104     local_apics[s->idx] = s;
1105     return 0;
1106 }
1107
1108 static SysBusDeviceInfo apic_info = {
1109     .init = apic_init1,
1110     .qdev.name = "apic",
1111     .qdev.size = sizeof(APICState),
1112     .qdev.vmsd = &vmstate_apic,
1113     .qdev.reset = apic_reset,
1114     .qdev.no_user = 1,
1115     .qdev.props = (Property[]) {
1116         DEFINE_PROP_UINT8("id", APICState, id, -1),
1117         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1118         DEFINE_PROP_END_OF_LIST(),
1119     }
1120 };
1121
1122 static void apic_register_devices(void)
1123 {
1124     sysbus_register_withprop(&apic_info);
1125 }
1126
1127 device_init(apic_register_devices)