4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "device-assignment.h"
35 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
37 # define PCI_DPRINTF(format, ...) do { } while (0)
43 pci_set_irq_fn set_irq
;
44 pci_map_irq_fn map_irq
;
45 pci_hotplug_fn hotplug
;
46 uint32_t config_reg
; /* XXX: suppress */
48 PCIDevice
*devices
[256];
49 PCIDevice
*parent_dev
;
51 QLIST_HEAD(, PCIBus
) child
; /* this will be replaced by qdev later */
52 QLIST_ENTRY(PCIBus
) sibling
;/* this will be replaced by qdev later */
54 /* The bus IRQ state is the logical OR of the connected devices.
55 Keep a count of the number of devices with raised IRQs. */
60 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
62 static struct BusInfo pci_bus_info
= {
64 .size
= sizeof(PCIBus
),
65 .print_dev
= pcibus_dev_print
,
66 .props
= (Property
[]) {
67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
68 DEFINE_PROP_END_OF_LIST()
72 static void pci_update_mappings(PCIDevice
*d
);
73 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
75 target_phys_addr_t pci_mem_base
;
76 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
77 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
82 QLIST_ENTRY(PCIHostBus
) next
;
84 static QLIST_HEAD(, PCIHostBus
) host_buses
;
86 static const VMStateDescription vmstate_pcibus
= {
89 .minimum_version_id
= 1,
90 .minimum_version_id_old
= 1,
91 .fields
= (VMStateField
[]) {
92 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
93 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
98 static int pci_bar(PCIDevice
*d
, int reg
)
102 if (reg
!= PCI_ROM_SLOT
)
103 return PCI_BASE_ADDRESS_0
+ reg
* 4;
105 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
106 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
109 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
111 return (d
->irq_state
>> irq_num
) & 0x1;
114 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
116 d
->irq_state
&= ~(0x1 << irq_num
);
117 d
->irq_state
|= level
<< irq_num
;
120 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
125 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
128 pci_dev
= bus
->parent_dev
;
130 bus
->irq_count
[irq_num
] += change
;
131 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
134 /* Update interrupt status bit in config space on interrupt
136 static void pci_update_irq_status(PCIDevice
*dev
)
138 if (dev
->irq_state
) {
139 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
141 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
145 static void pci_device_reset(PCIDevice
*dev
)
150 pci_update_irq_status(dev
);
151 dev
->config
[PCI_COMMAND
] &= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
153 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
154 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
155 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
156 if (!dev
->io_regions
[r
].size
) {
159 pci_set_long(dev
->config
+ pci_bar(dev
, r
), dev
->io_regions
[r
].type
);
161 pci_update_mappings(dev
);
164 static void pci_bus_reset(void *opaque
)
166 PCIBus
*bus
= opaque
;
169 for (i
= 0; i
< bus
->nirq
; i
++) {
170 bus
->irq_count
[i
] = 0;
172 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
173 if (bus
->devices
[i
]) {
174 pci_device_reset(bus
->devices
[i
]);
179 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
181 struct PCIHostBus
*host
;
182 host
= qemu_mallocz(sizeof(*host
));
183 host
->domain
= domain
;
185 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
188 PCIBus
*pci_find_root_bus(int domain
)
190 struct PCIHostBus
*host
;
192 QLIST_FOREACH(host
, &host_buses
, next
) {
193 if (host
->domain
== domain
) {
201 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
202 const char *name
, int devfn_min
)
204 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
205 bus
->devfn_min
= devfn_min
;
208 QLIST_INIT(&bus
->child
);
209 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
211 vmstate_register(-1, &vmstate_pcibus
, bus
);
212 qemu_register_reset(pci_bus_reset
, bus
);
215 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
219 bus
= qemu_mallocz(sizeof(*bus
));
220 bus
->qbus
.qdev_allocated
= 1;
221 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
225 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
226 void *irq_opaque
, int nirq
)
228 bus
->set_irq
= set_irq
;
229 bus
->map_irq
= map_irq
;
230 bus
->irq_opaque
= irq_opaque
;
232 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
235 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
)
237 bus
->qbus
.allow_hotplug
= 1;
238 bus
->hotplug
= hotplug
;
241 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
242 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
243 void *irq_opaque
, int devfn_min
, int nirq
)
247 bus
= pci_bus_new(parent
, name
, devfn_min
);
248 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
252 static void pci_register_secondary_bus(PCIBus
*parent
,
255 pci_map_irq_fn map_irq
,
258 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
259 bus
->map_irq
= map_irq
;
260 bus
->parent_dev
= dev
;
262 QLIST_INIT(&bus
->child
);
263 QLIST_INSERT_HEAD(&parent
->child
, bus
, sibling
);
266 static void pci_unregister_secondary_bus(PCIBus
*bus
)
268 assert(QLIST_EMPTY(&bus
->child
));
269 QLIST_REMOVE(bus
, sibling
);
272 int pci_bus_num(PCIBus
*s
)
275 return 0; /* pci host bridge */
276 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
279 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
281 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
285 assert(size
== pci_config_size(s
));
286 config
= qemu_malloc(size
);
288 qemu_get_buffer(f
, config
, size
);
289 for (i
= 0; i
< size
; ++i
) {
290 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
]) {
295 memcpy(s
->config
, config
, size
);
297 pci_update_mappings(s
);
303 /* just put buffer */
304 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
306 const uint8_t **v
= pv
;
307 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
308 qemu_put_buffer(f
, *v
, size
);
311 static VMStateInfo vmstate_info_pci_config
= {
312 .name
= "pci config",
313 .get
= get_pci_config_device
,
314 .put
= put_pci_config_device
,
317 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
319 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
320 uint32_t irq_state
[PCI_NUM_PINS
];
322 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
323 irq_state
[i
] = qemu_get_be32(f
);
324 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
325 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
331 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
332 pci_set_irq_state(s
, i
, irq_state
[i
]);
338 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
341 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
343 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
344 qemu_put_be32(f
, pci_irq_state(s
, i
));
348 static VMStateInfo vmstate_info_pci_irq_state
= {
349 .name
= "pci irq state",
350 .get
= get_pci_irq_state
,
351 .put
= put_pci_irq_state
,
354 const VMStateDescription vmstate_pci_device
= {
357 .minimum_version_id
= 1,
358 .minimum_version_id_old
= 1,
359 .fields
= (VMStateField
[]) {
360 VMSTATE_INT32_LE(version_id
, PCIDevice
),
361 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
362 vmstate_info_pci_config
,
363 PCI_CONFIG_SPACE_SIZE
),
364 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
365 vmstate_info_pci_irq_state
,
366 PCI_NUM_PINS
* sizeof(int32_t)),
367 VMSTATE_END_OF_LIST()
371 const VMStateDescription vmstate_pcie_device
= {
374 .minimum_version_id
= 1,
375 .minimum_version_id_old
= 1,
376 .fields
= (VMStateField
[]) {
377 VMSTATE_INT32_LE(version_id
, PCIDevice
),
378 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
379 vmstate_info_pci_config
,
380 PCIE_CONFIG_SPACE_SIZE
),
381 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
382 vmstate_info_pci_irq_state
,
383 PCI_NUM_PINS
* sizeof(int32_t)),
384 VMSTATE_END_OF_LIST()
388 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
390 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
393 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
395 /* Clear interrupt status bit: it is implicit
396 * in irq_state which we are saving.
397 * This makes us compatible with old devices
398 * which never set or clear this bit. */
399 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
400 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
401 /* Restore the interrupt status bit. */
402 pci_update_irq_status(s
);
405 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
408 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
409 /* Restore the interrupt status bit. */
410 pci_update_irq_status(s
);
414 static int pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
418 id
= (void*)(&pci_dev
->config
[PCI_SUBVENDOR_ID
]);
419 id
[0] = cpu_to_le16(pci_default_sub_vendor_id
);
420 id
[1] = cpu_to_le16(pci_default_sub_device_id
);
425 * Parse pci address in qemu command
426 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
428 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
433 unsigned long dom
= 0, bus
= 0;
437 val
= strtoul(p
, &e
, 16);
443 val
= strtoul(p
, &e
, 16);
450 val
= strtoul(p
, &e
, 16);
456 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
464 /* Note: QEMU doesn't implement domains other than 0 */
465 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
475 * Parse device bdf in device assignment command:
477 * -pcidevice host=bus:dev.func
479 * Parse <bus>:<slot>.<func> return -1 on error
481 int pci_parse_host_devaddr(const char *addr
, int *busp
,
482 int *slotp
, int *funcp
)
487 int bus
= 0, slot
= 0, func
= 0;
490 val
= strtoul(p
, &e
, 16);
496 val
= strtoul(p
, &e
, 16);
502 val
= strtoul(p
, &e
, 16);
511 if (bus
> 0xff || slot
> 0x1f || func
> 0x7)
523 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
526 /* strip legacy tag */
527 if (!strncmp(addr
, "pci_addr=", 9)) {
530 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
531 monitor_printf(mon
, "Invalid pci address\n");
537 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
544 return pci_find_bus(pci_find_root_bus(0), 0);
547 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
552 return pci_find_bus(pci_find_root_bus(0), bus
);
555 static void pci_init_cmask(PCIDevice
*dev
)
557 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
558 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
559 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
560 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
561 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
562 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
563 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
564 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
567 static void pci_init_wmask(PCIDevice
*dev
)
569 int config_size
= pci_config_size(dev
);
571 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
572 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
573 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
574 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
575 PCI_COMMAND_INTX_DISABLE
);
577 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
578 config_size
- PCI_CONFIG_HEADER_SIZE
);
581 static void pci_init_wmask_bridge(PCIDevice
*d
)
583 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
584 PCI_SEC_LETENCY_TIMER */
585 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
588 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
589 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
590 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
591 PCI_MEMORY_RANGE_MASK
& 0xffff);
592 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
593 PCI_MEMORY_RANGE_MASK
& 0xffff);
594 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
595 PCI_PREF_RANGE_MASK
& 0xffff);
596 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
597 PCI_PREF_RANGE_MASK
& 0xffff);
599 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
600 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
602 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
, 0xffff);
605 static void pci_config_alloc(PCIDevice
*pci_dev
)
607 int config_size
= pci_config_size(pci_dev
);
609 pci_dev
->config
= qemu_mallocz(config_size
);
610 pci_dev
->cmask
= qemu_mallocz(config_size
);
611 pci_dev
->wmask
= qemu_mallocz(config_size
);
612 pci_dev
->used
= qemu_mallocz(config_size
);
615 static void pci_config_free(PCIDevice
*pci_dev
)
617 qemu_free(pci_dev
->config
);
618 qemu_free(pci_dev
->cmask
);
619 qemu_free(pci_dev
->wmask
);
620 qemu_free(pci_dev
->used
);
623 /* -1 for devfn means auto assign */
624 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
625 const char *name
, int devfn
,
626 PCIConfigReadFunc
*config_read
,
627 PCIConfigWriteFunc
*config_write
,
631 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
633 if (!bus
->devices
[devfn
])
636 qemu_error("PCI: no devfn available for %s, all in use\n", name
);
639 } else if (bus
->devices
[devfn
]) {
640 qemu_error("PCI: devfn %d not available for %s, in use by %s\n", devfn
,
641 name
, bus
->devices
[devfn
]->name
);
645 pci_dev
->devfn
= devfn
;
646 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
647 pci_dev
->irq_state
= 0;
648 pci_config_alloc(pci_dev
);
650 header_type
&= ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
651 if (header_type
== PCI_HEADER_TYPE_NORMAL
) {
652 pci_set_default_subsystem_id(pci_dev
);
654 pci_init_cmask(pci_dev
);
655 pci_init_wmask(pci_dev
);
656 if (header_type
== PCI_HEADER_TYPE_BRIDGE
) {
657 pci_init_wmask_bridge(pci_dev
);
661 config_read
= pci_default_read_config
;
663 config_write
= pci_default_write_config
;
664 pci_dev
->config_read
= config_read
;
665 pci_dev
->config_write
= config_write
;
666 bus
->devices
[devfn
] = pci_dev
;
667 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
668 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
672 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
673 int instance_size
, int devfn
,
674 PCIConfigReadFunc
*config_read
,
675 PCIConfigWriteFunc
*config_write
)
679 pci_dev
= qemu_mallocz(instance_size
);
680 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
681 config_read
, config_write
,
682 PCI_HEADER_TYPE_NORMAL
);
683 if (pci_dev
== NULL
) {
684 hw_error("PCI: can't register device\n");
688 static target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
690 return addr
+ pci_mem_base
;
693 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
698 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
699 r
= &pci_dev
->io_regions
[i
];
700 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
702 if (r
->type
== PCI_BASE_ADDRESS_SPACE_IO
) {
703 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
705 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
712 static int pci_unregister_device(DeviceState
*dev
)
714 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
715 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
719 ret
= info
->exit(pci_dev
);
723 pci_unregister_io_regions(pci_dev
);
725 qemu_free_irqs(pci_dev
->irq
);
726 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
727 pci_config_free(pci_dev
);
731 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
732 pcibus_t size
, int type
,
733 PCIMapIORegionFunc
*map_func
)
739 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
742 if (size
& (size
-1)) {
743 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
744 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
748 r
= &pci_dev
->io_regions
[region_num
];
749 r
->addr
= PCI_BAR_UNMAPPED
;
751 r
->filtered_size
= size
;
753 r
->map_func
= map_func
;
756 addr
= pci_bar(pci_dev
, region_num
);
757 if (region_num
== PCI_ROM_SLOT
) {
758 /* ROM enable bit is writeable */
759 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
761 pci_set_long(pci_dev
->config
+ addr
, type
);
762 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
763 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
764 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
765 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
767 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
768 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
772 static uint32_t pci_config_get_io_base(PCIDevice
*d
,
773 uint32_t base
, uint32_t base_upper16
)
777 val
= ((uint32_t)d
->config
[base
] & PCI_IO_RANGE_MASK
) << 8;
778 if (d
->config
[base
] & PCI_IO_RANGE_TYPE_32
) {
779 val
|= (uint32_t)pci_get_word(d
->config
+ base_upper16
) << 16;
784 static pcibus_t
pci_config_get_memory_base(PCIDevice
*d
, uint32_t base
)
786 return ((pcibus_t
)pci_get_word(d
->config
+ base
) & PCI_MEMORY_RANGE_MASK
)
790 static pcibus_t
pci_config_get_pref_base(PCIDevice
*d
,
791 uint32_t base
, uint32_t upper
)
796 tmp
= (pcibus_t
)pci_get_word(d
->config
+ base
);
797 val
= (tmp
& PCI_PREF_RANGE_MASK
) << 16;
798 if (tmp
& PCI_PREF_RANGE_TYPE_64
) {
799 val
|= (pcibus_t
)pci_get_long(d
->config
+ upper
) << 32;
804 static pcibus_t
pci_bridge_get_base(PCIDevice
*bridge
, uint8_t type
)
807 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
808 base
= pci_config_get_io_base(bridge
,
809 PCI_IO_BASE
, PCI_IO_BASE_UPPER16
);
811 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
812 base
= pci_config_get_pref_base(
813 bridge
, PCI_PREF_MEMORY_BASE
, PCI_PREF_BASE_UPPER32
);
815 base
= pci_config_get_memory_base(bridge
, PCI_MEMORY_BASE
);
822 static pcibus_t
pci_bridge_get_limit(PCIDevice
*bridge
, uint8_t type
)
825 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
826 limit
= pci_config_get_io_base(bridge
,
827 PCI_IO_LIMIT
, PCI_IO_LIMIT_UPPER16
);
828 limit
|= 0xfff; /* PCI bridge spec 3.2.5.6. */
830 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
831 limit
= pci_config_get_pref_base(
832 bridge
, PCI_PREF_MEMORY_LIMIT
, PCI_PREF_LIMIT_UPPER32
);
834 limit
= pci_config_get_memory_base(bridge
, PCI_MEMORY_LIMIT
);
836 limit
|= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
841 static void pci_bridge_filter(PCIDevice
*d
, pcibus_t
*addr
, pcibus_t
*size
,
844 pcibus_t base
= *addr
;
845 pcibus_t limit
= *addr
+ *size
- 1;
848 for (br
= d
->bus
->parent_dev
; br
; br
= br
->bus
->parent_dev
) {
849 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
851 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
852 if (!(cmd
& PCI_COMMAND_IO
)) {
856 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
861 base
= MAX(base
, pci_bridge_get_base(br
, type
));
862 limit
= MIN(limit
, pci_bridge_get_limit(br
, type
));
869 *size
= limit
- base
+ 1;
872 *addr
= PCI_BAR_UNMAPPED
;
876 static pcibus_t
pci_bar_address(PCIDevice
*d
,
877 int reg
, uint8_t type
, pcibus_t size
)
879 pcibus_t new_addr
, last_addr
;
880 int bar
= pci_bar(d
, reg
);
881 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
883 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
884 if (!(cmd
& PCI_COMMAND_IO
)) {
885 return PCI_BAR_UNMAPPED
;
887 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
888 last_addr
= new_addr
+ size
- 1;
889 /* NOTE: we have only 64K ioports on PC */
890 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
891 return PCI_BAR_UNMAPPED
;
896 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
897 return PCI_BAR_UNMAPPED
;
899 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
900 new_addr
= pci_get_quad(d
->config
+ bar
);
902 new_addr
= pci_get_long(d
->config
+ bar
);
904 /* the ROM slot has a specific enable bit */
905 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
906 return PCI_BAR_UNMAPPED
;
908 new_addr
&= ~(size
- 1);
909 last_addr
= new_addr
+ size
- 1;
910 /* NOTE: we do not support wrapping */
911 /* XXX: as we cannot support really dynamic
912 mappings, we handle specific values as invalid
914 if (last_addr
<= new_addr
|| new_addr
== 0 ||
915 last_addr
== PCI_BAR_UNMAPPED
) {
916 return PCI_BAR_UNMAPPED
;
919 /* Now pcibus_t is 64bit.
920 * Check if 32 bit BAR wraps around explicitly.
921 * Without this, PC ide doesn't work well.
922 * TODO: remove this work around.
924 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
925 return PCI_BAR_UNMAPPED
;
929 * OS is allowed to set BAR beyond its addressable
930 * bits. For example, 32 bit OS can set 64bit bar
931 * to >4G. Check it. TODO: we might need to support
932 * it in the future for e.g. PAE.
934 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
935 return PCI_BAR_UNMAPPED
;
941 static void pci_update_mappings(PCIDevice
*d
)
945 pcibus_t new_addr
, filtered_size
;
947 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
948 r
= &d
->io_regions
[i
];
950 /* this region isn't registered */
954 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
956 /* bridge filtering */
957 filtered_size
= r
->size
;
958 if (new_addr
!= PCI_BAR_UNMAPPED
) {
959 pci_bridge_filter(d
, &new_addr
, &filtered_size
, r
->type
);
962 /* This bar isn't changed */
963 if (new_addr
== r
->addr
&& filtered_size
== r
->filtered_size
)
966 /* now do the real mapping */
967 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
968 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
970 /* NOTE: specific hack for IDE in PC case:
971 only one byte must be mapped. */
972 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
973 if (class == 0x0101 && r
->size
== 4) {
974 isa_unassign_ioport(r
->addr
+ 2, 1);
976 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
979 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
982 qemu_unregister_coalesced_mmio(r
->addr
, r
->filtered_size
);
986 r
->filtered_size
= filtered_size
;
987 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
989 * TODO: currently almost all the map funcions assumes
990 * filtered_size == size and addr & ~(size - 1) == addr.
991 * However with bridge filtering, they aren't always true.
992 * Teach them such cases, such that filtered_size < size and
993 * addr & (size - 1) != 0.
995 r
->map_func(d
, i
, r
->addr
, r
->filtered_size
, r
->type
);
1000 static inline int pci_irq_disabled(PCIDevice
*d
)
1002 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1005 /* Called after interrupt disabled field update in config space,
1006 * assert/deassert interrupts if necessary.
1007 * Gets original interrupt disable bit value (before update). */
1008 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1010 int i
, disabled
= pci_irq_disabled(d
);
1011 if (disabled
== was_irq_disabled
)
1013 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1014 int state
= pci_irq_state(d
, i
);
1015 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1019 static uint32_t pci_read_config(PCIDevice
*d
,
1020 uint32_t address
, int len
)
1024 len
= MIN(len
, pci_config_size(d
) - address
);
1025 memcpy(&val
, d
->config
+ address
, len
);
1026 return le32_to_cpu(val
);
1029 uint32_t pci_default_read_config(PCIDevice
*d
,
1030 uint32_t address
, int len
)
1032 assert(len
== 1 || len
== 2 || len
== 4);
1034 if (pci_access_cap_config(d
, address
, len
)) {
1035 return d
->cap
.config_read(d
, address
, len
);
1038 return pci_read_config(d
, address
, len
);
1041 static void pci_write_config(PCIDevice
*pci_dev
,
1042 uint32_t address
, uint32_t val
, int len
)
1045 for (i
= 0; i
< len
; i
++) {
1046 pci_dev
->config
[address
+ i
] = val
& 0xff;
1051 int pci_access_cap_config(PCIDevice
*pci_dev
, uint32_t address
, int len
)
1053 if (pci_dev
->cap
.supported
&& address
>= pci_dev
->cap
.start
&&
1054 (address
+ len
) < pci_dev
->cap
.start
+ pci_dev
->cap
.length
)
1059 uint32_t pci_default_cap_read_config(PCIDevice
*pci_dev
,
1060 uint32_t address
, int len
)
1062 return pci_read_config(pci_dev
, address
, len
);
1065 void pci_default_cap_write_config(PCIDevice
*pci_dev
,
1066 uint32_t address
, uint32_t val
, int len
)
1068 pci_write_config(pci_dev
, address
, val
, len
);
1071 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1073 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1074 uint32_t config_size
= pci_config_size(d
);
1076 if (pci_access_cap_config(d
, addr
, l
)) {
1077 d
->cap
.config_write(d
, addr
, val
, l
);
1081 for (i
= 0; i
< l
&& addr
+ i
< config_size
; val
>>= 8, ++i
) {
1082 uint8_t wmask
= d
->wmask
[addr
+ i
];
1083 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1086 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1087 if (kvm_enabled() && kvm_irqchip_in_kernel() &&
1088 addr
>= PIIX_CONFIG_IRQ_ROUTE
&&
1089 addr
< PIIX_CONFIG_IRQ_ROUTE
+ 4)
1090 assigned_dev_update_irqs();
1091 #endif /* CONFIG_KVM_DEVICE_ASSIGNMENT */
1093 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1094 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1095 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1096 range_covers_byte(addr
, l
, PCI_COMMAND
))
1097 pci_update_mappings(d
);
1099 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1100 pci_update_irq_disabled(d
, was_irq_disabled
);
1103 /***********************************************************/
1104 /* generic PCI irq support */
1106 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1107 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1109 PCIDevice
*pci_dev
= opaque
;
1112 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1116 #if defined(TARGET_IA64)
1117 ioapic_set_irq(pci_dev
, irq_num
, level
);
1120 pci_set_irq_state(pci_dev
, irq_num
, level
);
1121 pci_update_irq_status(pci_dev
);
1122 if (pci_irq_disabled(pci_dev
))
1124 pci_change_irq_level(pci_dev
, irq_num
, change
);
1127 int pci_map_irq(PCIDevice
*pci_dev
, int pin
)
1129 return pci_dev
->bus
->map_irq(pci_dev
, pin
);
1132 /***********************************************************/
1133 /* monitor info on PCI */
1140 static const pci_class_desc pci_class_descriptions
[] =
1142 { 0x0100, "SCSI controller"},
1143 { 0x0101, "IDE controller"},
1144 { 0x0102, "Floppy controller"},
1145 { 0x0103, "IPI controller"},
1146 { 0x0104, "RAID controller"},
1147 { 0x0106, "SATA controller"},
1148 { 0x0107, "SAS controller"},
1149 { 0x0180, "Storage controller"},
1150 { 0x0200, "Ethernet controller"},
1151 { 0x0201, "Token Ring controller"},
1152 { 0x0202, "FDDI controller"},
1153 { 0x0203, "ATM controller"},
1154 { 0x0280, "Network controller"},
1155 { 0x0300, "VGA controller"},
1156 { 0x0301, "XGA controller"},
1157 { 0x0302, "3D controller"},
1158 { 0x0380, "Display controller"},
1159 { 0x0400, "Video controller"},
1160 { 0x0401, "Audio controller"},
1162 { 0x0480, "Multimedia controller"},
1163 { 0x0500, "RAM controller"},
1164 { 0x0501, "Flash controller"},
1165 { 0x0580, "Memory controller"},
1166 { 0x0600, "Host bridge"},
1167 { 0x0601, "ISA bridge"},
1168 { 0x0602, "EISA bridge"},
1169 { 0x0603, "MC bridge"},
1170 { 0x0604, "PCI bridge"},
1171 { 0x0605, "PCMCIA bridge"},
1172 { 0x0606, "NUBUS bridge"},
1173 { 0x0607, "CARDBUS bridge"},
1174 { 0x0608, "RACEWAY bridge"},
1175 { 0x0680, "Bridge"},
1176 { 0x0c03, "USB controller"},
1180 static void pci_info_device(PCIBus
*bus
, PCIDevice
*d
)
1182 Monitor
*mon
= cur_mon
;
1185 const pci_class_desc
*desc
;
1187 monitor_printf(mon
, " Bus %2d, device %3d, function %d:\n",
1188 pci_bus_num(d
->bus
),
1189 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
));
1190 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1191 monitor_printf(mon
, " ");
1192 desc
= pci_class_descriptions
;
1193 while (desc
->desc
&& class != desc
->class)
1196 monitor_printf(mon
, "%s", desc
->desc
);
1198 monitor_printf(mon
, "Class %04x", class);
1200 monitor_printf(mon
, ": PCI device %04x:%04x\n",
1201 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1202 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
1204 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
1205 monitor_printf(mon
, " IRQ %d.\n",
1206 d
->config
[PCI_INTERRUPT_LINE
]);
1208 if (class == 0x0604) {
1212 monitor_printf(mon
, " BUS %d.\n", d
->config
[0x19]);
1213 monitor_printf(mon
, " secondary bus %d.\n",
1214 d
->config
[PCI_SECONDARY_BUS
]);
1215 monitor_printf(mon
, " subordinate bus %d.\n",
1216 d
->config
[PCI_SUBORDINATE_BUS
]);
1218 base
= pci_bridge_get_base(d
, PCI_BASE_ADDRESS_SPACE_IO
);
1219 limit
= pci_bridge_get_limit(d
, PCI_BASE_ADDRESS_SPACE_IO
);
1220 monitor_printf(mon
, " IO range [0x%04"PRIx64
", 0x%04"PRIx64
"]\n",
1223 base
= pci_bridge_get_base(d
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1224 limit
= pci_bridge_get_limit(d
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1226 " memory range [0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1229 base
= pci_bridge_get_base(d
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1230 PCI_BASE_ADDRESS_MEM_PREFETCH
);
1231 limit
= pci_bridge_get_limit(d
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1232 PCI_BASE_ADDRESS_MEM_PREFETCH
);
1233 monitor_printf(mon
, " prefetchable memory range "
1234 "[0x%08"PRIx64
", 0x%08"PRIx64
"]\n", base
, limit
);
1236 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
1237 r
= &d
->io_regions
[i
];
1239 monitor_printf(mon
, " BAR%d: ", i
);
1240 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1241 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
1242 " [0x%04"FMT_PCIBUS
"].\n",
1243 r
->addr
, r
->addr
+ r
->size
- 1);
1245 const char *type
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
?
1246 "64 bit" : "32 bit";
1247 const char *prefetch
=
1248 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
?
1249 " prefetchable" : "";
1251 monitor_printf(mon
, "%s%s memory at 0x%08"FMT_PCIBUS
1252 " [0x%08"FMT_PCIBUS
"].\n",
1254 r
->addr
, r
->addr
+ r
->size
- 1);
1258 monitor_printf(mon
, " id \"%s\"\n", d
->qdev
.id
? d
->qdev
.id
: "");
1259 if (class == 0x0604 && d
->config
[0x19] != 0) {
1260 pci_for_each_device(bus
, d
->config
[0x19], pci_info_device
);
1264 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1265 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1270 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1271 d
= bus
->devices
[devfn
];
1277 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1278 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1280 bus
= pci_find_bus(bus
, bus_num
);
1283 pci_for_each_device_under_bus(bus
, fn
);
1287 void pci_info(Monitor
*mon
)
1289 struct PCIHostBus
*host
;
1290 QLIST_FOREACH(host
, &host_buses
, next
) {
1291 pci_for_each_device(host
->bus
, 0, pci_info_device
);
1295 static const char * const pci_nic_models
[] = {
1307 static const char * const pci_nic_names
[] = {
1319 /* Initialize a PCI NIC. */
1320 /* FIXME callers should check for failure, but don't */
1321 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1322 const char *default_devaddr
)
1324 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1331 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1335 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1337 qemu_error("Invalid PCI device address %s for device %s\n",
1338 devaddr
, pci_nic_names
[i
]);
1342 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1343 dev
= &pci_dev
->qdev
;
1345 dev
->id
= qemu_strdup(nd
->name
);
1346 qdev_set_nic_properties(dev
, nd
);
1347 if (qdev_init(dev
) < 0)
1352 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1353 const char *default_devaddr
)
1357 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1360 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1374 static void pci_bridge_update_mappings_fn(PCIBus
*b
, PCIDevice
*d
)
1376 pci_update_mappings(d
);
1379 static void pci_bridge_update_mappings(PCIBus
*b
)
1383 pci_for_each_device_under_bus(b
, pci_bridge_update_mappings_fn
);
1385 QLIST_FOREACH(child
, &b
->child
, sibling
) {
1386 pci_bridge_update_mappings(child
);
1390 static void pci_bridge_write_config(PCIDevice
*d
,
1391 uint32_t address
, uint32_t val
, int len
)
1393 pci_default_write_config(d
, address
, val
, len
);
1395 if (/* io base/limit */
1396 ranges_overlap(address
, len
, PCI_IO_BASE
, 2) ||
1398 /* memory base/limit, prefetchable base/limit and
1399 io base/limit upper 16 */
1400 ranges_overlap(address
, len
, PCI_MEMORY_BASE
, 20)) {
1401 pci_bridge_update_mappings(d
->bus
);
1405 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1412 if (pci_bus_num(bus
) == bus_num
) {
1417 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1419 if (!bus
->parent_dev
/* pci host bridge */
1420 || (pci_bus_num(sec
) <= bus_num
&&
1421 bus
->parent_dev
->config
[PCI_SUBORDINATE_BUS
])) {
1422 return pci_find_bus(sec
, bus_num
);
1429 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, int slot
, int function
)
1431 bus
= pci_find_bus(bus
, bus_num
);
1436 return bus
->devices
[PCI_DEVFN(slot
, function
)];
1439 static int pci_bridge_initfn(PCIDevice
*dev
)
1441 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1443 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
1444 pci_config_set_device_id(s
->dev
.config
, s
->did
);
1446 pci_set_word(dev
->config
+ PCI_STATUS
,
1447 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1448 pci_config_set_class(dev
->config
, PCI_CLASS_BRIDGE_PCI
);
1449 dev
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_BRIDGE
;
1450 pci_set_word(dev
->config
+ PCI_SEC_STATUS
,
1451 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1455 static int pci_bridge_exitfn(PCIDevice
*pci_dev
)
1457 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, pci_dev
);
1458 PCIBus
*bus
= &s
->bus
;
1459 pci_unregister_secondary_bus(bus
);
1463 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
1464 pci_map_irq_fn map_irq
, const char *name
)
1469 dev
= pci_create(bus
, devfn
, "pci-bridge");
1470 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
1471 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
1472 qdev_init_nofail(&dev
->qdev
);
1474 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1475 pci_register_secondary_bus(bus
, &s
->bus
, &s
->dev
, map_irq
, name
);
1479 PCIDevice
*pci_bridge_get_device(PCIBus
*bus
)
1481 return bus
->parent_dev
;
1484 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1486 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1487 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
1491 /* initialize cap_present for pci_is_express() and pci_config_size() */
1492 if (info
->is_express
) {
1493 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1496 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1497 devfn
= pci_dev
->devfn
;
1498 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
1499 info
->config_read
, info
->config_write
,
1501 if (pci_dev
== NULL
)
1503 rc
= info
->init(pci_dev
);
1506 if (qdev
->hotplugged
)
1507 bus
->hotplug(pci_dev
, 1);
1511 static int pci_unplug_device(DeviceState
*qdev
)
1513 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1515 dev
->bus
->hotplug(dev
, 0);
1519 void pci_qdev_register(PCIDeviceInfo
*info
)
1521 info
->qdev
.init
= pci_qdev_init
;
1522 info
->qdev
.unplug
= pci_unplug_device
;
1523 info
->qdev
.exit
= pci_unregister_device
;
1524 info
->qdev
.bus_info
= &pci_bus_info
;
1525 qdev_register(&info
->qdev
);
1528 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1530 while (info
->qdev
.name
) {
1531 pci_qdev_register(info
);
1536 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1540 dev
= qdev_create(&bus
->qbus
, name
);
1541 qdev_prop_set_uint32(dev
, "addr", devfn
);
1542 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1545 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1547 PCIDevice
*dev
= pci_create(bus
, devfn
, name
);
1548 qdev_init_nofail(&dev
->qdev
);
1552 int pci_enable_capability_support(PCIDevice
*pci_dev
,
1553 uint32_t config_start
,
1554 PCICapConfigReadFunc
*config_read
,
1555 PCICapConfigWriteFunc
*config_write
,
1556 PCICapConfigInitFunc
*config_init
)
1561 pci_dev
->config
[0x06] |= 0x10; // status = capabilities
1563 if (config_start
== 0)
1564 pci_dev
->cap
.start
= PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR
;
1565 else if (config_start
>= 0x40 && config_start
< 0xff)
1566 pci_dev
->cap
.start
= config_start
;
1571 pci_dev
->cap
.config_read
= config_read
;
1573 pci_dev
->cap
.config_read
= pci_default_cap_read_config
;
1575 pci_dev
->cap
.config_write
= config_write
;
1577 pci_dev
->cap
.config_write
= pci_default_cap_write_config
;
1578 pci_dev
->cap
.supported
= 1;
1579 pci_dev
->config
[PCI_CAPABILITY_LIST
] = pci_dev
->cap
.start
;
1580 return config_init(pci_dev
);
1583 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1585 int config_size
= pci_config_size(pdev
);
1586 int offset
= PCI_CONFIG_HEADER_SIZE
;
1588 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1591 else if (i
- offset
+ 1 == size
)
1596 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1601 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1604 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1605 prev
= next
+ PCI_CAP_LIST_NEXT
)
1606 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1614 /* Reserve space and add capability to the linked list in pci config space */
1615 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1617 uint8_t offset
= pci_find_space(pdev
, size
);
1618 uint8_t *config
= pdev
->config
+ offset
;
1621 config
[PCI_CAP_LIST_ID
] = cap_id
;
1622 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1623 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1624 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1625 memset(pdev
->used
+ offset
, 0xFF, size
);
1626 /* Make capability read-only by default */
1627 memset(pdev
->wmask
+ offset
, 0, size
);
1628 /* Check capability by default */
1629 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1633 /* Unlink capability from the pci config space. */
1634 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1636 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1639 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1640 /* Make capability writeable again */
1641 memset(pdev
->wmask
+ offset
, 0xff, size
);
1642 /* Clear cmask as device-specific registers can't be checked */
1643 memset(pdev
->cmask
+ offset
, 0, size
);
1644 memset(pdev
->used
+ offset
, 0, size
);
1646 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1647 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1650 /* Reserve space for capability at a known offset (to call after load). */
1651 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
1653 memset(pdev
->used
+ offset
, 0xff, size
);
1656 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1658 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1661 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1663 PCIDevice
*d
= (PCIDevice
*)dev
;
1664 const pci_class_desc
*desc
;
1669 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1670 desc
= pci_class_descriptions
;
1671 while (desc
->desc
&& class != desc
->class)
1674 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1676 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1679 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1680 "pci id %04x:%04x (sub %04x:%04x)\n",
1682 d
->config
[PCI_SECONDARY_BUS
],
1683 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1684 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1685 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1686 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1687 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1688 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1689 r
= &d
->io_regions
[i
];
1692 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1693 " [0x%"FMT_PCIBUS
"]\n",
1695 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1696 r
->addr
, r
->addr
+ r
->size
- 1);
1700 static PCIDeviceInfo bridge_info
= {
1701 .qdev
.name
= "pci-bridge",
1702 .qdev
.size
= sizeof(PCIBridge
),
1703 .init
= pci_bridge_initfn
,
1704 .exit
= pci_bridge_exitfn
,
1705 .config_write
= pci_bridge_write_config
,
1706 .qdev
.props
= (Property
[]) {
1707 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
1708 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
1709 DEFINE_PROP_END_OF_LIST(),
1713 static void pci_register_devices(void)
1715 pci_qdev_register(&bridge_info
);
1718 device_init(pci_register_devices
)