hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "pci.h"
  21 #include "qemu-timer.h"
  22 #include "sysemu.h"
  23 #include "i2c.h"
  24 #include "smbus.h"
  25 #include "kvm.h"
  26 #include "qemu-kvm.h"
  27 #include "string.h"
  28
  29 //#define DEBUG
  30
  31 /* i82731AB (PIIX4) compatible power management function */
  32 #define PM_FREQ 3579545
  33
  34 #define ACPI_DBG_IO_ADDR  0xb044
  35
  36 typedef struct PIIX4PMState {
  37     PCIDevice dev;
  38     uint16_t pmsts;
  39     uint16_t pmen;
  40     uint16_t pmcntrl;
  41     uint8_t apmc;
  42     uint8_t apms;
  43     QEMUTimer *tmr_timer;
  44     int64_t tmr_overflow_time;
  45     i2c_bus *smbus;
  46     uint8_t smb_stat;
  47     uint8_t smb_ctl;
  48     uint8_t smb_cmd;
  49     uint8_t smb_addr;
  50     uint8_t smb_data0;
  51     uint8_t smb_data1;
  52     uint8_t smb_data[32];
  53     uint8_t smb_index;
  54     qemu_irq irq;
  55 } PIIX4PMState;
  56
  57 #define RSM_STS (1 << 15)
  58 #define PWRBTN_STS (1 << 8)
  59 #define RTC_EN (1 << 10)
  60 #define PWRBTN_EN (1 << 8)
  61 #define GBL_EN (1 << 5)
  62 #define TMROF_EN (1 << 0)
  63
  64 #define SCI_EN (1 << 0)
  65
  66 #define SUS_EN (1 << 13)
  67
  68 #define ACPI_ENABLE 0xf1
  69 #define ACPI_DISABLE 0xf0
  70
  71 #define SMBHSTSTS 0x00
  72 #define SMBHSTCNT 0x02
  73 #define SMBHSTCMD 0x03
  74 #define SMBHSTADD 0x04
  75 #define SMBHSTDAT0 0x05
  76 #define SMBHSTDAT1 0x06
  77 #define SMBBLKDAT 0x07
  78
  79 static PIIX4PMState *pm_state;
  80
  81 static uint32_t get_pmtmr(PIIX4PMState *s)
  82 {
  83     uint32_t d;
  84     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  85     return d & 0xffffff;
  86 }
  87
  88 static int get_pmsts(PIIX4PMState *s)
  89 {
  90     int64_t d;
  91     int pmsts;
  92     pmsts = s->pmsts;
  93     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  94     if (d >= s->tmr_overflow_time)
  95         s->pmsts |= TMROF_EN;
  96     return s->pmsts;
  97 }
  98
  99 static void pm_update_sci(PIIX4PMState *s)
 100 {
 101     int sci_level, pmsts;
 102     int64_t expire_time;
 103
 104     pmsts = get_pmsts(s);
 105     sci_level = (((pmsts & s->pmen) &
 106                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 107     qemu_set_irq(s->irq, sci_level);
 108     /* schedule a timer interruption if needed */
 109     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 110         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_FREQ);
 111         qemu_mod_timer(s->tmr_timer, expire_time);
 112     } else {
 113         qemu_del_timer(s->tmr_timer);
 114     }
 115 }
 116
 117 static void pm_tmr_timer(void *opaque)
 118 {
 119     PIIX4PMState *s = opaque;
 120     pm_update_sci(s);
 121 }
 122
 123 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 124 {
 125     PIIX4PMState *s = opaque;
 126     addr &= 0x3f;
 127     switch(addr) {
 128     case 0x00:
 129         {
 130             int64_t d;
 131             int pmsts;
 132             pmsts = get_pmsts(s);
 133             if (pmsts & val & TMROF_EN) {
 134                 /* if TMRSTS is reset, then compute the new overflow time */
 135                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ,
 136                              get_ticks_per_sec());
 137                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 138             }
 139             s->pmsts &= ~val;
 140             pm_update_sci(s);
 141         }
 142         break;
 143     case 0x02:
 144         s->pmen = val;
 145         pm_update_sci(s);
 146         break;
 147     case 0x04:
 148         {
 149             int sus_typ;
 150             s->pmcntrl = val & ~(SUS_EN);
 151             if (val & SUS_EN) {
 152                 /* change suspend type */
 153                 sus_typ = (val >> 10) & 7;
 154                 switch(sus_typ) {
 155                 case 0: /* soft power off */
 156                     qemu_system_shutdown_request();
 157                     break;
 158                 case 1:
 159                     /* RSM_STS should be set on resume. Pretend that resume
 160                        was caused by power button */
 161                     s->pmsts |= (RSM_STS | PWRBTN_STS);
 162                     qemu_system_reset_request();
 163 #if defined(TARGET_I386)
 164                     cmos_set_s3_resume();
 165 #endif
 166                 default:
 167                     break;
 168                 }
 169             }
 170         }
 171         break;
 172     default:
 173         break;
 174     }
 175 #ifdef DEBUG
 176     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 177 #endif
 178 }
 179
 180 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 181 {
 182     PIIX4PMState *s = opaque;
 183     uint32_t val;
 184
 185     addr &= 0x3f;
 186     switch(addr) {
 187     case 0x00:
 188         val = get_pmsts(s);
 189         break;
 190     case 0x02:
 191         val = s->pmen;
 192         break;
 193     case 0x04:
 194         val = s->pmcntrl;
 195         break;
 196     default:
 197         val = 0;
 198         break;
 199     }
 200 #ifdef DEBUG
 201     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 202 #endif
 203     return val;
 204 }
 205
 206 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 207 {
 208     //    PIIX4PMState *s = opaque;
 209     addr &= 0x3f;
 210 #ifdef DEBUG
 211     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 212 #endif
 213 }
 214
 215 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 216 {
 217     PIIX4PMState *s = opaque;
 218     uint32_t val;
 219
 220     addr &= 0x3f;
 221     switch(addr) {
 222     case 0x08:
 223         val = get_pmtmr(s);
 224         break;
 225     default:
 226         val = 0;
 227         break;
 228     }
 229 #ifdef DEBUG
 230     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 231 #endif
 232     return val;
 233 }
 234
 235 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 236 {
 237     PIIX4PMState *s = opaque;
 238     addr &= 1;
 239 #ifdef DEBUG
 240     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 241 #endif
 242     if (addr == 0) {
 243         s->apmc = val;
 244
 245         /* ACPI specs 3.0, 4.7.2.5 */
 246         if (val == ACPI_ENABLE) {
 247             s->pmcntrl |= SCI_EN;
 248         } else if (val == ACPI_DISABLE) {
 249             s->pmcntrl &= ~SCI_EN;
 250         }
 251
 252         if (s->dev.config[0x5b] & (1 << 1)) {
 253             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 254         }
 255     } else {
 256         s->apms = val;
 257     }
 258 }
 259
 260 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 261 {
 262     PIIX4PMState *s = opaque;
 263     uint32_t val;
 264
 265     addr &= 1;
 266     if (addr == 0) {
 267         val = s->apmc;
 268     } else {
 269         val = s->apms;
 270     }
 271 #ifdef DEBUG
 272     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 273 #endif
 274     return val;
 275 }
 276
 277 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 278 {
 279 #if defined(DEBUG)
 280     printf("ACPI: DBG: 0x%08x\n", val);
 281 #endif
 282 }
 283
 284 static void smb_transaction(PIIX4PMState *s)
 285 {
 286     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 287     uint8_t read = s->smb_addr & 0x01;
 288     uint8_t cmd = s->smb_cmd;
 289     uint8_t addr = s->smb_addr >> 1;
 290     i2c_bus *bus = s->smbus;
 291
 292 #ifdef DEBUG
 293     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 294 #endif
 295     switch(prot) {
 296     case 0x0:
 297         smbus_quick_command(bus, addr, read);
 298         break;
 299     case 0x1:
 300         if (read) {
 301             s->smb_data0 = smbus_receive_byte(bus, addr);
 302         } else {
 303             smbus_send_byte(bus, addr, cmd);
 304         }
 305         break;
 306     case 0x2:
 307         if (read) {
 308             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 309         } else {
 310             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 311         }
 312         break;
 313     case 0x3:
 314         if (read) {
 315             uint16_t val;
 316             val = smbus_read_word(bus, addr, cmd);
 317             s->smb_data0 = val;
 318             s->smb_data1 = val >> 8;
 319         } else {
 320             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 321         }
 322         break;
 323     case 0x5:
 324         if (read) {
 325             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 326         } else {
 327             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 328         }
 329         break;
 330     default:
 331         goto error;
 332     }
 333     return;
 334
 335   error:
 336     s->smb_stat |= 0x04;
 337 }
 338
 339 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 340 {
 341     PIIX4PMState *s = opaque;
 342     addr &= 0x3f;
 343 #ifdef DEBUG
 344     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 345 #endif
 346     switch(addr) {
 347     case SMBHSTSTS:
 348         s->smb_stat = 0;
 349         s->smb_index = 0;
 350         break;
 351     case SMBHSTCNT:
 352         s->smb_ctl = val;
 353         if (val & 0x40)
 354             smb_transaction(s);
 355         break;
 356     case SMBHSTCMD:
 357         s->smb_cmd = val;
 358         break;
 359     case SMBHSTADD:
 360         s->smb_addr = val;
 361         break;
 362     case SMBHSTDAT0:
 363         s->smb_data0 = val;
 364         break;
 365     case SMBHSTDAT1:
 366         s->smb_data1 = val;
 367         break;
 368     case SMBBLKDAT:
 369         s->smb_data[s->smb_index++] = val;
 370         if (s->smb_index > 31)
 371             s->smb_index = 0;
 372         break;
 373     default:
 374         break;
 375     }
 376 }
 377
 378 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 379 {
 380     PIIX4PMState *s = opaque;
 381     uint32_t val;
 382
 383     addr &= 0x3f;
 384     switch(addr) {
 385     case SMBHSTSTS:
 386         val = s->smb_stat;
 387         break;
 388     case SMBHSTCNT:
 389         s->smb_index = 0;
 390         val = s->smb_ctl & 0x1f;
 391         break;
 392     case SMBHSTCMD:
 393         val = s->smb_cmd;
 394         break;
 395     case SMBHSTADD:
 396         val = s->smb_addr;
 397         break;
 398     case SMBHSTDAT0:
 399         val = s->smb_data0;
 400         break;
 401     case SMBHSTDAT1:
 402         val = s->smb_data1;
 403         break;
 404     case SMBBLKDAT:
 405         val = s->smb_data[s->smb_index++];
 406         if (s->smb_index > 31)
 407             s->smb_index = 0;
 408         break;
 409     default:
 410         val = 0;
 411         break;
 412     }
 413 #ifdef DEBUG
 414     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 415 #endif
 416     return val;
 417 }
 418
 419 static void pm_io_space_update(PIIX4PMState *s)
 420 {
 421     uint32_t pm_io_base;
 422
 423     if (s->dev.config[0x80] & 1) {
 424         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 425         pm_io_base &= 0xffc0;
 426
 427         /* XXX: need to improve memory and ioport allocation */
 428 #if defined(DEBUG)
 429         printf("PM: mapping to 0x%x\n", pm_io_base);
 430 #endif
 431         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 432         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 433         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 434         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 435     }
 436 }
 437
 438 static void pm_write_config(PCIDevice *d,
 439                             uint32_t address, uint32_t val, int len)
 440 {
 441     pci_default_write_config(d, address, val, len);
 442     if (address == 0x80)
 443         pm_io_space_update((PIIX4PMState *)d);
 444 }
 445
 446 static int vmstate_acpi_post_load(void *opaque, int version_id)
 447 {
 448     PIIX4PMState *s = opaque;
 449
 450     pm_io_space_update(s);
 451     return 0;
 452 }
 453
 454 static const VMStateDescription vmstate_acpi = {
 455     .name = "piix4_pm",
 456     .version_id = 1,
 457     .minimum_version_id = 1,
 458     .minimum_version_id_old = 1,
 459     .post_load = vmstate_acpi_post_load,
 460     .fields      = (VMStateField []) {
 461         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 462         VMSTATE_UINT16(pmsts, PIIX4PMState),
 463         VMSTATE_UINT16(pmen, PIIX4PMState),
 464         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 465         VMSTATE_UINT8(apmc, PIIX4PMState),
 466         VMSTATE_UINT8(apms, PIIX4PMState),
 467         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 468         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 469         VMSTATE_END_OF_LIST()
 470     }
 471 };
 472
 473 static void piix4_reset(void *opaque)
 474 {
 475     PIIX4PMState *s = opaque;
 476     uint8_t *pci_conf = s->dev.config;
 477
 478     pci_conf[0x58] = 0;
 479     pci_conf[0x59] = 0;
 480     pci_conf[0x5a] = 0;
 481     pci_conf[0x5b] = 0;
 482
 483     if (kvm_enabled()) {
 484         /* Mark SMM as already inited (until KVM supports SMM). */
 485         pci_conf[0x5B] = 0x02;
 486     }
 487 }
 488
 489 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 490 {
 491 #if defined(TARGET_I386)
 492     PIIX4PMState *s = opaque;
 493
 494     if (!s) {
 495         qemu_system_shutdown_request();
 496     } else if (s->pmen & PWRBTN_EN) {
 497         s->pmsts |= PWRBTN_EN;
 498         pm_update_sci(s);
 499     }
 500 #endif
 501 }
 502
 503 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 504                        qemu_irq sci_irq)
 505 {
 506     PIIX4PMState *s;
 507     uint8_t *pci_conf;
 508
 509     s = (PIIX4PMState *)pci_register_device(bus,
 510                                          "PM", sizeof(PIIX4PMState),
 511                                          devfn, NULL, pm_write_config);
 512     pm_state = s;
 513     pci_conf = s->dev.config;
 514     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 515     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 516     pci_conf[0x06] = 0x80;
 517     pci_conf[0x07] = 0x02;
 518     pci_conf[0x08] = 0x03; // revision number
 519     pci_conf[0x09] = 0x00;
 520     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 521     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 522     pci_conf[0x3d] = 0x01; // interrupt pin 1
 523
 524     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 525
 526 #if defined(TARGET_IA64)
 527     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 528     pci_conf[0x41] = 0x1f;
 529     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 530     s->pmcntrl = SCI_EN;
 531 #endif
 532
 533     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 534     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 535
 536     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 537
 538     if (kvm_enabled()) {
 539         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 540          * support SMM mode. */
 541         pci_conf[0x5B] = 0x02;
 542     }
 543
 544     /* XXX: which specification is used ? The i82731AB has different
 545        mappings */
 546     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 547     pci_conf[0x63] = 0x60;
 548     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 549         (serial_hds[1] != NULL ? 0x90 : 0);
 550
 551     pci_conf[0x90] = smb_io_base | 1;
 552     pci_conf[0x91] = smb_io_base >> 8;
 553     pci_conf[0xd2] = 0x09;
 554     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 555     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 556
 557     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 558
 559     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 560
 561     vmstate_register(0, &vmstate_acpi, s);
 562
 563     s->smbus = i2c_init_bus(NULL, "i2c");
 564     s->irq = sci_irq;
 565     qemu_register_reset(piix4_reset, s);
 566
 567     return s->smbus;
 568 }
 569
 570 #define GPE_BASE 0xafe0
 571 #define PROC_BASE 0xaf00
 572 #define PCI_BASE 0xae00
 573 #define PCI_EJ_BASE 0xae08
 574
 575 struct gpe_regs {
 576     uint16_t sts; /* status */
 577     uint16_t en;  /* enabled */
 578     uint8_t cpus_sts[32];
 579 };
 580
 581 struct pci_status {
 582     uint32_t up;
 583     uint32_t down;
 584 };
 585
 586 static struct gpe_regs gpe;
 587 static struct pci_status pci0_status;
 588
 589 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 590 {
 591     if (addr & 1)
 592         return (val >> 8) & 0xff;
 593     return val & 0xff;
 594 }
 595
 596 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 597 {
 598     uint32_t val = 0;
 599     struct gpe_regs *g = opaque;
 600     switch (addr) {
 601         case PROC_BASE ... PROC_BASE+31:
 602             val = g->cpus_sts[addr - PROC_BASE];
 603             break;
 604
 605         case GPE_BASE:
 606         case GPE_BASE + 1:
 607             val = gpe_read_val(g->sts, addr);
 608             break;
 609         case GPE_BASE + 2:
 610         case GPE_BASE + 3:
 611             val = gpe_read_val(g->en, addr);
 612             break;
 613         default:
 614             break;
 615     }
 616
 617 #if defined(DEBUG)
 618     printf("gpe read %x == %x\n", addr, val);
 619 #endif
 620     return val;
 621 }
 622
 623 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 624 {
 625     if (addr & 1)
 626         *cur = (*cur & 0xff) | (val << 8);
 627     else
 628         *cur = (*cur & 0xff00) | (val & 0xff);
 629 }
 630
 631 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 632 {
 633     uint16_t x1, x0 = val & 0xff;
 634     int shift = (addr & 1) ? 8 : 0;
 635
 636     x1 = (*cur >> shift) & 0xff;
 637
 638     x1 = x1 & ~x0;
 639
 640     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 641 }
 642
 643 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 644 {
 645     struct gpe_regs *g = opaque;
 646     switch (addr) {
 647         case PROC_BASE ... PROC_BASE + 31:
 648             /* don't allow to change cpus_sts from inside a guest */
 649             break;
 650
 651         case GPE_BASE:
 652         case GPE_BASE + 1:
 653             gpe_reset_val(&g->sts, addr, val);
 654             break;
 655         case GPE_BASE + 2:
 656         case GPE_BASE + 3:
 657             gpe_write_val(&g->en, addr, val);
 658             break;
 659         default:
 660             break;
 661    }
 662
 663 #if defined(DEBUG)
 664     printf("gpe write %x <== %d\n", addr, val);
 665 #endif
 666 }
 667
 668 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 669 {
 670     uint32_t val = 0;
 671     struct pci_status *g = opaque;
 672     switch (addr) {
 673         case PCI_BASE:
 674             val = g->up;
 675             break;
 676         case PCI_BASE + 4:
 677             val = g->down;
 678             break;
 679         default:
 680             break;
 681     }
 682
 683 #if defined(DEBUG)
 684     printf("pcihotplug read %x == %x\n", addr, val);
 685 #endif
 686     return val;
 687 }
 688
 689 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 690 {
 691     struct pci_status *g = opaque;
 692     switch (addr) {
 693         case PCI_BASE:
 694             g->up = val;
 695             break;
 696         case PCI_BASE + 4:
 697             g->down = val;
 698             break;
 699    }
 700
 701 #if defined(DEBUG)
 702     printf("pcihotplug write %x <== %d\n", addr, val);
 703 #endif
 704 }
 705
 706 static uint32_t pciej_read(void *opaque, uint32_t addr)
 707 {
 708 #if defined(DEBUG)
 709     printf("pciej read %x\n", addr);
 710 #endif
 711     return 0;
 712 }
 713
 714 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 715 {
 716     BusState *bus = opaque;
 717     DeviceState *qdev, *next;
 718     PCIDevice *dev;
 719     int slot = ffs(val) - 1;
 720
 721     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 722         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 723         if (PCI_SLOT(dev->devfn) == slot) {
 724             qdev_free(qdev);
 725         }
 726     }
 727
 728
 729 #if defined(DEBUG)
 730     printf("pciej write %x <== %d\n", addr, val);
 731 #endif
 732 }
 733
 734 static const char *model;
 735
 736 static int piix4_device_hotplug(PCIDevice *dev, int state);
 737
 738 void piix4_acpi_system_hot_add_init(PCIBus *bus, const char *cpu_model)
 739 {
 740     int i = 0, cpus = smp_cpus;
 741
 742     while (cpus > 0) {
 743         gpe.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 744         cpus -= 8;
 745     }
 746     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 747     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 748
 749     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, &gpe);
 750     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, &gpe);
 751
 752     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 753     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 754
 755     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 756     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 757
 758     model = cpu_model;
 759
 760     pci_bus_hotplug(bus, piix4_device_hotplug);
 761 }
 762
 763 #if defined(TARGET_I386)
 764 static void enable_processor(struct gpe_regs *g, int cpu)
 765 {
 766     g->sts |= 4;
 767     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 768 }
 769
 770 static void disable_processor(struct gpe_regs *g, int cpu)
 771 {
 772     g->sts |= 4;
 773     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 774 }
 775
 776 void qemu_system_cpu_hot_add(int cpu, int state)
 777 {
 778     CPUState *env;
 779
 780     if (state && !qemu_get_cpu(cpu)) {
 781         env = pc_new_cpu(model);
 782         if (!env) {
 783             fprintf(stderr, "cpu %d creation failed\n", cpu);
 784             return;
 785         }
 786         env->cpuid_apic_id = cpu;
 787     }
 788
 789     if (state)
 790         enable_processor(&gpe, cpu);
 791     else
 792         disable_processor(&gpe, cpu);
 793     if (gpe.en & 4) {
 794         qemu_set_irq(pm_state->irq, 1);
 795         qemu_set_irq(pm_state->irq, 0);
 796     }
 797 }
 798 #endif
 799
 800 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 801 {
 802     g->sts |= 2;
 803     p->up |= (1 << slot);
 804 }
 805
 806 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 807 {
 808     g->sts |= 2;
 809     p->down |= (1 << slot);
 810 }
 811
 812 static int piix4_device_hotplug(PCIDevice *dev, int state)
 813 {
 814     int slot = PCI_SLOT(dev->devfn);
 815
 816     pci0_status.up = 0;
 817     pci0_status.down = 0;
 818     if (state)
 819         enable_device(&pci0_status, &gpe, slot);
 820     else
 821         disable_device(&pci0_status, &gpe, slot);
 822     if (gpe.en & 2) {
 823         qemu_set_irq(pm_state->irq, 1);
 824         qemu_set_irq(pm_state->irq, 0);
 825     }
 826     return 0;
 827 }
 828
 829 struct acpi_table_header
 830 {
 831     char signature [4];    /* ACPI signature (4 ASCII characters) */
 832     uint32_t length;          /* Length of table, in bytes, including header */
 833     uint8_t revision;         /* ACPI Specification minor version # */
 834     uint8_t checksum;         /* To make sum of entire table == 0 */
 835     char oem_id [6];       /* OEM identification */
 836     char oem_table_id [8]; /* OEM table identification */
 837     uint32_t oem_revision;    /* OEM revision number */
 838     char asl_compiler_id [4]; /* ASL compiler vendor ID */
 839     uint32_t asl_compiler_revision; /* ASL compiler revision number */
 840 } __attribute__((packed));
 841
 842 char *acpi_tables;
 843 size_t acpi_tables_len;
 844
 845 static int acpi_checksum(const uint8_t *data, int len)
 846 {
 847     int sum, i;
 848     sum = 0;
 849     for(i = 0; i < len; i++)
 850         sum += data[i];
 851     return (-sum) & 0xff;
 852 }
 853
 854 int acpi_table_add(const char *t)
 855 {
 856     static const char *dfl_id = "QEMUQEMU";
 857     char buf[1024], *p, *f;
 858     struct acpi_table_header acpi_hdr;
 859     unsigned long val;
 860     size_t off;
 861
 862     memset(&acpi_hdr, 0, sizeof(acpi_hdr));
 863
 864     if (get_param_value(buf, sizeof(buf), "sig", t)) {
 865         strncpy(acpi_hdr.signature, buf, 4);
 866     } else {
 867         strncpy(acpi_hdr.signature, dfl_id, 4);
 868     }
 869     if (get_param_value(buf, sizeof(buf), "rev", t)) {
 870         val = strtoul(buf, &p, 10);
 871         if (val > 255 || *p != '\0')
 872             goto out;
 873     } else {
 874         val = 1;
 875     }
 876     acpi_hdr.revision = (int8_t)val;
 877
 878     if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
 879         strncpy(acpi_hdr.oem_id, buf, 6);
 880     } else {
 881         strncpy(acpi_hdr.oem_id, dfl_id, 6);
 882     }
 883
 884     if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
 885         strncpy(acpi_hdr.oem_table_id, buf, 8);
 886     } else {
 887         strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
 888     }
 889
 890     if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
 891         val = strtol(buf, &p, 10);
 892         if(*p != '\0')
 893             goto out;
 894     } else {
 895         val = 1;
 896     }
 897     acpi_hdr.oem_revision = cpu_to_le32(val);
 898
 899     if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
 900         strncpy(acpi_hdr.asl_compiler_id, buf, 4);
 901     } else {
 902         strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
 903     }
 904
 905     if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
 906         val = strtol(buf, &p, 10);
 907         if(*p != '\0')
 908             goto out;
 909     } else {
 910         val = 1;
 911     }
 912     acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
 913
 914     if (!get_param_value(buf, sizeof(buf), "data", t)) {
 915          buf[0] = '\0';
 916     }
 917
 918     acpi_hdr.length = sizeof(acpi_hdr);
 919
 920     f = buf;
 921     while (buf[0]) {
 922         struct stat s;
 923         char *n = strchr(f, ':');
 924         if (n)
 925             *n = '\0';
 926         if(stat(f, &s) < 0) {
 927             fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
 928             goto out;
 929         }
 930         acpi_hdr.length += s.st_size;
 931         if (!n)
 932             break;
 933         *n = ':';
 934         f = n + 1;
 935     }
 936
 937     if (!acpi_tables) {
 938         acpi_tables_len = sizeof(uint16_t);
 939         acpi_tables = qemu_mallocz(acpi_tables_len);
 940     }
 941     p = acpi_tables + acpi_tables_len;
 942     acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
 943     acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
 944
 945     acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
 946     *(uint16_t*)p = acpi_hdr.length;
 947     p += sizeof(uint16_t);
 948     memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
 949     off = sizeof(acpi_hdr);
 950
 951     f = buf;
 952     while (buf[0]) {
 953         struct stat s;
 954         int fd;
 955         char *n = strchr(f, ':');
 956         if (n)
 957             *n = '\0';
 958         fd = open(f, O_RDONLY);
 959
 960         if(fd < 0)
 961             goto out;
 962         if(fstat(fd, &s) < 0) {
 963             close(fd);
 964             goto out;
 965         }
 966
 967         do {
 968             int r;
 969             r = read(fd, p + off, s.st_size);
 970             if (r > 0) {
 971                 off += r;
 972                 s.st_size -= r;
 973             } else if ((r < 0 && errno != EINTR) || r == 0) {
 974                 close(fd);
 975                 goto out;
 976             }
 977         } while(s.st_size);
 978
 979         close(fd);
 980         if (!n)
 981             break;
 982         f = n + 1;
 983     }
 984
 985     ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
 986     /* increase number of tables */
 987     (*(uint16_t*)acpi_tables) =
 988             cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
 989     return 0;
 990 out:
 991     if (acpi_tables) {
 992         qemu_free(acpi_tables);
 993         acpi_tables = NULL;
 994     }
 995     return -1;
 996 }