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qemu-kvm: Remove eventfd compat header
[qemu/qemu-dev-zwu.git] / hw / usb-ehci.c
blobe33e546b432c6beafdd6bacc2bf945d2185b760f
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28 #include "hw.h"
29 #include "qemu-timer.h"
30 #include "usb.h"
31 #include "pci.h"
32 #include "monitor.h"
33 #include "trace.h"
34
35 #define EHCI_DEBUG 0
36
37 #if EHCI_DEBUG
38 #define DPRINTF printf
39 #else
40 #define DPRINTF(...)
41 #endif
42
43 /* internal processing - reset HC to try and recover */
44 #define USB_RET_PROCERR (-99)
45
46 #define MMIO_SIZE 0x1000
47
48 /* Capability Registers Base Address - section 2.2 */
49 #define CAPREGBASE 0x0000
50 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54 #define EECP HCCPARAMS + 1
55 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
57
58 #define OPREGBASE 0x0020 // Operational Registers Base Address
59
60 #define USBCMD OPREGBASE + 0x0000
61 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
62 #define USBCMD_HCRESET (1 << 1) // HC Reset
63 #define USBCMD_FLS (3 << 2) // Frame List Size
64 #define USBCMD_FLS_SH 2 // Frame List Size Shift
65 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
73
74 #define USBSTS OPREGBASE + 0x0004
75 #define USBSTS_RO_MASK 0x0000003f
76 #define USBSTS_INT (1 << 0) // USB Interrupt
77 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
78 #define USBSTS_PCD (1 << 2) // Port Change Detect
79 #define USBSTS_FLR (1 << 3) // Frame List Rollover
80 #define USBSTS_HSE (1 << 4) // Host System Error
81 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82 #define USBSTS_HALT (1 << 12) // HC Halted
83 #define USBSTS_REC (1 << 13) // Reclamation
84 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86
87 /*
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
90 */
91 #define USBINTR OPREGBASE + 0x0008
92 #define USBINTR_MASK 0x0000003f
93
94 #define FRINDEX OPREGBASE + 0x000c
95 #define CTRLDSSEGMENT OPREGBASE + 0x0010
96 #define PERIODICLISTBASE OPREGBASE + 0x0014
97 #define ASYNCLISTADDR OPREGBASE + 0x0018
98 #define ASYNCLISTADDR_MASK 0xffffffe0
99
100 #define CONFIGFLAG OPREGBASE + 0x0040
101
102 #define PORTSC (OPREGBASE + 0x0044)
103 #define PORTSC_BEGIN PORTSC
104 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
105 /*
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
108 */
109 #define PORTSC_RO_MASK 0x007021c5
110 #define PORTSC_RWC_MASK 0x0000002a
111 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114 #define PORTSC_PTC (15 << 16) // Port Test Control
115 #define PORTSC_PTC_SH 16 // Port Test Control shift
116 #define PORTSC_PIC (3 << 14) // Port Indicator Control
117 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118 #define PORTSC_POWNER (1 << 13) // Port Owner
119 #define PORTSC_PPOWER (1 << 12) // Port Power
120 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
121 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122 #define PORTSC_PRESET (1 << 8) // Port Reset
123 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
124 #define PORTSC_FPRES (1 << 6) // Force Port Resume
125 #define PORTSC_OCC (1 << 5) // Over Current Change
126 #define PORTSC_OCA (1 << 4) // Over Current Active
127 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128 #define PORTSC_PED (1 << 2) // Port Enable/Disable
129 #define PORTSC_CSC (1 << 1) // Connect Status Change
130 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
131
132 #define FRAME_TIMER_FREQ 1000
133 #define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
134
135 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136 #define NB_PORTS 4 // Number of downstream ports
137 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139 #define MAX_QH 100 // Max allowable queue heads in a chain
140
141 /* Internal periodic / asynchronous schedule state machine states
142 */
143 typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
149 */
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159 } EHCI_STATES;
160
161 /* macros for accessing fields within next link pointer entry */
162 #define NLPTR_GET(x) ((x) & 0xffffffe0)
163 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
165
166 /* link pointer types */
167 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168 #define NLPTR_TYPE_QH 1 // queue head
169 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
171
172
173 /* EHCI spec version 1.0 Section 3.3
174 */
175 typedef struct EHCIitd {
176 uint32_t next;
177
178 uint32_t transact[8];
179 #define ITD_XACT_ACTIVE (1 << 31)
180 #define ITD_XACT_DBERROR (1 << 30)
181 #define ITD_XACT_BABBLE (1 << 29)
182 #define ITD_XACT_XACTERR (1 << 28)
183 #define ITD_XACT_LENGTH_MASK 0x0fff0000
184 #define ITD_XACT_LENGTH_SH 16
185 #define ITD_XACT_IOC (1 << 15)
186 #define ITD_XACT_PGSEL_MASK 0x00007000
187 #define ITD_XACT_PGSEL_SH 12
188 #define ITD_XACT_OFFSET_MASK 0x00000fff
189
190 uint32_t bufptr[7];
191 #define ITD_BUFPTR_MASK 0xfffff000
192 #define ITD_BUFPTR_SH 12
193 #define ITD_BUFPTR_EP_MASK 0x00000f00
194 #define ITD_BUFPTR_EP_SH 8
195 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196 #define ITD_BUFPTR_DEVADDR_SH 0
197 #define ITD_BUFPTR_DIRECTION (1 << 11)
198 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199 #define ITD_BUFPTR_MAXPKT_SH 0
200 #define ITD_BUFPTR_MULT_MASK 0x00000003
201 #define ITD_BUFPTR_MULT_SH 0
202 } EHCIitd;
203
204 /* EHCI spec version 1.0 Section 3.4
205 */
206 typedef struct EHCIsitd {
207 uint32_t next; // Standard next link pointer
208 uint32_t epchar;
209 #define SITD_EPCHAR_IO (1 << 31)
210 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
211 #define SITD_EPCHAR_PORTNUM_SH 24
212 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
213 #define SITD_EPCHAR_HUBADDR_SH 16
214 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
215 #define SITD_EPCHAR_EPNUM_SH 8
216 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
217
218 uint32_t uframe;
219 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
220 #define SITD_UFRAME_CMASK_SH 8
221 #define SITD_UFRAME_SMASK_MASK 0x000000ff
222
223 uint32_t results;
224 #define SITD_RESULTS_IOC (1 << 31)
225 #define SITD_RESULTS_PGSEL (1 << 30)
226 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
227 #define SITD_RESULTS_TYBYTES_SH 16
228 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
229 #define SITD_RESULTS_CPROGMASK_SH 8
230 #define SITD_RESULTS_ACTIVE (1 << 7)
231 #define SITD_RESULTS_ERR (1 << 6)
232 #define SITD_RESULTS_DBERR (1 << 5)
233 #define SITD_RESULTS_BABBLE (1 << 4)
234 #define SITD_RESULTS_XACTERR (1 << 3)
235 #define SITD_RESULTS_MISSEDUF (1 << 2)
236 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
237
238 uint32_t bufptr[2];
239 #define SITD_BUFPTR_MASK 0xfffff000
240 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
241 #define SITD_BUFPTR_TPOS_MASK 0x00000018
242 #define SITD_BUFPTR_TPOS_SH 3
243 #define SITD_BUFPTR_TCNT_MASK 0x00000007
244
245 uint32_t backptr; // Standard next link pointer
246 } EHCIsitd;
247
248 /* EHCI spec version 1.0 Section 3.5
249 */
250 typedef struct EHCIqtd {
251 uint32_t next; // Standard next link pointer
252 uint32_t altnext; // Standard next link pointer
253 uint32_t token;
254 #define QTD_TOKEN_DTOGGLE (1 << 31)
255 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
256 #define QTD_TOKEN_TBYTES_SH 16
257 #define QTD_TOKEN_IOC (1 << 15)
258 #define QTD_TOKEN_CPAGE_MASK 0x00007000
259 #define QTD_TOKEN_CPAGE_SH 12
260 #define QTD_TOKEN_CERR_MASK 0x00000c00
261 #define QTD_TOKEN_CERR_SH 10
262 #define QTD_TOKEN_PID_MASK 0x00000300
263 #define QTD_TOKEN_PID_SH 8
264 #define QTD_TOKEN_ACTIVE (1 << 7)
265 #define QTD_TOKEN_HALT (1 << 6)
266 #define QTD_TOKEN_DBERR (1 << 5)
267 #define QTD_TOKEN_BABBLE (1 << 4)
268 #define QTD_TOKEN_XACTERR (1 << 3)
269 #define QTD_TOKEN_MISSEDUF (1 << 2)
270 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
271 #define QTD_TOKEN_PING (1 << 0)
272
273 uint32_t bufptr[5]; // Standard buffer pointer
274 #define QTD_BUFPTR_MASK 0xfffff000
275 } EHCIqtd;
276
277 /* EHCI spec version 1.0 Section 3.6
278 */
279 typedef struct EHCIqh {
280 uint32_t next; // Standard next link pointer
281
282 /* endpoint characteristics */
283 uint32_t epchar;
284 #define QH_EPCHAR_RL_MASK 0xf0000000
285 #define QH_EPCHAR_RL_SH 28
286 #define QH_EPCHAR_C (1 << 27)
287 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
288 #define QH_EPCHAR_MPLEN_SH 16
289 #define QH_EPCHAR_H (1 << 15)
290 #define QH_EPCHAR_DTC (1 << 14)
291 #define QH_EPCHAR_EPS_MASK 0x00003000
292 #define QH_EPCHAR_EPS_SH 12
293 #define EHCI_QH_EPS_FULL 0
294 #define EHCI_QH_EPS_LOW 1
295 #define EHCI_QH_EPS_HIGH 2
296 #define EHCI_QH_EPS_RESERVED 3
297
298 #define QH_EPCHAR_EP_MASK 0x00000f00
299 #define QH_EPCHAR_EP_SH 8
300 #define QH_EPCHAR_I (1 << 7)
301 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
302 #define QH_EPCHAR_DEVADDR_SH 0
303
304 /* endpoint capabilities */
305 uint32_t epcap;
306 #define QH_EPCAP_MULT_MASK 0xc0000000
307 #define QH_EPCAP_MULT_SH 30
308 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
309 #define QH_EPCAP_PORTNUM_SH 23
310 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
311 #define QH_EPCAP_HUBADDR_SH 16
312 #define QH_EPCAP_CMASK_MASK 0x0000ff00
313 #define QH_EPCAP_CMASK_SH 8
314 #define QH_EPCAP_SMASK_MASK 0x000000ff
315 #define QH_EPCAP_SMASK_SH 0
316
317 uint32_t current_qtd; // Standard next link pointer
318 uint32_t next_qtd; // Standard next link pointer
319 uint32_t altnext_qtd;
320 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
321 #define QH_ALTNEXT_NAKCNT_SH 1
322
323 uint32_t token; // Same as QTD token
324 uint32_t bufptr[5]; // Standard buffer pointer
325 #define BUFPTR_CPROGMASK_MASK 0x000000ff
326 #define BUFPTR_FRAMETAG_MASK 0x0000001f
327 #define BUFPTR_SBYTES_MASK 0x00000fe0
328 #define BUFPTR_SBYTES_SH 5
329 } EHCIqh;
330
331 /* EHCI spec version 1.0 Section 3.7
332 */
333 typedef struct EHCIfstn {
334 uint32_t next; // Standard next link pointer
335 uint32_t backptr; // Standard next link pointer
336 } EHCIfstn;
337
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIQueue {
348 EHCIState *ehci;
349 QTAILQ_ENTRY(EHCIQueue) next;
350 bool async_schedule;
351 uint32_t seen, ts;
352
353 /* cached data from guest - needs to be flushed
354 * when guest removes an entry (doorbell, handshake sequence)
355 */
356 EHCIqh qh; // copy of current QH (being worked on)
357 uint32_t qhaddr; // address QH read from
358 EHCIqtd qtd; // copy of current QTD (being worked on)
359 uint32_t qtdaddr; // address QTD read from
360
361 USBPacket packet;
362 uint8_t buffer[BUFF_SIZE];
363 int pid;
364 uint32_t tbytes;
365 enum async_state async;
366 int usb_status;
367 };
368
369 struct EHCIState {
370 PCIDevice dev;
371 USBBus bus;
372 qemu_irq irq;
373 target_phys_addr_t mem_base;
374 int mem;
375 int num_ports;
376 /*
377 * EHCI spec version 1.0 Section 2.3
378 * Host Controller Operational Registers
379 */
380 union {
381 uint8_t mmio[MMIO_SIZE];
382 struct {
383 uint8_t cap[OPREGBASE];
384 uint32_t usbcmd;
385 uint32_t usbsts;
386 uint32_t usbintr;
387 uint32_t frindex;
388 uint32_t ctrldssegment;
389 uint32_t periodiclistbase;
390 uint32_t asynclistaddr;
391 uint32_t notused[9];
392 uint32_t configflag;
393 uint32_t portsc[NB_PORTS];
394 };
395 };
396
397 /*
398 * Internal states, shadow registers, etc
399 */
400 uint32_t sofv;
401 QEMUTimer *frame_timer;
402 int attach_poll_counter;
403 int astate; // Current state in asynchronous schedule
404 int pstate; // Current state in periodic schedule
405 USBPort ports[NB_PORTS];
406 uint32_t usbsts_pending;
407 QTAILQ_HEAD(, EHCIQueue) queues;
408
409 uint32_t a_fetch_addr; // which address to look at next
410 uint32_t p_fetch_addr; // which address to look at next
411
412 USBPacket ipacket;
413 uint8_t ibuffer[BUFF_SIZE];
414 int isoch_pause;
415
416 uint32_t last_run_usec;
417 uint32_t frame_end_usec;
418 };
419
420 #define SET_LAST_RUN_CLOCK(s) \
421 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
422
423 /* nifty macros from Arnon's EHCI version */
424 #define get_field(data, field) \
425 (((data) & field##_MASK) >> field##_SH)
426
427 #define set_field(data, newval, field) do { \
428 uint32_t val = *data; \
429 val &= ~ field##_MASK; \
430 val |= ((newval) << field##_SH) & field##_MASK; \
431 *data = val; \
432 } while(0)
433
434 static const char *ehci_state_names[] = {
435 [ EST_INACTIVE ] = "INACTIVE",
436 [ EST_ACTIVE ] = "ACTIVE",
437 [ EST_EXECUTING ] = "EXECUTING",
438 [ EST_SLEEPING ] = "SLEEPING",
439 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
440 [ EST_FETCHENTRY ] = "FETCH ENTRY",
441 [ EST_FETCHQH ] = "FETCH QH",
442 [ EST_FETCHITD ] = "FETCH ITD",
443 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
444 [ EST_FETCHQTD ] = "FETCH QTD",
445 [ EST_EXECUTE ] = "EXECUTE",
446 [ EST_WRITEBACK ] = "WRITEBACK",
447 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
448 };
449
450 static const char *ehci_mmio_names[] = {
451 [ CAPLENGTH ] = "CAPLENGTH",
452 [ HCIVERSION ] = "HCIVERSION",
453 [ HCSPARAMS ] = "HCSPARAMS",
454 [ HCCPARAMS ] = "HCCPARAMS",
455 [ USBCMD ] = "USBCMD",
456 [ USBSTS ] = "USBSTS",
457 [ USBINTR ] = "USBINTR",
458 [ FRINDEX ] = "FRINDEX",
459 [ PERIODICLISTBASE ] = "P-LIST BASE",
460 [ ASYNCLISTADDR ] = "A-LIST ADDR",
461 [ PORTSC_BEGIN ] = "PORTSC #0",
462 [ PORTSC_BEGIN + 4] = "PORTSC #1",
463 [ PORTSC_BEGIN + 8] = "PORTSC #2",
464 [ PORTSC_BEGIN + 12] = "PORTSC #3",
465 [ CONFIGFLAG ] = "CONFIGFLAG",
466 };
467
468 static const char *nr2str(const char **n, size_t len, uint32_t nr)
469 {
470 if (nr < len && n[nr] != NULL) {
471 return n[nr];
472 } else {
473 return "unknown";
474 }
475 }
476
477 static const char *state2str(uint32_t state)
478 {
479 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
480 }
481
482 static const char *addr2str(target_phys_addr_t addr)
483 {
484 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
485 }
486
487 static void ehci_trace_usbsts(uint32_t mask, int state)
488 {
489 /* interrupts */
490 if (mask & USBSTS_INT) {
491 trace_usb_ehci_usbsts("INT", state);
492 }
493 if (mask & USBSTS_ERRINT) {
494 trace_usb_ehci_usbsts("ERRINT", state);
495 }
496 if (mask & USBSTS_PCD) {
497 trace_usb_ehci_usbsts("PCD", state);
498 }
499 if (mask & USBSTS_FLR) {
500 trace_usb_ehci_usbsts("FLR", state);
501 }
502 if (mask & USBSTS_HSE) {
503 trace_usb_ehci_usbsts("HSE", state);
504 }
505 if (mask & USBSTS_IAA) {
506 trace_usb_ehci_usbsts("IAA", state);
507 }
508
509 /* status */
510 if (mask & USBSTS_HALT) {
511 trace_usb_ehci_usbsts("HALT", state);
512 }
513 if (mask & USBSTS_REC) {
514 trace_usb_ehci_usbsts("REC", state);
515 }
516 if (mask & USBSTS_PSS) {
517 trace_usb_ehci_usbsts("PSS", state);
518 }
519 if (mask & USBSTS_ASS) {
520 trace_usb_ehci_usbsts("ASS", state);
521 }
522 }
523
524 static inline void ehci_set_usbsts(EHCIState *s, int mask)
525 {
526 if ((s->usbsts & mask) == mask) {
527 return;
528 }
529 ehci_trace_usbsts(mask, 1);
530 s->usbsts |= mask;
531 }
532
533 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
534 {
535 if ((s->usbsts & mask) == 0) {
536 return;
537 }
538 ehci_trace_usbsts(mask, 0);
539 s->usbsts &= ~mask;
540 }
541
542 static inline void ehci_set_interrupt(EHCIState *s, int intr)
543 {
544 int level = 0;
545
546 // TODO honour interrupt threshold requests
547
548 ehci_set_usbsts(s, intr);
549
550 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
551 level = 1;
552 }
553
554 qemu_set_irq(s->irq, level);
555 }
556
557 static inline void ehci_record_interrupt(EHCIState *s, int intr)
558 {
559 s->usbsts_pending |= intr;
560 }
561
562 static inline void ehci_commit_interrupt(EHCIState *s)
563 {
564 if (!s->usbsts_pending) {
565 return;
566 }
567 ehci_set_interrupt(s, s->usbsts_pending);
568 s->usbsts_pending = 0;
569 }
570
571 static void ehci_set_state(EHCIState *s, int async, int state)
572 {
573 if (async) {
574 trace_usb_ehci_state("async", state2str(state));
575 s->astate = state;
576 } else {
577 trace_usb_ehci_state("periodic", state2str(state));
578 s->pstate = state;
579 }
580 }
581
582 static int ehci_get_state(EHCIState *s, int async)
583 {
584 return async ? s->astate : s->pstate;
585 }
586
587 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
588 {
589 if (async) {
590 s->a_fetch_addr = addr;
591 } else {
592 s->p_fetch_addr = addr;
593 }
594 }
595
596 static int ehci_get_fetch_addr(EHCIState *s, int async)
597 {
598 return async ? s->a_fetch_addr : s->p_fetch_addr;
599 }
600
601 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
602 {
603 /* need three here due to argument count limits */
604 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
605 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
606 trace_usb_ehci_qh_fields(addr,
607 get_field(qh->epchar, QH_EPCHAR_RL),
608 get_field(qh->epchar, QH_EPCHAR_MPLEN),
609 get_field(qh->epchar, QH_EPCHAR_EPS),
610 get_field(qh->epchar, QH_EPCHAR_EP),
611 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
612 trace_usb_ehci_qh_bits(addr,
613 (bool)(qh->epchar & QH_EPCHAR_C),
614 (bool)(qh->epchar & QH_EPCHAR_H),
615 (bool)(qh->epchar & QH_EPCHAR_DTC),
616 (bool)(qh->epchar & QH_EPCHAR_I));
617 }
618
619 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
620 {
621 /* need three here due to argument count limits */
622 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
623 trace_usb_ehci_qtd_fields(addr,
624 get_field(qtd->token, QTD_TOKEN_TBYTES),
625 get_field(qtd->token, QTD_TOKEN_CPAGE),
626 get_field(qtd->token, QTD_TOKEN_CERR),
627 get_field(qtd->token, QTD_TOKEN_PID));
628 trace_usb_ehci_qtd_bits(addr,
629 (bool)(qtd->token & QTD_TOKEN_IOC),
630 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
631 (bool)(qtd->token & QTD_TOKEN_HALT),
632 (bool)(qtd->token & QTD_TOKEN_BABBLE),
633 (bool)(qtd->token & QTD_TOKEN_XACTERR));
634 }
635
636 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
637 {
638 trace_usb_ehci_itd(addr, itd->next,
639 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
640 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
641 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
642 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
643 }
644
645 /* queue management */
646
647 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
648 {
649 EHCIQueue *q;
650
651 q = qemu_mallocz(sizeof(*q));
652 q->ehci = ehci;
653 q->async_schedule = async;
654 QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
655 trace_usb_ehci_queue_action(q, "alloc");
656 return q;
657 }
658
659 static void ehci_free_queue(EHCIQueue *q)
660 {
661 trace_usb_ehci_queue_action(q, "free");
662 if (q->async == EHCI_ASYNC_INFLIGHT) {
663 usb_cancel_packet(&q->packet);
664 }
665 QTAILQ_REMOVE(&q->ehci->queues, q, next);
666 qemu_free(q);
667 }
668
669 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
670 {
671 EHCIQueue *q;
672
673 QTAILQ_FOREACH(q, &ehci->queues, next) {
674 if (addr == q->qhaddr) {
675 return q;
676 }
677 }
678 return NULL;
679 }
680
681 static void ehci_queues_rip_unused(EHCIState *ehci)
682 {
683 EHCIQueue *q, *tmp;
684
685 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
686 if (q->seen) {
687 q->seen = 0;
688 q->ts = ehci->last_run_usec;
689 continue;
690 }
691 if (ehci->last_run_usec < q->ts + 250000) {
692 /* allow 0.25 sec idle */
693 continue;
694 }
695 ehci_free_queue(q);
696 }
697 }
698
699 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev)
700 {
701 EHCIQueue *q, *tmp;
702
703 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
704 if (q->packet.owner != dev) {
705 continue;
706 }
707 ehci_free_queue(q);
708 }
709 }
710
711 static void ehci_queues_rip_all(EHCIState *ehci)
712 {
713 EHCIQueue *q, *tmp;
714
715 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
716 ehci_free_queue(q);
717 }
718 }
719
720 /* Attach or detach a device on root hub */
721
722 static void ehci_attach(USBPort *port)
723 {
724 EHCIState *s = port->opaque;
725 uint32_t *portsc = &s->portsc[port->index];
726
727 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
728
729 *portsc |= PORTSC_CONNECT;
730 *portsc |= PORTSC_CSC;
731
732 /*
733 * If a high speed device is attached then we own this port(indicated
734 * by zero in the PORTSC_POWNER bit field) so set the status bit
735 * and set an interrupt if enabled.
736 */
737 if ( !(*portsc & PORTSC_POWNER)) {
738 ehci_set_interrupt(s, USBSTS_PCD);
739 }
740 }
741
742 static void ehci_detach(USBPort *port)
743 {
744 EHCIState *s = port->opaque;
745 uint32_t *portsc = &s->portsc[port->index];
746
747 trace_usb_ehci_port_detach(port->index);
748
749 *portsc &= ~PORTSC_CONNECT;
750 *portsc |= PORTSC_CSC;
751
752 /*
753 * If a high speed device is attached then we own this port(indicated
754 * by zero in the PORTSC_POWNER bit field) so set the status bit
755 * and set an interrupt if enabled.
756 */
757 if ( !(*portsc & PORTSC_POWNER)) {
758 ehci_set_interrupt(s, USBSTS_PCD);
759 }
760 }
761
762 /* 4.1 host controller initialization */
763 static void ehci_reset(void *opaque)
764 {
765 EHCIState *s = opaque;
766 int i;
767
768 trace_usb_ehci_reset();
769
770 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
771
772 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
773 s->usbsts = USBSTS_HALT;
774
775 s->astate = EST_INACTIVE;
776 s->pstate = EST_INACTIVE;
777 s->isoch_pause = -1;
778 s->attach_poll_counter = 0;
779
780 for(i = 0; i < NB_PORTS; i++) {
781 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
782
783 if (s->ports[i].dev) {
784 usb_attach(&s->ports[i], s->ports[i].dev);
785 }
786 }
787 ehci_queues_rip_all(s);
788 }
789
790 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
791 {
792 EHCIState *s = ptr;
793 uint32_t val;
794
795 val = s->mmio[addr];
796
797 return val;
798 }
799
800 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
801 {
802 EHCIState *s = ptr;
803 uint32_t val;
804
805 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
806
807 return val;
808 }
809
810 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
811 {
812 EHCIState *s = ptr;
813 uint32_t val;
814
815 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
816 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
817
818 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
819 return val;
820 }
821
822 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
823 {
824 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
825 exit(1);
826 }
827
828 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
829 {
830 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
831 exit(1);
832 }
833
834 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
835 {
836 uint32_t *portsc = &s->portsc[port];
837 int rwc;
838 USBDevice *dev = s->ports[port].dev;
839
840 rwc = val & PORTSC_RWC_MASK;
841 val &= PORTSC_RO_MASK;
842
843 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
844
845 *portsc &= ~rwc;
846
847 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
848 trace_usb_ehci_port_reset(port, 1);
849 }
850
851 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
852 trace_usb_ehci_port_reset(port, 0);
853 usb_attach(&s->ports[port], dev);
854
855 // TODO how to handle reset of ports with no device
856 if (dev) {
857 usb_send_msg(dev, USB_MSG_RESET);
858 }
859
860 if (s->ports[port].dev) {
861 *portsc &= ~PORTSC_CSC;
862 }
863
864 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
865 * to SW that this port has a high speed device attached
866 *
867 * TODO - when to disable?
868 */
869 val |= PORTSC_PED;
870 val |= PORTSC_PEDC;
871 }
872
873 *portsc &= ~PORTSC_RO_MASK;
874 *portsc |= val;
875 }
876
877 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
878 {
879 EHCIState *s = ptr;
880 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
881 uint32_t old = *mmio;
882 int i;
883
884 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
885
886 /* Only aligned reads are allowed on OHCI */
887 if (addr & 3) {
888 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
889 TARGET_FMT_plx "\n", addr);
890 return;
891 }
892
893 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
894 handle_port_status_write(s, (addr-PORTSC)/4, val);
895 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
896 return;
897 }
898
899 if (addr < OPREGBASE) {
900 fprintf(stderr, "usb-ehci: write attempt to read-only register"
901 TARGET_FMT_plx "\n", addr);
902 return;
903 }
904
905
906 /* Do any register specific pre-write processing here. */
907 switch(addr) {
908 case USBCMD:
909 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
910 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
911 SET_LAST_RUN_CLOCK(s);
912 ehci_clear_usbsts(s, USBSTS_HALT);
913 }
914
915 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
916 qemu_del_timer(s->frame_timer);
917 // TODO - should finish out some stuff before setting halt
918 ehci_set_usbsts(s, USBSTS_HALT);
919 }
920
921 if (val & USBCMD_HCRESET) {
922 ehci_reset(s);
923 val &= ~USBCMD_HCRESET;
924 }
925
926 /* not supporting dynamic frame list size at the moment */
927 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
928 fprintf(stderr, "attempt to set frame list size -- value %d\n",
929 val & USBCMD_FLS);
930 val &= ~USBCMD_FLS;
931 }
932 break;
933
934 case USBSTS:
935 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
936 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
937 val = s->usbsts;
938 ehci_set_interrupt(s, 0);
939 break;
940
941 case USBINTR:
942 val &= USBINTR_MASK;
943 break;
944
945 case FRINDEX:
946 s->sofv = val >> 3;
947 break;
948
949 case CONFIGFLAG:
950 val &= 0x1;
951 if (val) {
952 for(i = 0; i < NB_PORTS; i++)
953 s->portsc[i] &= ~PORTSC_POWNER;
954 }
955 break;
956
957 case PERIODICLISTBASE:
958 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
959 fprintf(stderr,
960 "ehci: PERIODIC list base register set while periodic schedule\n"
961 " is enabled and HC is enabled\n");
962 }
963 break;
964
965 case ASYNCLISTADDR:
966 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
967 fprintf(stderr,
968 "ehci: ASYNC list address register set while async schedule\n"
969 " is enabled and HC is enabled\n");
970 }
971 break;
972 }
973
974 *mmio = val;
975 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
976 }
977
978
979 // TODO : Put in common header file, duplication from usb-ohci.c
980
981 /* Get an array of dwords from main memory */
982 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
983 {
984 int i;
985
986 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
987 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
988 *buf = le32_to_cpu(*buf);
989 }
990
991 return 1;
992 }
993
994 /* Put an array of dwords in to main memory */
995 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
996 {
997 int i;
998
999 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1000 uint32_t tmp = cpu_to_le32(*buf);
1001 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
1002 }
1003
1004 return 1;
1005 }
1006
1007 // 4.10.2
1008
1009 static int ehci_qh_do_overlay(EHCIQueue *q)
1010 {
1011 int i;
1012 int dtoggle;
1013 int ping;
1014 int eps;
1015 int reload;
1016
1017 // remember values in fields to preserve in qh after overlay
1018
1019 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1020 ping = q->qh.token & QTD_TOKEN_PING;
1021
1022 q->qh.current_qtd = q->qtdaddr;
1023 q->qh.next_qtd = q->qtd.next;
1024 q->qh.altnext_qtd = q->qtd.altnext;
1025 q->qh.token = q->qtd.token;
1026
1027
1028 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1029 if (eps == EHCI_QH_EPS_HIGH) {
1030 q->qh.token &= ~QTD_TOKEN_PING;
1031 q->qh.token |= ping;
1032 }
1033
1034 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1035 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1036
1037 for (i = 0; i < 5; i++) {
1038 q->qh.bufptr[i] = q->qtd.bufptr[i];
1039 }
1040
1041 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1042 // preserve QH DT bit
1043 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1044 q->qh.token |= dtoggle;
1045 }
1046
1047 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1048 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1049
1050 put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1051
1052 return 0;
1053 }
1054
1055 static int ehci_buffer_rw(EHCIQueue *q, int bytes, int rw)
1056 {
1057 int bufpos = 0;
1058 int cpage, offset;
1059 uint32_t head;
1060 uint32_t tail;
1061
1062
1063 if (!bytes) {
1064 return 0;
1065 }
1066
1067 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1068 if (cpage > 4) {
1069 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1070 return USB_RET_PROCERR;
1071 }
1072
1073 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1074
1075 do {
1076 /* start and end of this page */
1077 head = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1078 tail = head + ~QTD_BUFPTR_MASK + 1;
1079 /* add offset into page */
1080 head |= offset;
1081
1082 if (bytes <= (tail - head)) {
1083 tail = head + bytes;
1084 }
1085
1086 trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos);
1087 cpu_physical_memory_rw(head, q->buffer + bufpos, tail - head, rw);
1088
1089 bufpos += (tail - head);
1090 offset += (tail - head);
1091 bytes -= (tail - head);
1092
1093 if (bytes > 0) {
1094 cpage++;
1095 offset = 0;
1096 }
1097 } while (bytes > 0);
1098
1099 /* save cpage */
1100 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1101
1102 /* save offset into cpage */
1103 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1104 q->qh.bufptr[0] |= offset;
1105
1106 return 0;
1107 }
1108
1109 static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
1110 {
1111 EHCIQueue *q = container_of(packet, EHCIQueue, packet);
1112
1113 trace_usb_ehci_queue_action(q, "wakeup");
1114 assert(q->async == EHCI_ASYNC_INFLIGHT);
1115 q->async = EHCI_ASYNC_FINISHED;
1116 q->usb_status = packet->len;
1117 }
1118
1119 static void ehci_execute_complete(EHCIQueue *q)
1120 {
1121 int c_err, reload;
1122
1123 assert(q->async != EHCI_ASYNC_INFLIGHT);
1124 q->async = EHCI_ASYNC_NONE;
1125
1126 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1127 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1128
1129 if (q->usb_status < 0) {
1130 err:
1131 /* TO-DO: put this is in a function that can be invoked below as well */
1132 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1133 c_err--;
1134 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1135
1136 switch(q->usb_status) {
1137 case USB_RET_NODEV:
1138 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1139 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1140 break;
1141 case USB_RET_STALL:
1142 q->qh.token |= QTD_TOKEN_HALT;
1143 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1144 break;
1145 case USB_RET_NAK:
1146 /* 4.10.3 */
1147 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1148 if ((q->pid == USB_TOKEN_IN) && reload) {
1149 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1150 nakcnt--;
1151 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1152 } else if (!reload) {
1153 return;
1154 }
1155 break;
1156 case USB_RET_BABBLE:
1157 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1158 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1159 break;
1160 default:
1161 /* should not be triggerable */
1162 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1163 assert(0);
1164 break;
1165 }
1166 } else {
1167 // DPRINTF("Short packet condition\n");
1168 // TODO check 4.12 for splits
1169
1170 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1171 q->usb_status = USB_RET_BABBLE;
1172 goto err;
1173 }
1174
1175 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1176 if (ehci_buffer_rw(q, q->usb_status, 1) != 0) {
1177 q->usb_status = USB_RET_PROCERR;
1178 return;
1179 }
1180 q->tbytes -= q->usb_status;
1181 } else {
1182 q->tbytes = 0;
1183 }
1184
1185 DPRINTF("updating tbytes to %d\n", q->tbytes);
1186 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1187 }
1188
1189 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1190 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1191
1192 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1193 ehci_record_interrupt(q->ehci, USBSTS_INT);
1194 }
1195 }
1196
1197 // 4.10.3
1198
1199 static int ehci_execute(EHCIQueue *q)
1200 {
1201 USBPort *port;
1202 USBDevice *dev;
1203 int ret;
1204 int i;
1205 int endp;
1206 int devadr;
1207
1208 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1209 fprintf(stderr, "Attempting to execute inactive QH\n");
1210 return USB_RET_PROCERR;
1211 }
1212
1213 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1214 if (q->tbytes > BUFF_SIZE) {
1215 fprintf(stderr, "Request for more bytes than allowed\n");
1216 return USB_RET_PROCERR;
1217 }
1218
1219 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1220 switch(q->pid) {
1221 case 0: q->pid = USB_TOKEN_OUT; break;
1222 case 1: q->pid = USB_TOKEN_IN; break;
1223 case 2: q->pid = USB_TOKEN_SETUP; break;
1224 default: fprintf(stderr, "bad token\n"); break;
1225 }
1226
1227 if ((q->tbytes && q->pid != USB_TOKEN_IN) &&
1228 (ehci_buffer_rw(q, q->tbytes, 0) != 0)) {
1229 return USB_RET_PROCERR;
1230 }
1231
1232 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1233 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1234
1235 ret = USB_RET_NODEV;
1236
1237 // TO-DO: associating device with ehci port
1238 for(i = 0; i < NB_PORTS; i++) {
1239 port = &q->ehci->ports[i];
1240 dev = port->dev;
1241
1242 // TODO sometime we will also need to check if we are the port owner
1243
1244 if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) {
1245 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1246 i, q->ehci->portsc[i]);
1247 continue;
1248 }
1249
1250 q->packet.pid = q->pid;
1251 q->packet.devaddr = devadr;
1252 q->packet.devep = endp;
1253 q->packet.data = q->buffer;
1254 q->packet.len = q->tbytes;
1255
1256 ret = usb_handle_packet(dev, &q->packet);
1257
1258 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1259 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1260 q->packet.len, q->tbytes, endp, ret);
1261
1262 if (ret != USB_RET_NODEV) {
1263 break;
1264 }
1265 }
1266
1267 if (ret > BUFF_SIZE) {
1268 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1269 return USB_RET_PROCERR;
1270 }
1271
1272 return ret;
1273 }
1274
1275 /* 4.7.2
1276 */
1277
1278 static int ehci_process_itd(EHCIState *ehci,
1279 EHCIitd *itd)
1280 {
1281 USBPort *port;
1282 USBDevice *dev;
1283 int ret;
1284 uint32_t i, j, len, len1, len2, pid, dir, devaddr, endp;
1285 uint32_t pg, off, ptr1, ptr2, max, mult;
1286
1287 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1288 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1289 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1290 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1291 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1292
1293 for(i = 0; i < 8; i++) {
1294 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1295 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1296 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1297 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1298 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1299 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1300
1301 if (len > max * mult) {
1302 len = max * mult;
1303 }
1304
1305 if (len > BUFF_SIZE) {
1306 return USB_RET_PROCERR;
1307 }
1308
1309 if (off + len > 4096) {
1310 /* transfer crosses page border */
1311 len2 = off + len - 4096;
1312 len1 = len - len2;
1313 } else {
1314 len1 = len;
1315 len2 = 0;
1316 }
1317
1318 if (!dir) {
1319 pid = USB_TOKEN_OUT;
1320 trace_usb_ehci_data(0, pg, off, ptr1 + off, len1, 0);
1321 cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 0);
1322 if (len2) {
1323 trace_usb_ehci_data(0, pg+1, 0, ptr2, len2, len1);
1324 cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 0);
1325 }
1326 } else {
1327 pid = USB_TOKEN_IN;
1328 }
1329
1330 ret = USB_RET_NODEV;
1331
1332 for (j = 0; j < NB_PORTS; j++) {
1333 port = &ehci->ports[j];
1334 dev = port->dev;
1335
1336 // TODO sometime we will also need to check if we are the port owner
1337
1338 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1339 continue;
1340 }
1341
1342 ehci->ipacket.pid = pid;
1343 ehci->ipacket.devaddr = devaddr;
1344 ehci->ipacket.devep = endp;
1345 ehci->ipacket.data = ehci->ibuffer;
1346 ehci->ipacket.len = len;
1347
1348 ret = usb_handle_packet(dev, &ehci->ipacket);
1349
1350 if (ret != USB_RET_NODEV) {
1351 break;
1352 }
1353 }
1354
1355 #if 0
1356 /* In isoch, there is no facility to indicate a NAK so let's
1357 * instead just complete a zero-byte transaction. Setting
1358 * DBERR seems too draconian.
1359 */
1360
1361 if (ret == USB_RET_NAK) {
1362 if (ehci->isoch_pause > 0) {
1363 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1364 ehci->isoch_pause--;
1365 return 0;
1366 } else if (ehci->isoch_pause == -1) {
1367 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1368 // Pause frindex for up to 50 msec waiting for data from
1369 // remote
1370 ehci->isoch_pause = 50;
1371 return 0;
1372 } else {
1373 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1374 ret = 0;
1375 }
1376 } else {
1377 DPRINTF("ISOCH: received ACK, clearing pause\n");
1378 ehci->isoch_pause = -1;
1379 }
1380 #else
1381 if (ret == USB_RET_NAK) {
1382 ret = 0;
1383 }
1384 #endif
1385
1386 if (ret >= 0) {
1387 if (!dir) {
1388 /* OUT */
1389 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1390 } else {
1391 /* IN */
1392 if (len1 > ret) {
1393 len1 = ret;
1394 }
1395 if (len2 > ret - len1) {
1396 len2 = ret - len1;
1397 }
1398 if (len1) {
1399 trace_usb_ehci_data(1, pg, off, ptr1 + off, len1, 0);
1400 cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 1);
1401 }
1402 if (len2) {
1403 trace_usb_ehci_data(1, pg+1, 0, ptr2, len2, len1);
1404 cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 1);
1405 }
1406 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1407 }
1408
1409 if (itd->transact[i] & ITD_XACT_IOC) {
1410 ehci_record_interrupt(ehci, USBSTS_INT);
1411 }
1412 }
1413 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1414 }
1415 }
1416 return 0;
1417 }
1418
1419 /* This state is the entry point for asynchronous schedule
1420 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1421 */
1422 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1423 {
1424 EHCIqh qh;
1425 int i = 0;
1426 int again = 0;
1427 uint32_t entry = ehci->asynclistaddr;
1428
1429 /* set reclamation flag at start event (4.8.6) */
1430 if (async) {
1431 ehci_set_usbsts(ehci, USBSTS_REC);
1432 }
1433
1434 ehci_queues_rip_unused(ehci);
1435
1436 /* Find the head of the list (4.9.1.1) */
1437 for(i = 0; i < MAX_QH; i++) {
1438 get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1439 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1440
1441 if (qh.epchar & QH_EPCHAR_H) {
1442 if (async) {
1443 entry |= (NLPTR_TYPE_QH << 1);
1444 }
1445
1446 ehci_set_fetch_addr(ehci, async, entry);
1447 ehci_set_state(ehci, async, EST_FETCHENTRY);
1448 again = 1;
1449 goto out;
1450 }
1451
1452 entry = qh.next;
1453 if (entry == ehci->asynclistaddr) {
1454 break;
1455 }
1456 }
1457
1458 /* no head found for list. */
1459
1460 ehci_set_state(ehci, async, EST_ACTIVE);
1461
1462 out:
1463 return again;
1464 }
1465
1466
1467 /* This state is the entry point for periodic schedule processing as
1468 * well as being a continuation state for async processing.
1469 */
1470 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1471 {
1472 int again = 0;
1473 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1474
1475 if (entry < 0x1000) {
1476 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1477 ehci_set_state(ehci, async, EST_ACTIVE);
1478 goto out;
1479 }
1480
1481 /* section 4.8, only QH in async schedule */
1482 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1483 fprintf(stderr, "non queue head request in async schedule\n");
1484 return -1;
1485 }
1486
1487 switch (NLPTR_TYPE_GET(entry)) {
1488 case NLPTR_TYPE_QH:
1489 ehci_set_state(ehci, async, EST_FETCHQH);
1490 again = 1;
1491 break;
1492
1493 case NLPTR_TYPE_ITD:
1494 ehci_set_state(ehci, async, EST_FETCHITD);
1495 again = 1;
1496 break;
1497
1498 default:
1499 // TODO: handle siTD and FSTN types
1500 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1501 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1502 return -1;
1503 }
1504
1505 out:
1506 return again;
1507 }
1508
1509 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1510 {
1511 uint32_t entry;
1512 EHCIQueue *q;
1513 int reload;
1514
1515 entry = ehci_get_fetch_addr(ehci, async);
1516 q = ehci_find_queue_by_qh(ehci, entry);
1517 if (NULL == q) {
1518 q = ehci_alloc_queue(ehci, async);
1519 }
1520 q->qhaddr = entry;
1521 q->seen++;
1522
1523 if (q->seen > 1) {
1524 /* we are going in circles -- stop processing */
1525 ehci_set_state(ehci, async, EST_ACTIVE);
1526 q = NULL;
1527 goto out;
1528 }
1529
1530 get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1531 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1532
1533 if (q->async == EHCI_ASYNC_INFLIGHT) {
1534 /* I/O still in progress -- skip queue */
1535 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1536 goto out;
1537 }
1538 if (q->async == EHCI_ASYNC_FINISHED) {
1539 /* I/O finished -- continue processing queue */
1540 trace_usb_ehci_queue_action(q, "resume");
1541 ehci_set_state(ehci, async, EST_EXECUTING);
1542 goto out;
1543 }
1544
1545 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1546
1547 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1548 if (ehci->usbsts & USBSTS_REC) {
1549 ehci_clear_usbsts(ehci, USBSTS_REC);
1550 } else {
1551 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1552 " - done processing\n", q->qhaddr);
1553 ehci_set_state(ehci, async, EST_ACTIVE);
1554 q = NULL;
1555 goto out;
1556 }
1557 }
1558
1559 #if EHCI_DEBUG
1560 if (q->qhaddr != q->qh.next) {
1561 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1562 q->qhaddr,
1563 q->qh.epchar & QH_EPCHAR_H,
1564 q->qh.token & QTD_TOKEN_HALT,
1565 q->qh.token & QTD_TOKEN_ACTIVE,
1566 q->qh.next);
1567 }
1568 #endif
1569
1570 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1571 if (reload) {
1572 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1573 }
1574
1575 if (q->qh.token & QTD_TOKEN_HALT) {
1576 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1577
1578 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1579 q->qtdaddr = q->qh.current_qtd;
1580 ehci_set_state(ehci, async, EST_FETCHQTD);
1581
1582 } else {
1583 /* EHCI spec version 1.0 Section 4.10.2 */
1584 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1585 }
1586
1587 out:
1588 return q;
1589 }
1590
1591 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1592 {
1593 uint32_t entry;
1594 EHCIitd itd;
1595
1596 assert(!async);
1597 entry = ehci_get_fetch_addr(ehci, async);
1598
1599 get_dwords(NLPTR_GET(entry),(uint32_t *) &itd,
1600 sizeof(EHCIitd) >> 2);
1601 ehci_trace_itd(ehci, entry, &itd);
1602
1603 if (ehci_process_itd(ehci, &itd) != 0) {
1604 return -1;
1605 }
1606
1607 put_dwords(NLPTR_GET(entry), (uint32_t *) &itd,
1608 sizeof(EHCIitd) >> 2);
1609 ehci_set_fetch_addr(ehci, async, itd.next);
1610 ehci_set_state(ehci, async, EST_FETCHENTRY);
1611
1612 return 1;
1613 }
1614
1615 /* Section 4.10.2 - paragraph 3 */
1616 static int ehci_state_advqueue(EHCIQueue *q, int async)
1617 {
1618 #if 0
1619 /* TO-DO: 4.10.2 - paragraph 2
1620 * if I-bit is set to 1 and QH is not active
1621 * go to horizontal QH
1622 */
1623 if (I-bit set) {
1624 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1625 goto out;
1626 }
1627 #endif
1628
1629 /*
1630 * want data and alt-next qTD is valid
1631 */
1632 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1633 (q->qh.altnext_qtd > 0x1000) &&
1634 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1635 q->qtdaddr = q->qh.altnext_qtd;
1636 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1637
1638 /*
1639 * next qTD is valid
1640 */
1641 } else if ((q->qh.next_qtd > 0x1000) &&
1642 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1643 q->qtdaddr = q->qh.next_qtd;
1644 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1645
1646 /*
1647 * no valid qTD, try next QH
1648 */
1649 } else {
1650 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1651 }
1652
1653 return 1;
1654 }
1655
1656 /* Section 4.10.2 - paragraph 4 */
1657 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1658 {
1659 int again = 0;
1660
1661 get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2);
1662 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1663
1664 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1665 ehci_set_state(q->ehci, async, EST_EXECUTE);
1666 again = 1;
1667 } else {
1668 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1669 again = 1;
1670 }
1671
1672 return again;
1673 }
1674
1675 static int ehci_state_horizqh(EHCIQueue *q, int async)
1676 {
1677 int again = 0;
1678
1679 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1680 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1681 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1682 again = 1;
1683 } else {
1684 ehci_set_state(q->ehci, async, EST_ACTIVE);
1685 }
1686
1687 return again;
1688 }
1689
1690 /*
1691 * Write the qh back to guest physical memory. This step isn't
1692 * in the EHCI spec but we need to do it since we don't share
1693 * physical memory with our guest VM.
1694 *
1695 * The first three dwords are read-only for the EHCI, so skip them
1696 * when writing back the qh.
1697 */
1698 static void ehci_flush_qh(EHCIQueue *q)
1699 {
1700 uint32_t *qh = (uint32_t *) &q->qh;
1701 uint32_t dwords = sizeof(EHCIqh) >> 2;
1702 uint32_t addr = NLPTR_GET(q->qhaddr);
1703
1704 put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1705 }
1706
1707 static int ehci_state_execute(EHCIQueue *q, int async)
1708 {
1709 int again = 0;
1710 int reload, nakcnt;
1711 int smask;
1712
1713 if (ehci_qh_do_overlay(q) != 0) {
1714 return -1;
1715 }
1716
1717 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1718
1719 if (!smask) {
1720 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1721 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1722 if (reload && !nakcnt) {
1723 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1724 again = 1;
1725 goto out;
1726 }
1727 }
1728
1729 // TODO verify enough time remains in the uframe as in 4.4.1.1
1730 // TODO write back ptr to async list when done or out of time
1731 // TODO Windows does not seem to ever set the MULT field
1732
1733 if (!async) {
1734 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1735 if (!transactCtr) {
1736 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1737 again = 1;
1738 goto out;
1739 }
1740 }
1741
1742 if (async) {
1743 ehci_set_usbsts(q->ehci, USBSTS_REC);
1744 }
1745
1746 q->usb_status = ehci_execute(q);
1747 if (q->usb_status == USB_RET_PROCERR) {
1748 again = -1;
1749 goto out;
1750 }
1751 if (q->usb_status == USB_RET_ASYNC) {
1752 ehci_flush_qh(q);
1753 trace_usb_ehci_queue_action(q, "suspend");
1754 q->async = EHCI_ASYNC_INFLIGHT;
1755 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1756 again = 1;
1757 goto out;
1758 }
1759
1760 ehci_set_state(q->ehci, async, EST_EXECUTING);
1761 again = 1;
1762
1763 out:
1764 return again;
1765 }
1766
1767 static int ehci_state_executing(EHCIQueue *q, int async)
1768 {
1769 int again = 0;
1770 int reload, nakcnt;
1771
1772 ehci_execute_complete(q);
1773 if (q->usb_status == USB_RET_ASYNC) {
1774 goto out;
1775 }
1776 if (q->usb_status == USB_RET_PROCERR) {
1777 again = -1;
1778 goto out;
1779 }
1780
1781 // 4.10.3
1782 if (!async) {
1783 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1784 transactCtr--;
1785 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1786 // 4.10.3, bottom of page 82, should exit this state when transaction
1787 // counter decrements to 0
1788 }
1789
1790 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1791 if (reload) {
1792 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1793 if (q->usb_status == USB_RET_NAK) {
1794 if (nakcnt) {
1795 nakcnt--;
1796 }
1797 } else {
1798 nakcnt = reload;
1799 }
1800 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1801 }
1802
1803 /* 4.10.5 */
1804 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1805 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1806 } else {
1807 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1808 }
1809
1810 again = 1;
1811
1812 out:
1813 ehci_flush_qh(q);
1814 return again;
1815 }
1816
1817
1818 static int ehci_state_writeback(EHCIQueue *q, int async)
1819 {
1820 int again = 0;
1821
1822 /* Write back the QTD from the QH area */
1823 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1824 put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd,
1825 sizeof(EHCIqtd) >> 2);
1826
1827 /*
1828 * EHCI specs say go horizontal here.
1829 *
1830 * We can also advance the queue here for performance reasons. We
1831 * need to take care to only take that shortcut in case we've
1832 * processed the qtd just written back without errors, i.e. halt
1833 * bit is clear.
1834 */
1835 if (q->qh.token & QTD_TOKEN_HALT) {
1836 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1837 again = 1;
1838 } else {
1839 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1840 again = 1;
1841 }
1842 return again;
1843 }
1844
1845 /*
1846 * This is the state machine that is common to both async and periodic
1847 */
1848
1849 static void ehci_advance_state(EHCIState *ehci,
1850 int async)
1851 {
1852 EHCIQueue *q = NULL;
1853 int again;
1854 int iter = 0;
1855
1856 do {
1857 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1858 iter++;
1859 /* if we are roaming a lot of QH without executing a qTD
1860 * something is wrong with the linked list. TO-DO: why is
1861 * this hack needed?
1862 */
1863 assert(iter < MAX_ITERATIONS);
1864 #if 0
1865 if (iter > MAX_ITERATIONS) {
1866 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1867 ehci_set_state(ehci, async, EST_ACTIVE);
1868 break;
1869 }
1870 #endif
1871 }
1872 switch(ehci_get_state(ehci, async)) {
1873 case EST_WAITLISTHEAD:
1874 again = ehci_state_waitlisthead(ehci, async);
1875 break;
1876
1877 case EST_FETCHENTRY:
1878 again = ehci_state_fetchentry(ehci, async);
1879 break;
1880
1881 case EST_FETCHQH:
1882 q = ehci_state_fetchqh(ehci, async);
1883 again = q ? 1 : 0;
1884 break;
1885
1886 case EST_FETCHITD:
1887 again = ehci_state_fetchitd(ehci, async);
1888 break;
1889
1890 case EST_ADVANCEQUEUE:
1891 again = ehci_state_advqueue(q, async);
1892 break;
1893
1894 case EST_FETCHQTD:
1895 again = ehci_state_fetchqtd(q, async);
1896 break;
1897
1898 case EST_HORIZONTALQH:
1899 again = ehci_state_horizqh(q, async);
1900 break;
1901
1902 case EST_EXECUTE:
1903 iter = 0;
1904 again = ehci_state_execute(q, async);
1905 break;
1906
1907 case EST_EXECUTING:
1908 assert(q != NULL);
1909 again = ehci_state_executing(q, async);
1910 break;
1911
1912 case EST_WRITEBACK:
1913 again = ehci_state_writeback(q, async);
1914 break;
1915
1916 default:
1917 fprintf(stderr, "Bad state!\n");
1918 again = -1;
1919 assert(0);
1920 break;
1921 }
1922
1923 if (again < 0) {
1924 fprintf(stderr, "processing error - resetting ehci HC\n");
1925 ehci_reset(ehci);
1926 again = 0;
1927 assert(0);
1928 }
1929 }
1930 while (again);
1931
1932 ehci_commit_interrupt(ehci);
1933 }
1934
1935 static void ehci_advance_async_state(EHCIState *ehci)
1936 {
1937 int async = 1;
1938
1939 switch(ehci_get_state(ehci, async)) {
1940 case EST_INACTIVE:
1941 if (!(ehci->usbcmd & USBCMD_ASE)) {
1942 break;
1943 }
1944 ehci_set_usbsts(ehci, USBSTS_ASS);
1945 ehci_set_state(ehci, async, EST_ACTIVE);
1946 // No break, fall through to ACTIVE
1947
1948 case EST_ACTIVE:
1949 if ( !(ehci->usbcmd & USBCMD_ASE)) {
1950 ehci_clear_usbsts(ehci, USBSTS_ASS);
1951 ehci_set_state(ehci, async, EST_INACTIVE);
1952 break;
1953 }
1954
1955 /* If the doorbell is set, the guest wants to make a change to the
1956 * schedule. The host controller needs to release cached data.
1957 * (section 4.8.2)
1958 */
1959 if (ehci->usbcmd & USBCMD_IAAD) {
1960 DPRINTF("ASYNC: doorbell request acknowledged\n");
1961 ehci->usbcmd &= ~USBCMD_IAAD;
1962 ehci_set_interrupt(ehci, USBSTS_IAA);
1963 break;
1964 }
1965
1966 /* make sure guest has acknowledged */
1967 /* TO-DO: is this really needed? */
1968 if (ehci->usbsts & USBSTS_IAA) {
1969 DPRINTF("IAA status bit still set.\n");
1970 break;
1971 }
1972
1973 /* check that address register has been set */
1974 if (ehci->asynclistaddr == 0) {
1975 break;
1976 }
1977
1978 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
1979 ehci_advance_state(ehci, async);
1980 break;
1981
1982 default:
1983 /* this should only be due to a developer mistake */
1984 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1985 "Resetting to active\n", ehci->astate);
1986 assert(0);
1987 }
1988 }
1989
1990 static void ehci_advance_periodic_state(EHCIState *ehci)
1991 {
1992 uint32_t entry;
1993 uint32_t list;
1994 int async = 0;
1995
1996 // 4.6
1997
1998 switch(ehci_get_state(ehci, async)) {
1999 case EST_INACTIVE:
2000 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
2001 ehci_set_usbsts(ehci, USBSTS_PSS);
2002 ehci_set_state(ehci, async, EST_ACTIVE);
2003 // No break, fall through to ACTIVE
2004 } else
2005 break;
2006
2007 case EST_ACTIVE:
2008 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2009 ehci_clear_usbsts(ehci, USBSTS_PSS);
2010 ehci_set_state(ehci, async, EST_INACTIVE);
2011 break;
2012 }
2013
2014 list = ehci->periodiclistbase & 0xfffff000;
2015 /* check that register has been set */
2016 if (list == 0) {
2017 break;
2018 }
2019 list |= ((ehci->frindex & 0x1ff8) >> 1);
2020
2021 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
2022 entry = le32_to_cpu(entry);
2023
2024 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2025 ehci->frindex / 8, list, entry);
2026 ehci_set_fetch_addr(ehci, async,entry);
2027 ehci_set_state(ehci, async, EST_FETCHENTRY);
2028 ehci_advance_state(ehci, async);
2029 break;
2030
2031 default:
2032 /* this should only be due to a developer mistake */
2033 fprintf(stderr, "ehci: Bad periodic state %d. "
2034 "Resetting to active\n", ehci->pstate);
2035 assert(0);
2036 }
2037 }
2038
2039 static void ehci_frame_timer(void *opaque)
2040 {
2041 EHCIState *ehci = opaque;
2042 int64_t expire_time, t_now;
2043 int usec_elapsed;
2044 int frames;
2045 int usec_now;
2046 int i;
2047 int skipped_frames = 0;
2048
2049
2050 t_now = qemu_get_clock_ns(vm_clock);
2051 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
2052 if (expire_time == t_now) {
2053 expire_time++;
2054 }
2055
2056 usec_now = t_now / 1000;
2057 usec_elapsed = usec_now - ehci->last_run_usec;
2058 frames = usec_elapsed / FRAME_TIMER_USEC;
2059 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
2060
2061 for (i = 0; i < frames; i++) {
2062 if ( !(ehci->usbsts & USBSTS_HALT)) {
2063 if (ehci->isoch_pause <= 0) {
2064 ehci->frindex += 8;
2065 }
2066
2067 if (ehci->frindex > 0x00001fff) {
2068 ehci->frindex = 0;
2069 ehci_set_interrupt(ehci, USBSTS_FLR);
2070 }
2071
2072 ehci->sofv = (ehci->frindex - 1) >> 3;
2073 ehci->sofv &= 0x000003ff;
2074 }
2075
2076 if (frames - i > 10) {
2077 skipped_frames++;
2078 } else {
2079 ehci_advance_periodic_state(ehci);
2080 }
2081
2082 ehci->last_run_usec += FRAME_TIMER_USEC;
2083 }
2084
2085 #if 0
2086 if (skipped_frames) {
2087 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2088 }
2089 #endif
2090
2091 /* Async is not inside loop since it executes everything it can once
2092 * called
2093 */
2094 ehci_advance_async_state(ehci);
2095
2096 qemu_mod_timer(ehci->frame_timer, expire_time);
2097 }
2098
2099 static CPUReadMemoryFunc *ehci_readfn[3]={
2100 ehci_mem_readb,
2101 ehci_mem_readw,
2102 ehci_mem_readl
2103 };
2104
2105 static CPUWriteMemoryFunc *ehci_writefn[3]={
2106 ehci_mem_writeb,
2107 ehci_mem_writew,
2108 ehci_mem_writel
2109 };
2110
2111 static void ehci_map(PCIDevice *pci_dev, int region_num,
2112 pcibus_t addr, pcibus_t size, int type)
2113 {
2114 EHCIState *s =(EHCIState *)pci_dev;
2115
2116 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
2117 region_num, addr, size, s->mem);
2118 s->mem_base = addr;
2119 cpu_register_physical_memory(addr, size, s->mem);
2120 }
2121
2122 static void ehci_device_destroy(USBBus *bus, USBDevice *dev)
2123 {
2124 EHCIState *s = container_of(bus, EHCIState, bus);
2125
2126 ehci_queues_rip_device(s, dev);
2127 }
2128
2129 static int usb_ehci_initfn(PCIDevice *dev);
2130
2131 static USBPortOps ehci_port_ops = {
2132 .attach = ehci_attach,
2133 .detach = ehci_detach,
2134 .complete = ehci_async_complete_packet,
2135 };
2136
2137 static USBBusOps ehci_bus_ops = {
2138 .device_destroy = ehci_device_destroy,
2139 };
2140
2141 static PCIDeviceInfo ehci_info = {
2142 .qdev.name = "usb-ehci",
2143 .qdev.size = sizeof(EHCIState),
2144 .init = usb_ehci_initfn,
2145 .vendor_id = PCI_VENDOR_ID_INTEL,
2146 .device_id = PCI_DEVICE_ID_INTEL_82801D,
2147 .revision = 0x10,
2148 .class_id = PCI_CLASS_SERIAL_USB,
2149 };
2150
2151 static int usb_ehci_initfn(PCIDevice *dev)
2152 {
2153 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2154 uint8_t *pci_conf = s->dev.config;
2155 int i;
2156
2157 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2158
2159 /* capabilities pointer */
2160 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2161 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2162
2163 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2164 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2165 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2166
2167 // pci_conf[0x50] = 0x01; // power management caps
2168
2169 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2170 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2171 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2172
2173 pci_conf[0x64] = 0x00;
2174 pci_conf[0x65] = 0x00;
2175 pci_conf[0x66] = 0x00;
2176 pci_conf[0x67] = 0x00;
2177 pci_conf[0x68] = 0x01;
2178 pci_conf[0x69] = 0x00;
2179 pci_conf[0x6a] = 0x00;
2180 pci_conf[0x6b] = 0x00; // USBLEGSUP
2181 pci_conf[0x6c] = 0x00;
2182 pci_conf[0x6d] = 0x00;
2183 pci_conf[0x6e] = 0x00;
2184 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2185
2186 // 2.2 host controller interface version
2187 s->mmio[0x00] = (uint8_t) OPREGBASE;
2188 s->mmio[0x01] = 0x00;
2189 s->mmio[0x02] = 0x00;
2190 s->mmio[0x03] = 0x01; // HC version
2191 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2192 s->mmio[0x05] = 0x00; // No companion ports at present
2193 s->mmio[0x06] = 0x00;
2194 s->mmio[0x07] = 0x00;
2195 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2196 s->mmio[0x09] = 0x68; // EECP
2197 s->mmio[0x0a] = 0x00;
2198 s->mmio[0x0b] = 0x00;
2199
2200 s->irq = s->dev.irq[3];
2201
2202 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2203 for(i = 0; i < NB_PORTS; i++) {
2204 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2205 USB_SPEED_MASK_HIGH);
2206 usb_port_location(&s->ports[i], NULL, i+1);
2207 s->ports[i].dev = 0;
2208 }
2209
2210 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2211 QTAILQ_INIT(&s->queues);
2212
2213 qemu_register_reset(ehci_reset, s);
2214
2215 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2216 DEVICE_LITTLE_ENDIAN);
2217
2218 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2219 ehci_map);
2220
2221 fprintf(stderr, "*** EHCI support is under development ***\n");
2222
2223 return 0;
2224 }
2225
2226 static void ehci_register(void)
2227 {
2228 pci_qdev_register(&ehci_info);
2229 }
2230 device_init(ehci_register);
2231
2232 /*
2233 * vim: expandtab ts=4
2234 */
Zhi Yong Wu's QEmu Source Tree - dev