2 * High Precisition Event Timer emulation
4 * Copyright (c) 2007 Alexander Graf
5 * Copyright (c) 2008 IBM Corporation
7 * Authors: Beth Kon <bkon@us.ibm.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * *****************************************************************
24 * This driver attempts to emulate an HPET device in software.
30 #include "qemu-timer.h"
31 #include "hpet_emul.h"
33 #include "mc146818rtc.h"
37 #define DPRINTF printf
42 #define HPET_MSI_SUPPORT 0
45 typedef struct HPETTimer
{ /* timers */
46 uint8_t tn
; /*timer number*/
47 QEMUTimer
*qemu_timer
;
48 struct HPETState
*state
;
49 /* Memory-mapped, software visible timer registers */
50 uint64_t config
; /* configuration/cap */
51 uint64_t cmp
; /* comparator */
52 uint64_t fsb
; /* FSB route */
53 /* Hidden register state */
54 uint64_t period
; /* Last value written to comparator */
55 uint8_t wrap_flag
; /* timer pop will indicate wrap for one-shot 32-bit
56 * mode. Next pop will be actual timer expiration.
60 typedef struct HPETState
{
63 qemu_irq irqs
[HPET_NUM_IRQ_ROUTES
];
65 uint8_t rtc_irq_level
;
67 HPETTimer timer
[HPET_MAX_TIMERS
];
69 /* Memory-mapped, software visible registers */
70 uint64_t capability
; /* capabilities */
71 uint64_t config
; /* configuration */
72 uint64_t isr
; /* interrupt status reg */
73 uint64_t hpet_counter
; /* main counter */
74 uint8_t hpet_id
; /* instance id */
77 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
79 static uint32_t hpet_in_legacy_mode(HPETState
*s
)
81 return s
->config
& HPET_CFG_LEGACY
;
84 static uint32_t timer_int_route(struct HPETTimer
*timer
)
86 return (timer
->config
& HPET_TN_INT_ROUTE_MASK
) >> HPET_TN_INT_ROUTE_SHIFT
;
89 static uint32_t timer_fsb_route(HPETTimer
*t
)
91 return t
->config
& HPET_TN_FSB_ENABLE
;
94 static uint32_t hpet_enabled(HPETState
*s
)
96 return s
->config
& HPET_CFG_ENABLE
;
99 static uint32_t timer_is_periodic(HPETTimer
*t
)
101 return t
->config
& HPET_TN_PERIODIC
;
104 static uint32_t timer_enabled(HPETTimer
*t
)
106 return t
->config
& HPET_TN_ENABLE
;
109 static uint32_t hpet_time_after(uint64_t a
, uint64_t b
)
111 return ((int32_t)(b
) - (int32_t)(a
) < 0);
114 static uint32_t hpet_time_after64(uint64_t a
, uint64_t b
)
116 return ((int64_t)(b
) - (int64_t)(a
) < 0);
119 static uint64_t ticks_to_ns(uint64_t value
)
121 return (muldiv64(value
, HPET_CLK_PERIOD
, FS_PER_NS
));
124 static uint64_t ns_to_ticks(uint64_t value
)
126 return (muldiv64(value
, FS_PER_NS
, HPET_CLK_PERIOD
));
129 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old
, uint64_t mask
)
136 static int activating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
138 return (!(old
& mask
) && (new & mask
));
141 static int deactivating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
143 return ((old
& mask
) && !(new & mask
));
146 static uint64_t hpet_get_ticks(HPETState
*s
)
148 return ns_to_ticks(qemu_get_clock(vm_clock
) + s
->hpet_offset
);
152 * calculate diff between comparator value and current ticks
154 static inline uint64_t hpet_calculate_diff(HPETTimer
*t
, uint64_t current
)
157 if (t
->config
& HPET_TN_32BIT
) {
160 cmp
= (uint32_t)t
->cmp
;
161 diff
= cmp
- (uint32_t)current
;
162 diff
= (int32_t)diff
> 0 ? diff
: (uint32_t)0;
163 return (uint64_t)diff
;
168 diff
= cmp
- current
;
169 diff
= (int64_t)diff
> 0 ? diff
: (uint64_t)0;
174 static void update_irq(struct HPETTimer
*timer
, int set
)
180 if (timer
->tn
<= 1 && hpet_in_legacy_mode(timer
->state
)) {
181 /* if LegacyReplacementRoute bit is set, HPET specification requires
182 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
183 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
185 route
= (timer
->tn
== 0) ? 0 : RTC_ISA_IRQ
;
187 route
= timer_int_route(timer
);
190 mask
= 1 << timer
->tn
;
191 if (!set
|| !timer_enabled(timer
) || !hpet_enabled(timer
->state
)) {
193 if (!timer_fsb_route(timer
)) {
194 qemu_irq_lower(s
->irqs
[route
]);
196 } else if (timer_fsb_route(timer
)) {
197 stl_phys(timer
->fsb
>> 32, timer
->fsb
& 0xffffffff);
198 } else if (timer
->config
& HPET_TN_TYPE_LEVEL
) {
200 qemu_irq_raise(s
->irqs
[route
]);
203 qemu_irq_pulse(s
->irqs
[route
]);
207 static void hpet_pre_save(void *opaque
)
209 HPETState
*s
= opaque
;
211 /* save current counter value */
212 s
->hpet_counter
= hpet_get_ticks(s
);
215 static int hpet_pre_load(void *opaque
)
217 HPETState
*s
= opaque
;
219 /* version 1 only supports 3, later versions will load the actual value */
220 s
->num_timers
= HPET_MIN_TIMERS
;
224 static int hpet_post_load(void *opaque
, int version_id
)
226 HPETState
*s
= opaque
;
228 /* Recalculate the offset between the main counter and guest time */
229 s
->hpet_offset
= ticks_to_ns(s
->hpet_counter
) - qemu_get_clock(vm_clock
);
231 /* Push number of timers into capability returned via HPET_ID */
232 s
->capability
&= ~HPET_ID_NUM_TIM_MASK
;
233 s
->capability
|= (s
->num_timers
- 1) << HPET_ID_NUM_TIM_SHIFT
;
234 hpet_cfg
.hpet
[s
->hpet_id
].event_timer_block_id
= (uint32_t)s
->capability
;
236 /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
237 s
->flags
&= ~(1 << HPET_MSI_SUPPORT
);
238 if (s
->timer
[0].config
& HPET_TN_FSB_CAP
) {
239 s
->flags
|= 1 << HPET_MSI_SUPPORT
;
242 if (hpet_in_legacy_mode(s
)) {
249 static const VMStateDescription vmstate_hpet_timer
= {
250 .name
= "hpet_timer",
252 .minimum_version_id
= 1,
253 .minimum_version_id_old
= 1,
254 .fields
= (VMStateField
[]) {
255 VMSTATE_UINT8(tn
, HPETTimer
),
256 VMSTATE_UINT64(config
, HPETTimer
),
257 VMSTATE_UINT64(cmp
, HPETTimer
),
258 VMSTATE_UINT64(fsb
, HPETTimer
),
259 VMSTATE_UINT64(period
, HPETTimer
),
260 VMSTATE_UINT8(wrap_flag
, HPETTimer
),
261 VMSTATE_TIMER(qemu_timer
, HPETTimer
),
262 VMSTATE_END_OF_LIST()
266 static const VMStateDescription vmstate_hpet
= {
269 .minimum_version_id
= 1,
270 .minimum_version_id_old
= 1,
271 .pre_save
= hpet_pre_save
,
272 .pre_load
= hpet_pre_load
,
273 .post_load
= hpet_post_load
,
274 .fields
= (VMStateField
[]) {
275 VMSTATE_UINT64(config
, HPETState
),
276 VMSTATE_UINT64(isr
, HPETState
),
277 VMSTATE_UINT64(hpet_counter
, HPETState
),
278 VMSTATE_UINT8_V(num_timers
, HPETState
, 2),
279 VMSTATE_STRUCT_VARRAY_UINT8(timer
, HPETState
, num_timers
, 0,
280 vmstate_hpet_timer
, HPETTimer
),
281 VMSTATE_END_OF_LIST()
286 * timer expiration callback
288 static void hpet_timer(void *opaque
)
290 HPETTimer
*t
= opaque
;
293 uint64_t period
= t
->period
;
294 uint64_t cur_tick
= hpet_get_ticks(t
->state
);
296 if (timer_is_periodic(t
) && period
!= 0) {
297 if (t
->config
& HPET_TN_32BIT
) {
298 while (hpet_time_after(cur_tick
, t
->cmp
)) {
299 t
->cmp
= (uint32_t)(t
->cmp
+ t
->period
);
302 while (hpet_time_after64(cur_tick
, t
->cmp
)) {
306 diff
= hpet_calculate_diff(t
, cur_tick
);
307 qemu_mod_timer(t
->qemu_timer
,
308 qemu_get_clock(vm_clock
) + (int64_t)ticks_to_ns(diff
));
309 } else if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
311 diff
= hpet_calculate_diff(t
, cur_tick
);
312 qemu_mod_timer(t
->qemu_timer
, qemu_get_clock(vm_clock
) +
313 (int64_t)ticks_to_ns(diff
));
320 static void hpet_set_timer(HPETTimer
*t
)
323 uint32_t wrap_diff
; /* how many ticks until we wrap? */
324 uint64_t cur_tick
= hpet_get_ticks(t
->state
);
326 /* whenever new timer is being set up, make sure wrap_flag is 0 */
328 diff
= hpet_calculate_diff(t
, cur_tick
);
330 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
331 * counter wraps in addition to an interrupt with comparator match.
333 if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
334 wrap_diff
= 0xffffffff - (uint32_t)cur_tick
;
335 if (wrap_diff
< (uint32_t)diff
) {
340 qemu_mod_timer(t
->qemu_timer
,
341 qemu_get_clock(vm_clock
) + (int64_t)ticks_to_ns(diff
));
344 static void hpet_del_timer(HPETTimer
*t
)
346 qemu_del_timer(t
->qemu_timer
);
351 static uint32_t hpet_ram_readb(void *opaque
, target_phys_addr_t addr
)
353 printf("qemu: hpet_read b at %" PRIx64
"\n", addr
);
357 static uint32_t hpet_ram_readw(void *opaque
, target_phys_addr_t addr
)
359 printf("qemu: hpet_read w at %" PRIx64
"\n", addr
);
364 static uint32_t hpet_ram_readl(void *opaque
, target_phys_addr_t addr
)
366 HPETState
*s
= opaque
;
367 uint64_t cur_tick
, index
;
369 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64
"\n", addr
);
371 /*address range of all TN regs*/
372 if (index
>= 0x100 && index
<= 0x3ff) {
373 uint8_t timer_id
= (addr
- 0x100) / 0x20;
374 HPETTimer
*timer
= &s
->timer
[timer_id
];
376 if (timer_id
> s
->num_timers
) {
377 DPRINTF("qemu: timer id out of range\n");
381 switch ((addr
- 0x100) % 0x20) {
383 return timer
->config
;
384 case HPET_TN_CFG
+ 4: // Interrupt capabilities
385 return timer
->config
>> 32;
386 case HPET_TN_CMP
: // comparator register
388 case HPET_TN_CMP
+ 4:
389 return timer
->cmp
>> 32;
392 case HPET_TN_ROUTE
+ 4:
393 return timer
->fsb
>> 32;
395 DPRINTF("qemu: invalid hpet_ram_readl\n");
401 return s
->capability
;
403 return s
->capability
>> 32;
407 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
410 if (hpet_enabled(s
)) {
411 cur_tick
= hpet_get_ticks(s
);
413 cur_tick
= s
->hpet_counter
;
415 DPRINTF("qemu: reading counter = %" PRIx64
"\n", cur_tick
);
417 case HPET_COUNTER
+ 4:
418 if (hpet_enabled(s
)) {
419 cur_tick
= hpet_get_ticks(s
);
421 cur_tick
= s
->hpet_counter
;
423 DPRINTF("qemu: reading counter + 4 = %" PRIx64
"\n", cur_tick
);
424 return cur_tick
>> 32;
428 DPRINTF("qemu: invalid hpet_ram_readl\n");
436 static void hpet_ram_writeb(void *opaque
, target_phys_addr_t addr
,
439 printf("qemu: invalid hpet_write b at %" PRIx64
" = %#x\n",
443 static void hpet_ram_writew(void *opaque
, target_phys_addr_t addr
,
446 printf("qemu: invalid hpet_write w at %" PRIx64
" = %#x\n",
451 static void hpet_ram_writel(void *opaque
, target_phys_addr_t addr
,
455 HPETState
*s
= opaque
;
456 uint64_t old_val
, new_val
, val
, index
;
458 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64
" = %#x\n", addr
, value
);
460 old_val
= hpet_ram_readl(opaque
, addr
);
463 /*address range of all TN regs*/
464 if (index
>= 0x100 && index
<= 0x3ff) {
465 uint8_t timer_id
= (addr
- 0x100) / 0x20;
466 HPETTimer
*timer
= &s
->timer
[timer_id
];
468 DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id
);
469 if (timer_id
> s
->num_timers
) {
470 DPRINTF("qemu: timer id out of range\n");
473 switch ((addr
- 0x100) % 0x20) {
475 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
476 if (activating_bit(old_val
, new_val
, HPET_TN_FSB_ENABLE
)) {
477 update_irq(timer
, 0);
479 val
= hpet_fixup_reg(new_val
, old_val
, HPET_TN_CFG_WRITE_MASK
);
480 timer
->config
= (timer
->config
& 0xffffffff00000000ULL
) | val
;
481 if (new_val
& HPET_TN_32BIT
) {
482 timer
->cmp
= (uint32_t)timer
->cmp
;
483 timer
->period
= (uint32_t)timer
->period
;
485 if (activating_bit(old_val
, new_val
, HPET_TN_ENABLE
)) {
486 hpet_set_timer(timer
);
487 } else if (deactivating_bit(old_val
, new_val
, HPET_TN_ENABLE
)) {
488 hpet_del_timer(timer
);
491 case HPET_TN_CFG
+ 4: // Interrupt capabilities
492 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
494 case HPET_TN_CMP
: // comparator register
495 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
496 if (timer
->config
& HPET_TN_32BIT
) {
497 new_val
= (uint32_t)new_val
;
499 if (!timer_is_periodic(timer
)
500 || (timer
->config
& HPET_TN_SETVAL
)) {
501 timer
->cmp
= (timer
->cmp
& 0xffffffff00000000ULL
) | new_val
;
503 if (timer_is_periodic(timer
)) {
505 * FIXME: Clamp period to reasonable min value?
506 * Clamp period to reasonable max value
508 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
510 (timer
->period
& 0xffffffff00000000ULL
) | new_val
;
512 timer
->config
&= ~HPET_TN_SETVAL
;
513 if (hpet_enabled(s
)) {
514 hpet_set_timer(timer
);
517 case HPET_TN_CMP
+ 4: // comparator register high order
518 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
519 if (!timer_is_periodic(timer
)
520 || (timer
->config
& HPET_TN_SETVAL
)) {
521 timer
->cmp
= (timer
->cmp
& 0xffffffffULL
) | new_val
<< 32;
524 * FIXME: Clamp period to reasonable min value?
525 * Clamp period to reasonable max value
527 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
529 (timer
->period
& 0xffffffffULL
) | new_val
<< 32;
531 timer
->config
&= ~HPET_TN_SETVAL
;
532 if (hpet_enabled(s
)) {
533 hpet_set_timer(timer
);
537 timer
->fsb
= (timer
->fsb
& 0xffffffff00000000ULL
) | new_val
;
539 case HPET_TN_ROUTE
+ 4:
540 timer
->fsb
= (new_val
<< 32) | (timer
->fsb
& 0xffffffff);
543 DPRINTF("qemu: invalid hpet_ram_writel\n");
552 val
= hpet_fixup_reg(new_val
, old_val
, HPET_CFG_WRITE_MASK
);
553 s
->config
= (s
->config
& 0xffffffff00000000ULL
) | val
;
554 if (activating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
555 /* Enable main counter and interrupt generation. */
557 ticks_to_ns(s
->hpet_counter
) - qemu_get_clock(vm_clock
);
558 for (i
= 0; i
< s
->num_timers
; i
++) {
559 if ((&s
->timer
[i
])->cmp
!= ~0ULL) {
560 hpet_set_timer(&s
->timer
[i
]);
563 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
564 /* Halt main counter and disable interrupt generation. */
565 s
->hpet_counter
= hpet_get_ticks(s
);
566 for (i
= 0; i
< s
->num_timers
; i
++) {
567 hpet_del_timer(&s
->timer
[i
]);
570 /* i8254 and RTC are disabled when HPET is in legacy mode */
571 if (activating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
573 qemu_irq_lower(s
->irqs
[RTC_ISA_IRQ
]);
574 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
576 qemu_set_irq(s
->irqs
[RTC_ISA_IRQ
], s
->rtc_irq_level
);
580 DPRINTF("qemu: invalid HPET_CFG+4 write \n");
583 val
= new_val
& s
->isr
;
584 for (i
= 0; i
< s
->num_timers
; i
++) {
585 if (val
& (1 << i
)) {
586 update_irq(&s
->timer
[i
], 0);
591 if (hpet_enabled(s
)) {
592 DPRINTF("qemu: Writing counter while HPET enabled!\n");
595 (s
->hpet_counter
& 0xffffffff00000000ULL
) | value
;
596 DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64
"\n",
597 value
, s
->hpet_counter
);
599 case HPET_COUNTER
+ 4:
600 if (hpet_enabled(s
)) {
601 DPRINTF("qemu: Writing counter while HPET enabled!\n");
604 (s
->hpet_counter
& 0xffffffffULL
) | (((uint64_t)value
) << 32);
605 DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64
"\n",
606 value
, s
->hpet_counter
);
609 DPRINTF("qemu: invalid hpet_ram_writel\n");
615 static CPUReadMemoryFunc
* const hpet_ram_read
[] = {
626 static CPUWriteMemoryFunc
* const hpet_ram_write
[] = {
637 static void hpet_reset(DeviceState
*d
)
639 HPETState
*s
= FROM_SYSBUS(HPETState
, sysbus_from_qdev(d
));
641 static int count
= 0;
643 for (i
= 0; i
< s
->num_timers
; i
++) {
644 HPETTimer
*timer
= &s
->timer
[i
];
646 hpet_del_timer(timer
);
648 timer
->config
= HPET_TN_PERIODIC_CAP
| HPET_TN_SIZE_CAP
;
649 if (s
->flags
& (1 << HPET_MSI_SUPPORT
)) {
650 timer
->config
|= HPET_TN_FSB_CAP
;
652 /* advertise availability of ioapic inti2 */
653 timer
->config
|= 0x00000004ULL
<< 32;
654 timer
->period
= 0ULL;
655 timer
->wrap_flag
= 0;
658 s
->hpet_counter
= 0ULL;
659 s
->hpet_offset
= 0ULL;
662 /* we don't enable pit when hpet_reset is first called (by hpet_init)
663 * because hpet is taking over for pit here. On subsequent invocations,
664 * hpet_reset is called due to system reset. At this point control must
665 * be returned to pit until SW reenables hpet.
669 hpet_cfg
.hpet
[s
->hpet_id
].event_timer_block_id
= (uint32_t)s
->capability
;
670 hpet_cfg
.hpet
[s
->hpet_id
].address
= sysbus_from_qdev(d
)->mmio
[0].addr
;
674 static void hpet_handle_rtc_irq(void *opaque
, int n
, int level
)
676 HPETState
*s
= FROM_SYSBUS(HPETState
, opaque
);
678 s
->rtc_irq_level
= level
;
679 if (!hpet_in_legacy_mode(s
)) {
680 qemu_set_irq(s
->irqs
[RTC_ISA_IRQ
], level
);
684 static int hpet_init(SysBusDevice
*dev
)
686 HPETState
*s
= FROM_SYSBUS(HPETState
, dev
);
690 if (hpet_cfg
.count
== UINT8_MAX
) {
695 if (hpet_cfg
.count
== 8) {
696 fprintf(stderr
, "Only 8 instances of HPET is allowed\n");
700 s
->hpet_id
= hpet_cfg
.count
++;
702 for (i
= 0; i
< HPET_NUM_IRQ_ROUTES
; i
++) {
703 sysbus_init_irq(dev
, &s
->irqs
[i
]);
706 if (s
->num_timers
< HPET_MIN_TIMERS
) {
707 s
->num_timers
= HPET_MIN_TIMERS
;
708 } else if (s
->num_timers
> HPET_MAX_TIMERS
) {
709 s
->num_timers
= HPET_MAX_TIMERS
;
711 for (i
= 0; i
< HPET_MAX_TIMERS
; i
++) {
712 timer
= &s
->timer
[i
];
713 timer
->qemu_timer
= qemu_new_timer(vm_clock
, hpet_timer
, timer
);
718 /* 64-bit main counter; LegacyReplacementRoute. */
719 s
->capability
= 0x8086a001ULL
;
720 s
->capability
|= (s
->num_timers
- 1) << HPET_ID_NUM_TIM_SHIFT
;
721 s
->capability
|= ((HPET_CLK_PERIOD
) << 32);
723 isa_reserve_irq(RTC_ISA_IRQ
);
724 qdev_init_gpio_in(&dev
->qdev
, hpet_handle_rtc_irq
, 1);
727 iomemtype
= cpu_register_io_memory(hpet_ram_read
,
729 DEVICE_NATIVE_ENDIAN
);
730 sysbus_init_mmio(dev
, 0x400, iomemtype
);
734 static SysBusDeviceInfo hpet_device_info
= {
736 .qdev
.size
= sizeof(HPETState
),
738 .qdev
.vmsd
= &vmstate_hpet
,
739 .qdev
.reset
= hpet_reset
,
741 .qdev
.props
= (Property
[]) {
742 DEFINE_PROP_UINT8("timers", HPETState
, num_timers
, HPET_MIN_TIMERS
),
743 DEFINE_PROP_BIT("msi", HPETState
, flags
, HPET_MSI_SUPPORT
, false),
744 DEFINE_PROP_END_OF_LIST(),
748 static void hpet_register_device(void)
750 sysbus_register_withprop(&hpet_device_info
);
753 device_init(hpet_register_device
)