hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "ioapic.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24 #include "sysbus.h"
  25 #include "trace.h"
  26 #include "kvm.h"
  27
  28 /* APIC Local Vector Table */
  29 #define APIC_LVT_TIMER   0
  30 #define APIC_LVT_THERMAL 1
  31 #define APIC_LVT_PERFORM 2
  32 #define APIC_LVT_LINT0   3
  33 #define APIC_LVT_LINT1   4
  34 #define APIC_LVT_ERROR   5
  35 #define APIC_LVT_NB      6
  36
  37 /* APIC delivery modes */
  38 #define APIC_DM_FIXED   0
  39 #define APIC_DM_LOWPRI  1
  40 #define APIC_DM_SMI     2
  41 #define APIC_DM_NMI     4
  42 #define APIC_DM_INIT    5
  43 #define APIC_DM_SIPI    6
  44 #define APIC_DM_EXTINT  7
  45
  46 /* APIC destination mode */
  47 #define APIC_DESTMODE_FLAT      0xf
  48 #define APIC_DESTMODE_CLUSTER   1
  49
  50 #define APIC_TRIGGER_EDGE  0
  51 #define APIC_TRIGGER_LEVEL 1
  52
  53 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  54 #define APIC_LVT_MASKED                 (1<<16)
  55 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  56 #define APIC_LVT_REMOTE_IRR             (1<<14)
  57 #define APIC_INPUT_POLARITY             (1<<13)
  58 #define APIC_SEND_PENDING               (1<<12)
  59
  60 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  61
  62 #define APIC_SV_DIRECTED_IO             (1<<12)
  63 #define APIC_SV_ENABLE                  (1<<8)
  64
  65 #define MAX_APICS 255
  66 #define MAX_APIC_WORDS 8
  67
  68 /* Intel APIC constants: from include/asm/msidef.h */
  69 #define MSI_DATA_VECTOR_SHIFT           0
  70 #define MSI_DATA_VECTOR_MASK            0x000000ff
  71 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  72 #define MSI_DATA_TRIGGER_SHIFT          15
  73 #define MSI_DATA_LEVEL_SHIFT            14
  74 #define MSI_ADDR_DEST_MODE_SHIFT        2
  75 #define MSI_ADDR_DEST_ID_SHIFT          12
  76 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  77
  78 #define MSI_ADDR_SIZE                   0x100000
  79
  80 typedef struct APICState APICState;
  81
  82 struct APICState {
  83     SysBusDevice busdev;
  84     void *cpu_env;
  85     uint32_t apicbase;
  86     uint8_t id;
  87     uint8_t arb_id;
  88     uint8_t tpr;
  89     uint32_t spurious_vec;
  90     uint8_t log_dest;
  91     uint8_t dest_mode;
  92     uint32_t isr[8];  /* in service register */
  93     uint32_t tmr[8];  /* trigger mode register */
  94     uint32_t irr[8]; /* interrupt request register */
  95     uint32_t lvt[APIC_LVT_NB];
  96     uint32_t esr; /* error register */
  97     uint32_t icr[2];
  98
  99     uint32_t divide_conf;
 100     int count_shift;
 101     uint32_t initial_count;
 102     int64_t initial_count_load_time, next_time;
 103     uint32_t idx;
 104     QEMUTimer *timer;
 105     int sipi_vector;
 106     int wait_for_sipi;
 107 };
 108
 109 static APICState *local_apics[MAX_APICS + 1];
 110 static int apic_irq_delivered;
 111
 112 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 113 static void apic_update_irq(APICState *s);
 114 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 115                                       uint8_t dest, uint8_t dest_mode);
 116
 117 /* Find first bit starting from msb */
 118 static int fls_bit(uint32_t value)
 119 {
 120     return 31 - clz32(value);
 121 }
 122
 123 /* Find first bit starting from lsb */
 124 static int ffs_bit(uint32_t value)
 125 {
 126     return ctz32(value);
 127 }
 128
 129 static inline void set_bit(uint32_t *tab, int index)
 130 {
 131     int i, mask;
 132     i = index >> 5;
 133     mask = 1 << (index & 0x1f);
 134     tab[i] |= mask;
 135 }
 136
 137 static inline void reset_bit(uint32_t *tab, int index)
 138 {
 139     int i, mask;
 140     i = index >> 5;
 141     mask = 1 << (index & 0x1f);
 142     tab[i] &= ~mask;
 143 }
 144
 145 static inline int get_bit(uint32_t *tab, int index)
 146 {
 147     int i, mask;
 148     i = index >> 5;
 149     mask = 1 << (index & 0x1f);
 150     return !!(tab[i] & mask);
 151 }
 152
 153 static void apic_local_deliver(APICState *s, int vector)
 154 {
 155     uint32_t lvt = s->lvt[vector];
 156     int trigger_mode;
 157
 158     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 159
 160     if (lvt & APIC_LVT_MASKED)
 161         return;
 162
 163     switch ((lvt >> 8) & 7) {
 164     case APIC_DM_SMI:
 165         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 166         break;
 167
 168     case APIC_DM_NMI:
 169         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 170         break;
 171
 172     case APIC_DM_EXTINT:
 173         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 174         break;
 175
 176     case APIC_DM_FIXED:
 177         trigger_mode = APIC_TRIGGER_EDGE;
 178         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 179             (lvt & APIC_LVT_LEVEL_TRIGGER))
 180             trigger_mode = APIC_TRIGGER_LEVEL;
 181         apic_set_irq(s, lvt & 0xff, trigger_mode);
 182     }
 183 }
 184
 185 void apic_deliver_pic_intr(DeviceState *d, int level)
 186 {
 187     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 188
 189     if (level) {
 190         apic_local_deliver(s, APIC_LVT_LINT0);
 191     } else {
 192         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 193
 194         switch ((lvt >> 8) & 7) {
 195         case APIC_DM_FIXED:
 196             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 197                 break;
 198             reset_bit(s->irr, lvt & 0xff);
 199             /* fall through */
 200         case APIC_DM_EXTINT:
 201             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 202             break;
 203         }
 204     }
 205 }
 206
 207 #define foreach_apic(apic, deliver_bitmask, code) \
 208 {\
 209     int __i, __j, __mask;\
 210     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 211         __mask = deliver_bitmask[__i];\
 212         if (__mask) {\
 213             for(__j = 0; __j < 32; __j++) {\
 214                 if (__mask & (1 << __j)) {\
 215                     apic = local_apics[__i * 32 + __j];\
 216                     if (apic) {\
 217                         code;\
 218                     }\
 219                 }\
 220             }\
 221         }\
 222     }\
 223 }
 224
 225 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 226                              uint8_t delivery_mode,
 227                              uint8_t vector_num, uint8_t polarity,
 228                              uint8_t trigger_mode)
 229 {
 230     APICState *apic_iter;
 231
 232     switch (delivery_mode) {
 233         case APIC_DM_LOWPRI:
 234             /* XXX: search for focus processor, arbitration */
 235             {
 236                 int i, d;
 237                 d = -1;
 238                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 239                     if (deliver_bitmask[i]) {
 240                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 241                         break;
 242                     }
 243                 }
 244                 if (d >= 0) {
 245                     apic_iter = local_apics[d];
 246                     if (apic_iter) {
 247                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 248                     }
 249                 }
 250             }
 251             return;
 252
 253         case APIC_DM_FIXED:
 254             break;
 255
 256         case APIC_DM_SMI:
 257             foreach_apic(apic_iter, deliver_bitmask,
 258                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 259             return;
 260
 261         case APIC_DM_NMI:
 262             foreach_apic(apic_iter, deliver_bitmask,
 263                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 264             return;
 265
 266         case APIC_DM_INIT:
 267             /* normal INIT IPI sent to processors */
 268             foreach_apic(apic_iter, deliver_bitmask,
 269                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 270             return;
 271
 272         case APIC_DM_EXTINT:
 273             /* handled in I/O APIC code */
 274             break;
 275
 276         default:
 277             return;
 278     }
 279
 280     foreach_apic(apic_iter, deliver_bitmask,
 281                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 282 }
 283
 284 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 285                       uint8_t delivery_mode, uint8_t vector_num,
 286                       uint8_t polarity, uint8_t trigger_mode)
 287 {
 288     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 289
 290     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 291                            polarity, trigger_mode);
 292
 293     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 294     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 295                      trigger_mode);
 296 }
 297
 298 void cpu_set_apic_base(DeviceState *d, uint64_t val)
 299 {
 300     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 301
 302     trace_cpu_set_apic_base(val);
 303
 304     if (!s)
 305         return;
 306     if (kvm_enabled() && kvm_irqchip_in_kernel())
 307         s->apicbase = val;
 308     else
 309         s->apicbase = (val & 0xfffff000) |
 310             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 311     /* if disabled, cannot be enabled again */
 312     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 313         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 314         cpu_clear_apic_feature(s->cpu_env);
 315         s->spurious_vec &= ~APIC_SV_ENABLE;
 316     }
 317 }
 318
 319 uint64_t cpu_get_apic_base(DeviceState *d)
 320 {
 321     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 322
 323     trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
 324
 325     return s ? s->apicbase : 0;
 326 }
 327
 328 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
 329 {
 330     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 331
 332     if (!s)
 333         return;
 334     s->tpr = (val & 0x0f) << 4;
 335     apic_update_irq(s);
 336 }
 337
 338 uint8_t cpu_get_apic_tpr(DeviceState *d)
 339 {
 340     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 341
 342     return s ? s->tpr >> 4 : 0;
 343 }
 344
 345 /* return -1 if no bit is set */
 346 static int get_highest_priority_int(uint32_t *tab)
 347 {
 348     int i;
 349     for(i = 7; i >= 0; i--) {
 350         if (tab[i] != 0) {
 351             return i * 32 + fls_bit(tab[i]);
 352         }
 353     }
 354     return -1;
 355 }
 356
 357 static int apic_get_ppr(APICState *s)
 358 {
 359     int tpr, isrv, ppr;
 360
 361     tpr = (s->tpr >> 4);
 362     isrv = get_highest_priority_int(s->isr);
 363     if (isrv < 0)
 364         isrv = 0;
 365     isrv >>= 4;
 366     if (tpr >= isrv)
 367         ppr = s->tpr;
 368     else
 369         ppr = isrv << 4;
 370     return ppr;
 371 }
 372
 373 static int apic_get_arb_pri(APICState *s)
 374 {
 375     /* XXX: arbitration */
 376     return 0;
 377 }
 378
 379 /* signal the CPU if an irq is pending */
 380 static void apic_update_irq(APICState *s)
 381 {
 382     int irrv, ppr;
 383     if (!(s->spurious_vec & APIC_SV_ENABLE))
 384         return;
 385     irrv = get_highest_priority_int(s->irr);
 386     if (irrv < 0)
 387         return;
 388     ppr = apic_get_ppr(s);
 389     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 390         return;
 391     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 392 }
 393
 394 void apic_reset_irq_delivered(void)
 395 {
 396     trace_apic_reset_irq_delivered(apic_irq_delivered);
 397
 398     apic_irq_delivered = 0;
 399 }
 400
 401 int apic_get_irq_delivered(void)
 402 {
 403     trace_apic_get_irq_delivered(apic_irq_delivered);
 404
 405     return apic_irq_delivered;
 406 }
 407
 408 void apic_set_irq_delivered(void)
 409 {
 410     apic_irq_delivered = 1;
 411 }
 412
 413 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 414 {
 415     apic_irq_delivered += !get_bit(s->irr, vector_num);
 416
 417     trace_apic_set_irq(apic_irq_delivered);
 418
 419     set_bit(s->irr, vector_num);
 420     if (trigger_mode)
 421         set_bit(s->tmr, vector_num);
 422     else
 423         reset_bit(s->tmr, vector_num);
 424     apic_update_irq(s);
 425 }
 426
 427 static void apic_eoi(APICState *s)
 428 {
 429     int isrv;
 430     isrv = get_highest_priority_int(s->isr);
 431     if (isrv < 0)
 432         return;
 433     reset_bit(s->isr, isrv);
 434     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
 435         ioapic_eoi_broadcast(isrv);
 436     }
 437     apic_update_irq(s);
 438 }
 439
 440 static int apic_find_dest(uint8_t dest)
 441 {
 442     APICState *apic = local_apics[dest];
 443     int i;
 444
 445     if (apic && apic->id == dest)
 446         return dest;  /* shortcut in case apic->id == apic->idx */
 447
 448     for (i = 0; i < MAX_APICS; i++) {
 449         apic = local_apics[i];
 450         if (apic && apic->id == dest)
 451             return i;
 452         if (!apic)
 453             break;
 454     }
 455
 456     return -1;
 457 }
 458
 459 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 460                                       uint8_t dest, uint8_t dest_mode)
 461 {
 462     APICState *apic_iter;
 463     int i;
 464
 465     if (dest_mode == 0) {
 466         if (dest == 0xff) {
 467             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 468         } else {
 469             int idx = apic_find_dest(dest);
 470             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 471             if (idx >= 0)
 472                 set_bit(deliver_bitmask, idx);
 473         }
 474     } else {
 475         /* XXX: cluster mode */
 476         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 477         for(i = 0; i < MAX_APICS; i++) {
 478             apic_iter = local_apics[i];
 479             if (apic_iter) {
 480                 if (apic_iter->dest_mode == 0xf) {
 481                     if (dest & apic_iter->log_dest)
 482                         set_bit(deliver_bitmask, i);
 483                 } else if (apic_iter->dest_mode == 0x0) {
 484                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 485                         (dest & apic_iter->log_dest & 0x0f)) {
 486                         set_bit(deliver_bitmask, i);
 487                     }
 488                 }
 489             } else {
 490                 break;
 491             }
 492         }
 493     }
 494 }
 495
 496 void apic_init_reset(DeviceState *d)
 497 {
 498     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 499     int i;
 500
 501     if (!s)
 502         return;
 503
 504     s->tpr = 0;
 505     s->spurious_vec = 0xff;
 506     s->log_dest = 0;
 507     s->dest_mode = 0xf;
 508     memset(s->isr, 0, sizeof(s->isr));
 509     memset(s->tmr, 0, sizeof(s->tmr));
 510     memset(s->irr, 0, sizeof(s->irr));
 511     for(i = 0; i < APIC_LVT_NB; i++)
 512         s->lvt[i] = 1 << 16; /* mask LVT */
 513     s->esr = 0;
 514     memset(s->icr, 0, sizeof(s->icr));
 515     s->divide_conf = 0;
 516     s->count_shift = 0;
 517     s->initial_count = 0;
 518     s->initial_count_load_time = 0;
 519     s->next_time = 0;
 520     s->wait_for_sipi = 1;
 521 }
 522
 523 static void apic_startup(APICState *s, int vector_num)
 524 {
 525     s->sipi_vector = vector_num;
 526     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 527 }
 528
 529 void apic_sipi(DeviceState *d)
 530 {
 531     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 532
 533     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 534
 535     if (!s->wait_for_sipi)
 536         return;
 537     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 538     s->wait_for_sipi = 0;
 539 }
 540
 541 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 542                          uint8_t delivery_mode, uint8_t vector_num,
 543                          uint8_t polarity, uint8_t trigger_mode)
 544 {
 545     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 546     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 547     int dest_shorthand = (s->icr[0] >> 18) & 3;
 548     APICState *apic_iter;
 549
 550     switch (dest_shorthand) {
 551     case 0:
 552         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 553         break;
 554     case 1:
 555         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 556         set_bit(deliver_bitmask, s->idx);
 557         break;
 558     case 2:
 559         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 560         break;
 561     case 3:
 562         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 563         reset_bit(deliver_bitmask, s->idx);
 564         break;
 565     }
 566
 567     switch (delivery_mode) {
 568         case APIC_DM_INIT:
 569             {
 570                 int trig_mode = (s->icr[0] >> 15) & 1;
 571                 int level = (s->icr[0] >> 14) & 1;
 572                 if (level == 0 && trig_mode == 1) {
 573                     foreach_apic(apic_iter, deliver_bitmask,
 574                                  apic_iter->arb_id = apic_iter->id );
 575                     return;
 576                 }
 577             }
 578             break;
 579
 580         case APIC_DM_SIPI:
 581             foreach_apic(apic_iter, deliver_bitmask,
 582                          apic_startup(apic_iter, vector_num) );
 583             return;
 584     }
 585
 586     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 587                      trigger_mode);
 588 }
 589
 590 int apic_get_interrupt(DeviceState *d)
 591 {
 592     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 593     int intno;
 594
 595     /* if the APIC is installed or enabled, we let the 8259 handle the
 596        IRQs */
 597     if (!s)
 598         return -1;
 599     if (!(s->spurious_vec & APIC_SV_ENABLE))
 600         return -1;
 601
 602     /* XXX: spurious IRQ handling */
 603     intno = get_highest_priority_int(s->irr);
 604     if (intno < 0)
 605         return -1;
 606     if (s->tpr && intno <= s->tpr)
 607         return s->spurious_vec & 0xff;
 608     reset_bit(s->irr, intno);
 609     set_bit(s->isr, intno);
 610     apic_update_irq(s);
 611     return intno;
 612 }
 613
 614 int apic_accept_pic_intr(DeviceState *d)
 615 {
 616     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 617     uint32_t lvt0;
 618
 619     if (!s)
 620         return -1;
 621
 622     lvt0 = s->lvt[APIC_LVT_LINT0];
 623
 624     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 625         (lvt0 & APIC_LVT_MASKED) == 0)
 626         return 1;
 627
 628     return 0;
 629 }
 630
 631 static uint32_t apic_get_current_count(APICState *s)
 632 {
 633     int64_t d;
 634     uint32_t val;
 635     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 636         s->count_shift;
 637     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 638         /* periodic */
 639         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 640     } else {
 641         if (d >= s->initial_count)
 642             val = 0;
 643         else
 644             val = s->initial_count - d;
 645     }
 646     return val;
 647 }
 648
 649 static void apic_timer_update(APICState *s, int64_t current_time)
 650 {
 651     int64_t next_time, d;
 652
 653     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 654         d = (current_time - s->initial_count_load_time) >>
 655             s->count_shift;
 656         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 657             if (!s->initial_count)
 658                 goto no_timer;
 659             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 660         } else {
 661             if (d >= s->initial_count)
 662                 goto no_timer;
 663             d = (uint64_t)s->initial_count + 1;
 664         }
 665         next_time = s->initial_count_load_time + (d << s->count_shift);
 666         qemu_mod_timer(s->timer, next_time);
 667         s->next_time = next_time;
 668     } else {
 669     no_timer:
 670         qemu_del_timer(s->timer);
 671     }
 672 }
 673
 674 static void apic_timer(void *opaque)
 675 {
 676     APICState *s = opaque;
 677
 678     apic_local_deliver(s, APIC_LVT_TIMER);
 679     apic_timer_update(s, s->next_time);
 680 }
 681
 682 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 683 {
 684     return 0;
 685 }
 686
 687 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 688 {
 689     return 0;
 690 }
 691
 692 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 693 {
 694 }
 695
 696 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 697 {
 698 }
 699
 700 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 701 {
 702     DeviceState *d;
 703     APICState *s;
 704     uint32_t val;
 705     int index;
 706
 707     d = cpu_get_current_apic();
 708     if (!d) {
 709         return 0;
 710     }
 711     s = DO_UPCAST(APICState, busdev.qdev, d);
 712
 713     index = (addr >> 4) & 0xff;
 714     switch(index) {
 715     case 0x02: /* id */
 716         val = s->id << 24;
 717         break;
 718     case 0x03: /* version */
 719         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 720         break;
 721     case 0x08:
 722         val = s->tpr;
 723         break;
 724     case 0x09:
 725         val = apic_get_arb_pri(s);
 726         break;
 727     case 0x0a:
 728         /* ppr */
 729         val = apic_get_ppr(s);
 730         break;
 731     case 0x0b:
 732         val = 0;
 733         break;
 734     case 0x0d:
 735         val = s->log_dest << 24;
 736         break;
 737     case 0x0e:
 738         val = s->dest_mode << 28;
 739         break;
 740     case 0x0f:
 741         val = s->spurious_vec;
 742         break;
 743     case 0x10 ... 0x17:
 744         val = s->isr[index & 7];
 745         break;
 746     case 0x18 ... 0x1f:
 747         val = s->tmr[index & 7];
 748         break;
 749     case 0x20 ... 0x27:
 750         val = s->irr[index & 7];
 751         break;
 752     case 0x28:
 753         val = s->esr;
 754         break;
 755     case 0x30:
 756     case 0x31:
 757         val = s->icr[index & 1];
 758         break;
 759     case 0x32 ... 0x37:
 760         val = s->lvt[index - 0x32];
 761         break;
 762     case 0x38:
 763         val = s->initial_count;
 764         break;
 765     case 0x39:
 766         val = apic_get_current_count(s);
 767         break;
 768     case 0x3e:
 769         val = s->divide_conf;
 770         break;
 771     default:
 772         s->esr |= ESR_ILLEGAL_ADDRESS;
 773         val = 0;
 774         break;
 775     }
 776     trace_apic_mem_readl(addr, val);
 777     return val;
 778 }
 779
 780 static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
 781 {
 782     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 783     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 784     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 785     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 786     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 787     /* XXX: Ignore redirection hint. */
 788     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 789 }
 790
 791 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 792 {
 793     DeviceState *d;
 794     APICState *s;
 795     int index = (addr >> 4) & 0xff;
 796     if (addr > 0xfff || !index) {
 797         /* MSI and MMIO APIC are at the same memory location,
 798          * but actually not on the global bus: MSI is on PCI bus
 799          * APIC is connected directly to the CPU.
 800          * Mapping them on the global bus happens to work because
 801          * MSI registers are reserved in APIC MMIO and vice versa. */
 802         apic_send_msi(addr, val);
 803         return;
 804     }
 805
 806     d = cpu_get_current_apic();
 807     if (!d) {
 808         return;
 809     }
 810     s = DO_UPCAST(APICState, busdev.qdev, d);
 811
 812     trace_apic_mem_writel(addr, val);
 813
 814     switch(index) {
 815     case 0x02:
 816         s->id = (val >> 24);
 817         break;
 818     case 0x03:
 819         break;
 820     case 0x08:
 821         s->tpr = val;
 822         apic_update_irq(s);
 823         break;
 824     case 0x09:
 825     case 0x0a:
 826         break;
 827     case 0x0b: /* EOI */
 828         apic_eoi(s);
 829         break;
 830     case 0x0d:
 831         s->log_dest = val >> 24;
 832         break;
 833     case 0x0e:
 834         s->dest_mode = val >> 28;
 835         break;
 836     case 0x0f:
 837         s->spurious_vec = val & 0x1ff;
 838         apic_update_irq(s);
 839         break;
 840     case 0x10 ... 0x17:
 841     case 0x18 ... 0x1f:
 842     case 0x20 ... 0x27:
 843     case 0x28:
 844         break;
 845     case 0x30:
 846         s->icr[0] = val;
 847         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 848                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 849                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 850         break;
 851     case 0x31:
 852         s->icr[1] = val;
 853         break;
 854     case 0x32 ... 0x37:
 855         {
 856             int n = index - 0x32;
 857             s->lvt[n] = val;
 858             if (n == APIC_LVT_TIMER)
 859                 apic_timer_update(s, qemu_get_clock(vm_clock));
 860         }
 861         break;
 862     case 0x38:
 863         s->initial_count = val;
 864         s->initial_count_load_time = qemu_get_clock(vm_clock);
 865         apic_timer_update(s, s->initial_count_load_time);
 866         break;
 867     case 0x39:
 868         break;
 869     case 0x3e:
 870         {
 871             int v;
 872             s->divide_conf = val & 0xb;
 873             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 874             s->count_shift = (v + 1) & 7;
 875         }
 876         break;
 877     default:
 878         s->esr |= ESR_ILLEGAL_ADDRESS;
 879         break;
 880     }
 881 }
 882
 883 #ifdef KVM_CAP_IRQCHIP
 884
 885 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 886 {
 887     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 888 }
 889
 890 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 891                                  int reg_id, uint32_t val)
 892 {
 893     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 894 }
 895
 896 static void kvm_kernel_lapic_save_to_user(APICState *s)
 897 {
 898     struct kvm_lapic_state apic;
 899     struct kvm_lapic_state *kapic = &apic;
 900     int i, v;
 901
 902     kvm_get_lapic(s->cpu_env, kapic);
 903
 904     s->id = kapic_reg(kapic, 0x2) >> 24;
 905     s->tpr = kapic_reg(kapic, 0x8);
 906     s->arb_id = kapic_reg(kapic, 0x9);
 907     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 908     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 909     s->spurious_vec = kapic_reg(kapic, 0xf);
 910     for (i = 0; i < 8; i++) {
 911         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 912         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 913         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 914     }
 915     s->esr = kapic_reg(kapic, 0x28);
 916     s->icr[0] = kapic_reg(kapic, 0x30);
 917     s->icr[1] = kapic_reg(kapic, 0x31);
 918     for (i = 0; i < APIC_LVT_NB; i++)
 919         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 920     s->initial_count = kapic_reg(kapic, 0x38);
 921     s->divide_conf = kapic_reg(kapic, 0x3e);
 922
 923     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 924     s->count_shift = (v + 1) & 7;
 925
 926     s->initial_count_load_time = qemu_get_clock(vm_clock);
 927     apic_timer_update(s, s->initial_count_load_time);
 928 }
 929
 930 static void kvm_kernel_lapic_load_from_user(APICState *s)
 931 {
 932     struct kvm_lapic_state apic;
 933     struct kvm_lapic_state *klapic = &apic;
 934     int i;
 935
 936     memset(klapic, 0, sizeof apic);
 937     kapic_set_reg(klapic, 0x2, s->id << 24);
 938     kapic_set_reg(klapic, 0x8, s->tpr);
 939     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 940     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 941     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 942     for (i = 0; i < 8; i++) {
 943         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 944         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 945         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 946     }
 947     kapic_set_reg(klapic, 0x28, s->esr);
 948     kapic_set_reg(klapic, 0x30, s->icr[0]);
 949     kapic_set_reg(klapic, 0x31, s->icr[1]);
 950     for (i = 0; i < APIC_LVT_NB; i++)
 951         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 952     kapic_set_reg(klapic, 0x38, s->initial_count);
 953     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 954
 955     kvm_set_lapic(s->cpu_env, klapic);
 956 }
 957
 958 #endif
 959
 960 void kvm_load_lapic(CPUState *env)
 961 {
 962 #ifdef KVM_CAP_IRQCHIP
 963     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 964
 965     if (!s) {
 966         return;
 967     }
 968
 969     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 970         kvm_kernel_lapic_load_from_user(s);
 971     }
 972 #endif
 973 }
 974
 975 void kvm_save_lapic(CPUState *env)
 976 {
 977 #ifdef KVM_CAP_IRQCHIP
 978     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 979
 980     if (!s) {
 981         return;
 982     }
 983
 984     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 985         kvm_kernel_lapic_save_to_user(s);
 986     }
 987 #endif
 988 }
 989
 990 /* This function is only used for old state version 1 and 2 */
 991 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 992 {
 993     APICState *s = opaque;
 994     int i;
 995
 996     if (version_id > 2)
 997         return -EINVAL;
 998
 999     /* XXX: what if the base changes? (registered memory regions) */
1000     qemu_get_be32s(f, &s->apicbase);
1001     qemu_get_8s(f, &s->id);
1002     qemu_get_8s(f, &s->arb_id);
1003     qemu_get_8s(f, &s->tpr);
1004     qemu_get_be32s(f, &s->spurious_vec);
1005     qemu_get_8s(f, &s->log_dest);
1006     qemu_get_8s(f, &s->dest_mode);
1007     for (i = 0; i < 8; i++) {
1008         qemu_get_be32s(f, &s->isr[i]);
1009         qemu_get_be32s(f, &s->tmr[i]);
1010         qemu_get_be32s(f, &s->irr[i]);
1011     }
1012     for (i = 0; i < APIC_LVT_NB; i++) {
1013         qemu_get_be32s(f, &s->lvt[i]);
1014     }
1015     qemu_get_be32s(f, &s->esr);
1016     qemu_get_be32s(f, &s->icr[0]);
1017     qemu_get_be32s(f, &s->icr[1]);
1018     qemu_get_be32s(f, &s->divide_conf);
1019     s->count_shift=qemu_get_be32(f);
1020     qemu_get_be32s(f, &s->initial_count);
1021     s->initial_count_load_time=qemu_get_be64(f);
1022     s->next_time=qemu_get_be64(f);
1023
1024     if (version_id >= 2)
1025         qemu_get_timer(f, s->timer);
1026     return 0;
1027 }
1028
1029 static const VMStateDescription vmstate_apic = {
1030     .name = "apic",
1031     .version_id = 3,
1032     .minimum_version_id = 3,
1033     .minimum_version_id_old = 1,
1034     .load_state_old = apic_load_old,
1035     .fields      = (VMStateField []) {
1036         VMSTATE_UINT32(apicbase, APICState),
1037         VMSTATE_UINT8(id, APICState),
1038         VMSTATE_UINT8(arb_id, APICState),
1039         VMSTATE_UINT8(tpr, APICState),
1040         VMSTATE_UINT32(spurious_vec, APICState),
1041         VMSTATE_UINT8(log_dest, APICState),
1042         VMSTATE_UINT8(dest_mode, APICState),
1043         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1044         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1045         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1046         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1047         VMSTATE_UINT32(esr, APICState),
1048         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1049         VMSTATE_UINT32(divide_conf, APICState),
1050         VMSTATE_INT32(count_shift, APICState),
1051         VMSTATE_UINT32(initial_count, APICState),
1052         VMSTATE_INT64(initial_count_load_time, APICState),
1053         VMSTATE_INT64(next_time, APICState),
1054         VMSTATE_TIMER(timer, APICState),
1055         VMSTATE_END_OF_LIST()
1056     }
1057 };
1058
1059 static void apic_reset(DeviceState *d)
1060 {
1061     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
1062     int bsp;
1063
1064     bsp = cpu_is_bsp(s->cpu_env);
1065     s->apicbase = 0xfee00000 |
1066         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1067
1068     apic_init_reset(d);
1069
1070     if (bsp) {
1071         /*
1072          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1073          * time typically by BIOS, so PIC interrupt can be delivered to the
1074          * processor when local APIC is enabled.
1075          */
1076         s->lvt[APIC_LVT_LINT0] = 0x700;
1077     }
1078 }
1079
1080 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1081     apic_mem_readb,
1082     apic_mem_readw,
1083     apic_mem_readl,
1084 };
1085
1086 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1087     apic_mem_writeb,
1088     apic_mem_writew,
1089     apic_mem_writel,
1090 };
1091
1092 static int apic_init1(SysBusDevice *dev)
1093 {
1094     APICState *s = FROM_SYSBUS(APICState, dev);
1095     int apic_io_memory;
1096     static int last_apic_idx;
1097
1098     if (last_apic_idx >= MAX_APICS) {
1099         return -1;
1100     }
1101     apic_io_memory = cpu_register_io_memory(apic_mem_read,
1102                                             apic_mem_write, NULL,
1103                                             DEVICE_NATIVE_ENDIAN);
1104     sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
1105
1106     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1107     s->idx = last_apic_idx++;
1108     local_apics[s->idx] = s;
1109     return 0;
1110 }
1111
1112 static SysBusDeviceInfo apic_info = {
1113     .init = apic_init1,
1114     .qdev.name = "apic",
1115     .qdev.size = sizeof(APICState),
1116     .qdev.vmsd = &vmstate_apic,
1117     .qdev.reset = apic_reset,
1118     .qdev.no_user = 1,
1119     .qdev.props = (Property[]) {
1120         DEFINE_PROP_UINT8("id", APICState, id, -1),
1121         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1122         DEFINE_PROP_END_OF_LIST(),
1123     }
1124 };
1125
1126 static void apic_register_devices(void)
1127 {
1128     sysbus_register_withprop(&apic_info);
1129 }
1130
1131 device_init(apic_register_devices)