13 . = . + 4096 * max_cpus
27 .quad 0x1e7 | (i << 21)
33 .quad ptl2 + 7 + 0 * 4096
34 .quad ptl2 + 7 + 1 * 4096
35 .quad ptl2 + 7 + 2 * 4096
36 .quad ptl2 + 7 + 3 * 4096
45 .word gdt64_end - gdt64 - 1
50 .quad 0x00af9b000000ffff // 64-bit code segment
51 .quad 0x00cf93000000ffff // 64-bit data segment
52 .quad 0x00affb000000ffff // 64-bit code segment (user)
53 .quad 0x00cff3000000ffff // 64-bit data segment (user)
54 .quad 0x00cf9b000000ffff // 32-bit code segment
55 .quad 0x00cf92000000ffff // 32-bit code segment
56 .quad 0x008F9A000000FFFF // 16-bit code segment
57 .quad 0x008F92000000FFFF // 16-bit data segment
61 .quad 0x000089000000ffff // 64-bit avail tss
62 .quad 0 // tss high addr
70 .quad ring0stacktop - i * 4096
72 .quad 0, 0, 0, 0, 0, 0, 0, 0
86 .long mb_magic, mb_flags, 0 - (mb_magic + mb_flags)
88 MSR_GS_BASE = 0xc0000101
90 .macro setup_percpu_area
93 mov $MSR_GS_BASE, %ecx
126 smp_stacktop: .long 0xa0000
132 .quad 0x00cf9b000000ffff // flat 32-bit code segment
133 .quad 0x00cf93000000ffff // flat 32-bit data segment
141 lgdtl gdt32_descr - sipi_entry
142 ljmpl $8, $ap_start32
145 .word gdt32_end - gdt32 - 1
159 lock/xaddl %esp, smp_stacktop
162 ljmpl $8, $ap_start64
171 lock incw cpu_online_count
178 call mask_pic_interrupts
194 mov $(APIC_DEFAULT_PHYS_BASE + APIC_ID), %eax
199 mov $((tss_end - tss) / max_cpus), %edx
202 mov %ax, tss_descr+2(%rbx)
204 mov %al, tss_descr+4(%rbx)
206 mov %al, tss_descr+7(%rbx)
208 mov %eax, tss_descr+8(%rbx)
209 lea tss_descr-gdt64(%rbx), %rax
217 mov $(sipi_end - sipi_entry), %rcx
219 mov $APIC_DEFAULT_PHYS_BASE, %eax
220 movl $(APIC_DEST_ALLBUT | APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT), APIC_ICR(%rax)
221 movl $(APIC_DEST_ALLBUT | APIC_DEST_PHYSICAL | APIC_DM_INIT), APIC_ICR(%rax)
222 movl $(APIC_DEST_ALLBUT | APIC_DEST_PHYSICAL | APIC_DM_STARTUP), APIC_ICR(%rax)
223 call fwcfg_get_nb_cpus
225 cmpw %ax, cpu_online_count
230 cpu_online_count: .word 1