hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "isa.h"
  28 #include "monitor.h"
  29 #include "qemu-timer.h"
  30
  31 #include "kvm.h"
  32
  33 /* debug PIC */
  34 //#define DEBUG_PIC
  35
  36 #ifdef DEBUG_PIC
  37 #define DPRINTF(fmt, ...)                                       \
  38     do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...)
  41 #endif
  42
  43 //#define DEBUG_IRQ_LATENCY
  44 //#define DEBUG_IRQ_COUNT
  45
  46 typedef struct PicState {
  47     uint8_t last_irr; /* edge detection */
  48     uint8_t irr; /* interrupt request register */
  49     uint8_t imr; /* interrupt mask register */
  50     uint8_t isr; /* interrupt service register */
  51     uint8_t priority_add; /* highest irq priority */
  52     uint8_t irq_base;
  53     uint8_t read_reg_select;
  54     uint8_t poll;
  55     uint8_t special_mask;
  56     uint8_t init_state;
  57     uint8_t auto_eoi;
  58     uint8_t rotate_on_auto_eoi;
  59     uint8_t special_fully_nested_mode;
  60     uint8_t init4; /* true if 4 byte init */
  61     uint8_t single_mode; /* true if slave pic is not initialized */
  62     uint8_t elcr; /* PIIX edge/trigger selection*/
  63     uint8_t elcr_mask;
  64     PicState2 *pics_state;
  65 } PicState;
  66
  67 struct PicState2 {
  68     /* 0 is master pic, 1 is slave pic */
  69     /* XXX: better separation between the two pics */
  70     PicState pics[2];
  71     qemu_irq parent_irq;
  72     void *irq_request_opaque;
  73 };
  74
  75 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  76 static int irq_level[16];
  77 #endif
  78 #ifdef DEBUG_IRQ_COUNT
  79 static uint64_t irq_count[16];
  80 #endif
  81 PicState2 *isa_pic;
  82
  83 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  84 static inline void pic_set_irq1(PicState *s, int irq, int level)
  85 {
  86     int mask;
  87     mask = 1 << irq;
  88     if (s->elcr & mask) {
  89         /* level triggered */
  90         if (level) {
  91             s->irr |= mask;
  92             s->last_irr |= mask;
  93         } else {
  94             s->irr &= ~mask;
  95             s->last_irr &= ~mask;
  96         }
  97     } else {
  98         /* edge triggered */
  99         if (level) {
 100             if ((s->last_irr & mask) == 0)
 101                 s->irr |= mask;
 102             s->last_irr |= mask;
 103         } else {
 104             s->last_irr &= ~mask;
 105         }
 106     }
 107 }
 108
 109 /* return the highest priority found in mask (highest = smallest
 110    number). Return 8 if no irq */
 111 static inline int get_priority(PicState *s, int mask)
 112 {
 113     int priority;
 114     if (mask == 0)
 115         return 8;
 116     priority = 0;
 117     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 118         priority++;
 119     return priority;
 120 }
 121
 122 /* return the pic wanted interrupt. return -1 if none */
 123 static int pic_get_irq(PicState *s)
 124 {
 125     int mask, cur_priority, priority;
 126
 127     mask = s->irr & ~s->imr;
 128     priority = get_priority(s, mask);
 129     if (priority == 8)
 130         return -1;
 131     /* compute current priority. If special fully nested mode on the
 132        master, the IRQ coming from the slave is not taken into account
 133        for the priority computation. */
 134     mask = s->isr;
 135     if (s->special_mask)
 136         mask &= ~s->imr;
 137     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 138         mask &= ~(1 << 2);
 139     cur_priority = get_priority(s, mask);
 140     if (priority < cur_priority) {
 141         /* higher priority found: an irq should be generated */
 142         return (priority + s->priority_add) & 7;
 143     } else {
 144         return -1;
 145     }
 146 }
 147
 148 /* raise irq to CPU if necessary. must be called every time the active
 149    irq may change */
 150 /* XXX: should not export it, but it is needed for an APIC kludge */
 151 void pic_update_irq(PicState2 *s)
 152 {
 153     int irq2, irq;
 154
 155     /* first look at slave pic */
 156     irq2 = pic_get_irq(&s->pics[1]);
 157     if (irq2 >= 0) {
 158         /* if irq request by slave pic, signal master PIC */
 159         pic_set_irq1(&s->pics[0], 2, 1);
 160         pic_set_irq1(&s->pics[0], 2, 0);
 161     }
 162     /* look at requested irq */
 163     irq = pic_get_irq(&s->pics[0]);
 164     if (irq >= 0) {
 165 #if defined(DEBUG_PIC)
 166         {
 167             int i;
 168             for(i = 0; i < 2; i++) {
 169                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 170                        i, s->pics[i].imr, s->pics[i].irr,
 171                        s->pics[i].priority_add);
 172
 173             }
 174         }
 175         printf("pic: cpu_interrupt\n");
 176 #endif
 177         qemu_irq_raise(s->parent_irq);
 178     }
 179
 180 /* all targets should do this rather than acking the IRQ in the cpu */
 181 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
 182     else {
 183         qemu_irq_lower(s->parent_irq);
 184     }
 185 #endif
 186 }
 187
 188 #ifdef DEBUG_IRQ_LATENCY
 189 int64_t irq_time[16];
 190 #endif
 191
 192 static void i8259_set_irq(void *opaque, int irq, int level)
 193 {
 194     PicState2 *s = opaque;
 195 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 196     if (level != irq_level[irq]) {
 197         DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
 198         irq_level[irq] = level;
 199 #ifdef DEBUG_IRQ_COUNT
 200         if (level == 1)
 201             irq_count[irq]++;
 202 #endif
 203     }
 204 #endif
 205 #ifdef DEBUG_IRQ_LATENCY
 206     if (level) {
 207         irq_time[irq] = qemu_get_clock(vm_clock);
 208     }
 209 #endif
 210     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 211     pic_update_irq(s);
 212 }
 213
 214 /* acknowledge interrupt 'irq' */
 215 static inline void pic_intack(PicState *s, int irq)
 216 {
 217     if (s->auto_eoi) {
 218         if (s->rotate_on_auto_eoi)
 219             s->priority_add = (irq + 1) & 7;
 220     } else {
 221         s->isr |= (1 << irq);
 222     }
 223
 224     /* We don't clear a level sensitive interrupt here */
 225     if (!(s->elcr & (1 << irq)))
 226         s->irr &= ~(1 << irq);
 227
 228 }
 229
 230 extern int time_drift_fix;
 231 extern int64_t timer_acks, timer_ints_to_push;
 232
 233 int pic_read_irq(PicState2 *s)
 234 {
 235     int irq, irq2, intno;
 236
 237     irq = pic_get_irq(&s->pics[0]);
 238     if (irq >= 0) {
 239
 240         pic_intack(&s->pics[0], irq);
 241 #ifdef TARGET_I386
 242         if (time_drift_fix && irq == 0) {
 243             timer_acks++;
 244             if (timer_ints_to_push > 0) {
 245                 timer_ints_to_push--;
 246                 /* simulate an edge irq0, like the one generated by i8254 */
 247                 pic_set_irq1(&s->pics[0], 0, 0);
 248                 pic_set_irq1(&s->pics[0], 0, 1);
 249             }
 250         }
 251 #endif
 252         if (irq == 2) {
 253             irq2 = pic_get_irq(&s->pics[1]);
 254             if (irq2 >= 0) {
 255                 pic_intack(&s->pics[1], irq2);
 256             } else {
 257                 /* spurious IRQ on slave controller */
 258                 irq2 = 7;
 259             }
 260             intno = s->pics[1].irq_base + irq2;
 261 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
 262             irq = irq2 + 8;
 263 #endif
 264         } else {
 265             intno = s->pics[0].irq_base + irq;
 266         }
 267     } else {
 268         /* spurious IRQ on host controller */
 269         irq = 7;
 270         intno = s->pics[0].irq_base + irq;
 271     }
 272     pic_update_irq(s);
 273
 274 #ifdef DEBUG_IRQ_LATENCY
 275     printf("IRQ%d latency=%0.3fus\n",
 276            irq,
 277            (double)(qemu_get_clock(vm_clock) -
 278                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 279 #endif
 280     DPRINTF("pic_interrupt: irq=%d\n", irq);
 281     return intno;
 282 }
 283
 284 static void pic_reset(void *opaque)
 285 {
 286     PicState *s = opaque;
 287
 288     s->last_irr = 0;
 289     s->irr = 0;
 290     s->imr = 0;
 291     s->isr = 0;
 292     s->priority_add = 0;
 293     s->irq_base = 0;
 294     s->read_reg_select = 0;
 295     s->poll = 0;
 296     s->special_mask = 0;
 297     s->init_state = 0;
 298     s->auto_eoi = 0;
 299     s->rotate_on_auto_eoi = 0;
 300     s->special_fully_nested_mode = 0;
 301     s->init4 = 0;
 302     s->single_mode = 0;
 303     /* Note: ELCR is not reset */
 304 }
 305
 306 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 307 {
 308     PicState *s = opaque;
 309     int priority, cmd, irq;
 310
 311     DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
 312     addr &= 1;
 313     if (addr == 0) {
 314         if (val & 0x10) {
 315             /* init */
 316             pic_reset(s);
 317             /* deassert a pending interrupt */
 318             qemu_irq_lower(s->pics_state->parent_irq);
 319             s->init_state = 1;
 320             s->init4 = val & 1;
 321             s->single_mode = val & 2;
 322             if (val & 0x08)
 323                 hw_error("level sensitive irq not supported");
 324         } else if (val & 0x08) {
 325             if (val & 0x04)
 326                 s->poll = 1;
 327             if (val & 0x02)
 328                 s->read_reg_select = val & 1;
 329             if (val & 0x40)
 330                 s->special_mask = (val >> 5) & 1;
 331         } else {
 332             cmd = val >> 5;
 333             switch(cmd) {
 334             case 0:
 335             case 4:
 336                 s->rotate_on_auto_eoi = cmd >> 2;
 337                 break;
 338             case 1: /* end of interrupt */
 339             case 5:
 340                 priority = get_priority(s, s->isr);
 341                 if (priority != 8) {
 342                     irq = (priority + s->priority_add) & 7;
 343                     s->isr &= ~(1 << irq);
 344                     if (cmd == 5)
 345                         s->priority_add = (irq + 1) & 7;
 346                     pic_update_irq(s->pics_state);
 347                 }
 348                 break;
 349             case 3:
 350                 irq = val & 7;
 351                 s->isr &= ~(1 << irq);
 352                 pic_update_irq(s->pics_state);
 353                 break;
 354             case 6:
 355                 s->priority_add = (val + 1) & 7;
 356                 pic_update_irq(s->pics_state);
 357                 break;
 358             case 7:
 359                 irq = val & 7;
 360                 s->isr &= ~(1 << irq);
 361                 s->priority_add = (irq + 1) & 7;
 362                 pic_update_irq(s->pics_state);
 363                 break;
 364             default:
 365                 /* no operation */
 366                 break;
 367             }
 368         }
 369     } else {
 370         switch(s->init_state) {
 371         case 0:
 372             /* normal mode */
 373             s->imr = val;
 374             pic_update_irq(s->pics_state);
 375             break;
 376         case 1:
 377             s->irq_base = val & 0xf8;
 378             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 379             break;
 380         case 2:
 381             if (s->init4) {
 382                 s->init_state = 3;
 383             } else {
 384                 s->init_state = 0;
 385             }
 386             break;
 387         case 3:
 388             s->special_fully_nested_mode = (val >> 4) & 1;
 389             s->auto_eoi = (val >> 1) & 1;
 390             s->init_state = 0;
 391             break;
 392         }
 393     }
 394 }
 395
 396 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 397 {
 398     int ret;
 399
 400     ret = pic_get_irq(s);
 401     if (ret >= 0) {
 402         if (addr1 >> 7) {
 403             s->pics_state->pics[0].isr &= ~(1 << 2);
 404             s->pics_state->pics[0].irr &= ~(1 << 2);
 405         }
 406         s->irr &= ~(1 << ret);
 407         s->isr &= ~(1 << ret);
 408         if (addr1 >> 7 || ret != 2)
 409             pic_update_irq(s->pics_state);
 410     } else {
 411         ret = 0x07;
 412         pic_update_irq(s->pics_state);
 413     }
 414
 415     return ret;
 416 }
 417
 418 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 419 {
 420     PicState *s = opaque;
 421     unsigned int addr;
 422     int ret;
 423
 424     addr = addr1;
 425     addr &= 1;
 426     if (s->poll) {
 427         ret = pic_poll_read(s, addr1);
 428         s->poll = 0;
 429     } else {
 430         if (addr == 0) {
 431             if (s->read_reg_select)
 432                 ret = s->isr;
 433             else
 434                 ret = s->irr;
 435         } else {
 436             ret = s->imr;
 437         }
 438     }
 439     DPRINTF("read: addr=0x%02x val=0x%02x\n", addr1, ret);
 440     return ret;
 441 }
 442
 443 /* memory mapped interrupt status */
 444 /* XXX: may be the same than pic_read_irq() */
 445 uint32_t pic_intack_read(PicState2 *s)
 446 {
 447     int ret;
 448
 449     ret = pic_poll_read(&s->pics[0], 0x00);
 450     if (ret == 2)
 451         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 452     /* Prepare for ISR read */
 453     s->pics[0].read_reg_select = 1;
 454
 455     return ret;
 456 }
 457
 458 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 459 {
 460     PicState *s = opaque;
 461     s->elcr = val & s->elcr_mask;
 462 }
 463
 464 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 465 {
 466     PicState *s = opaque;
 467     return s->elcr;
 468 }
 469
 470 static void kvm_kernel_pic_save_to_user(PicState *s);
 471 static int kvm_kernel_pic_load_from_user(PicState *s);
 472
 473 static void pic_pre_save(void *opaque)
 474 {
 475     PicState *s = opaque;
 476
 477     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 478         kvm_kernel_pic_save_to_user(s);
 479     }
 480 }
 481
 482 static int pic_post_load(void *opaque, int version_id)
 483 {
 484     PicState *s = opaque;
 485
 486     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 487         kvm_kernel_pic_load_from_user(s);
 488     }
 489     return 0;
 490 }
 491
 492 static const VMStateDescription vmstate_pic = {
 493     .name = "i8259",
 494     .version_id = 1,
 495     .pre_save = pic_pre_save,
 496     .post_load = pic_post_load,
 497     .minimum_version_id = 1,
 498     .minimum_version_id_old = 1,
 499     .fields      = (VMStateField []) {
 500         VMSTATE_UINT8(last_irr, PicState),
 501         VMSTATE_UINT8(irr, PicState),
 502         VMSTATE_UINT8(imr, PicState),
 503         VMSTATE_UINT8(isr, PicState),
 504         VMSTATE_UINT8(priority_add, PicState),
 505         VMSTATE_UINT8(irq_base, PicState),
 506         VMSTATE_UINT8(read_reg_select, PicState),
 507         VMSTATE_UINT8(poll, PicState),
 508         VMSTATE_UINT8(special_mask, PicState),
 509         VMSTATE_UINT8(init_state, PicState),
 510         VMSTATE_UINT8(auto_eoi, PicState),
 511         VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
 512         VMSTATE_UINT8(special_fully_nested_mode, PicState),
 513         VMSTATE_UINT8(init4, PicState),
 514         VMSTATE_UINT8(single_mode, PicState),
 515         VMSTATE_UINT8(elcr, PicState),
 516         VMSTATE_END_OF_LIST()
 517     }
 518 };
 519
 520 /* XXX: add generic master/slave system */
 521 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 522 {
 523     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 524     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 525     if (elcr_addr >= 0) {
 526         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 527         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 528     }
 529     vmstate_register(NULL, io_addr, &vmstate_pic, s);
 530     qemu_register_reset(pic_reset, s);
 531 }
 532
 533 void pic_info(Monitor *mon)
 534 {
 535     int i;
 536     PicState *s;
 537
 538     if (!isa_pic)
 539         return;
 540
 541     for(i=0;i<2;i++) {
 542         s = &isa_pic->pics[i];
 543         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 544                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 545                        i, s->irr, s->imr, s->isr, s->priority_add,
 546                        s->irq_base, s->read_reg_select, s->elcr,
 547                        s->special_fully_nested_mode);
 548     }
 549 }
 550
 551 void irq_info(Monitor *mon)
 552 {
 553 #ifndef DEBUG_IRQ_COUNT
 554     monitor_printf(mon, "irq statistic code not compiled.\n");
 555 #else
 556     int i;
 557     int64_t count;
 558
 559     monitor_printf(mon, "IRQ statistics:\n");
 560     for (i = 0; i < 16; i++) {
 561         count = irq_count[i];
 562         if (count > 0)
 563             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 564     }
 565 #endif
 566 }
 567
 568 qemu_irq *i8259_init(qemu_irq parent_irq)
 569 {
 570     PicState2 *s;
 571
 572     s = qemu_mallocz(sizeof(PicState2));
 573     pic_init1(0x20, 0x4d0, &s->pics[0]);
 574     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 575     s->pics[0].elcr_mask = 0xf8;
 576     s->pics[1].elcr_mask = 0xde;
 577     s->parent_irq = parent_irq;
 578     s->pics[0].pics_state = s;
 579     s->pics[1].pics_state = s;
 580     isa_pic = s;
 581     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 582 }
 583
 584 static void kvm_kernel_pic_save_to_user(PicState *s)
 585 {
 586 #ifdef KVM_CAP_IRQCHIP
 587     struct kvm_irqchip chip;
 588     struct kvm_pic_state *kpic;
 589
 590     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 591                    KVM_IRQCHIP_PIC_MASTER :
 592                    KVM_IRQCHIP_PIC_SLAVE;
 593     kvm_get_irqchip(kvm_context, &chip);
 594     kpic = &chip.chip.pic;
 595
 596     s->last_irr = kpic->last_irr;
 597     s->irr = kpic->irr;
 598     s->imr = kpic->imr;
 599     s->isr = kpic->isr;
 600     s->priority_add = kpic->priority_add;
 601     s->irq_base = kpic->irq_base;
 602     s->read_reg_select = kpic->read_reg_select;
 603     s->poll = kpic->poll;
 604     s->special_mask = kpic->special_mask;
 605     s->init_state = kpic->init_state;
 606     s->auto_eoi = kpic->auto_eoi;
 607     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 608     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 609     s->init4 = kpic->init4;
 610     s->elcr = kpic->elcr;
 611     s->elcr_mask = kpic->elcr_mask;
 612 #endif
 613 }
 614
 615 static int kvm_kernel_pic_load_from_user(PicState *s)
 616 {
 617 #ifdef KVM_CAP_IRQCHIP
 618     struct kvm_irqchip chip;
 619     struct kvm_pic_state *kpic;
 620
 621     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 622                    KVM_IRQCHIP_PIC_MASTER :
 623                    KVM_IRQCHIP_PIC_SLAVE;
 624     kpic = &chip.chip.pic;
 625
 626     kpic->last_irr = s->last_irr;
 627     kpic->irr = s->irr;
 628     kpic->imr = s->imr;
 629     kpic->isr = s->isr;
 630     kpic->priority_add = s->priority_add;
 631     kpic->irq_base = s->irq_base;
 632     kpic->read_reg_select = s->read_reg_select;
 633     kpic->poll = s->poll;
 634     kpic->special_mask = s->special_mask;
 635     kpic->init_state = s->init_state;
 636     kpic->auto_eoi = s->auto_eoi;
 637     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 638     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 639     kpic->init4 = s->init4;
 640     kpic->elcr = s->elcr;
 641     kpic->elcr_mask = s->elcr_mask;
 642
 643     kvm_set_irqchip(kvm_context, &chip);
 644 #endif
 645     return 0;
 646 }
 647
 648 #ifdef KVM_CAP_IRQCHIP
 649 static void kvm_i8259_set_irq(void *opaque, int irq, int level)
 650 {
 651     int pic_ret;
 652     if (kvm_set_irq(irq, level, &pic_ret)) {
 653         if (pic_ret != 0)
 654             apic_set_irq_delivered();
 655         return;
 656     }
 657 }
 658
 659 static void kvm_pic_init1(int io_addr, PicState *s)
 660 {
 661     vmstate_register(NULL, io_addr, &vmstate_pic, s);
 662     qemu_register_reset(pic_reset, s);
 663 }
 664
 665 qemu_irq *kvm_i8259_init(qemu_irq parent_irq)
 666 {
 667     PicState2 *s;
 668
 669     s = qemu_mallocz(sizeof(PicState2));
 670
 671     kvm_pic_init1(0x20, &s->pics[0]);
 672     kvm_pic_init1(0xa0, &s->pics[1]);
 673     s->parent_irq = parent_irq;
 674     s->pics[0].pics_state = s;
 675     s->pics[1].pics_state = s;
 676     isa_pic = s;
 677     return qemu_allocate_irqs(kvm_i8259_set_irq, s, 24);
 678 }
 679 #endif
 680
 681
 682