gdbstub.c

   1 /*
   2  * gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "qemu-common.h"
  21 #ifdef CONFIG_USER_ONLY
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <stdarg.h>
  25 #include <string.h>
  26 #include <errno.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "qemu.h"
  31 #else
  32 #include "monitor.h"
  33 #include "qemu-char.h"
  34 #include "sysemu.h"
  35 #include "gdbstub.h"
  36 #endif
  37 #include "qemu-kvm.h"
  38
  39 #define MAX_PACKET_LENGTH 4096
  40
  41 #include "qemu_socket.h"
  42 #include "kvm.h"
  43
  44
  45 enum {
  46     GDB_SIGNAL_0 = 0,
  47     GDB_SIGNAL_INT = 2,
  48     GDB_SIGNAL_TRAP = 5,
  49     GDB_SIGNAL_UNKNOWN = 143
  50 };
  51
  52 #ifdef CONFIG_USER_ONLY
  53
  54 /* Map target signal numbers to GDB protocol signal numbers and vice
  55  * versa.  For user emulation's currently supported systems, we can
  56  * assume most signals are defined.
  57  */
  58
  59 static int gdb_signal_table[] = {
  60     0,
  61     TARGET_SIGHUP,
  62     TARGET_SIGINT,
  63     TARGET_SIGQUIT,
  64     TARGET_SIGILL,
  65     TARGET_SIGTRAP,
  66     TARGET_SIGABRT,
  67     -1, /* SIGEMT */
  68     TARGET_SIGFPE,
  69     TARGET_SIGKILL,
  70     TARGET_SIGBUS,
  71     TARGET_SIGSEGV,
  72     TARGET_SIGSYS,
  73     TARGET_SIGPIPE,
  74     TARGET_SIGALRM,
  75     TARGET_SIGTERM,
  76     TARGET_SIGURG,
  77     TARGET_SIGSTOP,
  78     TARGET_SIGTSTP,
  79     TARGET_SIGCONT,
  80     TARGET_SIGCHLD,
  81     TARGET_SIGTTIN,
  82     TARGET_SIGTTOU,
  83     TARGET_SIGIO,
  84     TARGET_SIGXCPU,
  85     TARGET_SIGXFSZ,
  86     TARGET_SIGVTALRM,
  87     TARGET_SIGPROF,
  88     TARGET_SIGWINCH,
  89     -1, /* SIGLOST */
  90     TARGET_SIGUSR1,
  91     TARGET_SIGUSR2,
  92 #ifdef TARGET_SIGPWR
  93     TARGET_SIGPWR,
  94 #else
  95     -1,
  96 #endif
  97     -1, /* SIGPOLL */
  98     -1,
  99     -1,
 100     -1,
 101     -1,
 102     -1,
 103     -1,
 104     -1,
 105     -1,
 106     -1,
 107     -1,
 108     -1,
 109 #ifdef __SIGRTMIN
 110     __SIGRTMIN + 1,
 111     __SIGRTMIN + 2,
 112     __SIGRTMIN + 3,
 113     __SIGRTMIN + 4,
 114     __SIGRTMIN + 5,
 115     __SIGRTMIN + 6,
 116     __SIGRTMIN + 7,
 117     __SIGRTMIN + 8,
 118     __SIGRTMIN + 9,
 119     __SIGRTMIN + 10,
 120     __SIGRTMIN + 11,
 121     __SIGRTMIN + 12,
 122     __SIGRTMIN + 13,
 123     __SIGRTMIN + 14,
 124     __SIGRTMIN + 15,
 125     __SIGRTMIN + 16,
 126     __SIGRTMIN + 17,
 127     __SIGRTMIN + 18,
 128     __SIGRTMIN + 19,
 129     __SIGRTMIN + 20,
 130     __SIGRTMIN + 21,
 131     __SIGRTMIN + 22,
 132     __SIGRTMIN + 23,
 133     __SIGRTMIN + 24,
 134     __SIGRTMIN + 25,
 135     __SIGRTMIN + 26,
 136     __SIGRTMIN + 27,
 137     __SIGRTMIN + 28,
 138     __SIGRTMIN + 29,
 139     __SIGRTMIN + 30,
 140     __SIGRTMIN + 31,
 141     -1, /* SIGCANCEL */
 142     __SIGRTMIN,
 143     __SIGRTMIN + 32,
 144     __SIGRTMIN + 33,
 145     __SIGRTMIN + 34,
 146     __SIGRTMIN + 35,
 147     __SIGRTMIN + 36,
 148     __SIGRTMIN + 37,
 149     __SIGRTMIN + 38,
 150     __SIGRTMIN + 39,
 151     __SIGRTMIN + 40,
 152     __SIGRTMIN + 41,
 153     __SIGRTMIN + 42,
 154     __SIGRTMIN + 43,
 155     __SIGRTMIN + 44,
 156     __SIGRTMIN + 45,
 157     __SIGRTMIN + 46,
 158     __SIGRTMIN + 47,
 159     __SIGRTMIN + 48,
 160     __SIGRTMIN + 49,
 161     __SIGRTMIN + 50,
 162     __SIGRTMIN + 51,
 163     __SIGRTMIN + 52,
 164     __SIGRTMIN + 53,
 165     __SIGRTMIN + 54,
 166     __SIGRTMIN + 55,
 167     __SIGRTMIN + 56,
 168     __SIGRTMIN + 57,
 169     __SIGRTMIN + 58,
 170     __SIGRTMIN + 59,
 171     __SIGRTMIN + 60,
 172     __SIGRTMIN + 61,
 173     __SIGRTMIN + 62,
 174     __SIGRTMIN + 63,
 175     __SIGRTMIN + 64,
 176     __SIGRTMIN + 65,
 177     __SIGRTMIN + 66,
 178     __SIGRTMIN + 67,
 179     __SIGRTMIN + 68,
 180     __SIGRTMIN + 69,
 181     __SIGRTMIN + 70,
 182     __SIGRTMIN + 71,
 183     __SIGRTMIN + 72,
 184     __SIGRTMIN + 73,
 185     __SIGRTMIN + 74,
 186     __SIGRTMIN + 75,
 187     __SIGRTMIN + 76,
 188     __SIGRTMIN + 77,
 189     __SIGRTMIN + 78,
 190     __SIGRTMIN + 79,
 191     __SIGRTMIN + 80,
 192     __SIGRTMIN + 81,
 193     __SIGRTMIN + 82,
 194     __SIGRTMIN + 83,
 195     __SIGRTMIN + 84,
 196     __SIGRTMIN + 85,
 197     __SIGRTMIN + 86,
 198     __SIGRTMIN + 87,
 199     __SIGRTMIN + 88,
 200     __SIGRTMIN + 89,
 201     __SIGRTMIN + 90,
 202     __SIGRTMIN + 91,
 203     __SIGRTMIN + 92,
 204     __SIGRTMIN + 93,
 205     __SIGRTMIN + 94,
 206     __SIGRTMIN + 95,
 207     -1, /* SIGINFO */
 208     -1, /* UNKNOWN */
 209     -1, /* DEFAULT */
 210     -1,
 211     -1,
 212     -1,
 213     -1,
 214     -1,
 215     -1
 216 #endif
 217 };
 218 #else
 219 /* In system mode we only need SIGINT and SIGTRAP; other signals
 220    are not yet supported.  */
 221
 222 enum {
 223     TARGET_SIGINT = 2,
 224     TARGET_SIGTRAP = 5
 225 };
 226
 227 static int gdb_signal_table[] = {
 228     -1,
 229     -1,
 230     TARGET_SIGINT,
 231     -1,
 232     -1,
 233     TARGET_SIGTRAP
 234 };
 235 #endif
 236
 237 #ifdef CONFIG_USER_ONLY
 238 static int target_signal_to_gdb (int sig)
 239 {
 240     int i;
 241     for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
 242         if (gdb_signal_table[i] == sig)
 243             return i;
 244     return GDB_SIGNAL_UNKNOWN;
 245 }
 246 #endif
 247
 248 static int gdb_signal_to_target (int sig)
 249 {
 250     if (sig < ARRAY_SIZE (gdb_signal_table))
 251         return gdb_signal_table[sig];
 252     else
 253         return -1;
 254 }
 255
 256 //#define DEBUG_GDB
 257
 258 typedef struct GDBRegisterState {
 259     int base_reg;
 260     int num_regs;
 261     gdb_reg_cb get_reg;
 262     gdb_reg_cb set_reg;
 263     const char *xml;
 264     struct GDBRegisterState *next;
 265 } GDBRegisterState;
 266
 267 enum RSState {
 268     RS_INACTIVE,
 269     RS_IDLE,
 270     RS_GETLINE,
 271     RS_CHKSUM1,
 272     RS_CHKSUM2,
 273     RS_SYSCALL,
 274 };
 275 typedef struct GDBState {
 276     CPUState *c_cpu; /* current CPU for step/continue ops */
 277     CPUState *g_cpu; /* current CPU for other ops */
 278     CPUState *query_cpu; /* for q{f|s}ThreadInfo */
 279     enum RSState state; /* parsing state */
 280     char line_buf[MAX_PACKET_LENGTH];
 281     int line_buf_index;
 282     int line_csum;
 283     uint8_t last_packet[MAX_PACKET_LENGTH + 4];
 284     int last_packet_len;
 285     int signal;
 286 #ifdef CONFIG_USER_ONLY
 287     int fd;
 288     int running_state;
 289 #else
 290     CharDriverState *chr;
 291     CharDriverState *mon_chr;
 292 #endif
 293 } GDBState;
 294
 295 /* By default use no IRQs and no timers while single stepping so as to
 296  * make single stepping like an ICE HW step.
 297  */
 298 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
 299
 300 static GDBState *gdbserver_state;
 301
 302 /* This is an ugly hack to cope with both new and old gdb.
 303    If gdb sends qXfer:features:read then assume we're talking to a newish
 304    gdb that understands target descriptions.  */
 305 static int gdb_has_xml;
 306
 307 #ifdef CONFIG_USER_ONLY
 308 /* XXX: This is not thread safe.  Do we care?  */
 309 static int gdbserver_fd = -1;
 310
 311 static int get_char(GDBState *s)
 312 {
 313     uint8_t ch;
 314     int ret;
 315
 316     for(;;) {
 317         ret = recv(s->fd, &ch, 1, 0);
 318         if (ret < 0) {
 319             if (errno == ECONNRESET)
 320                 s->fd = -1;
 321             if (errno != EINTR && errno != EAGAIN)
 322                 return -1;
 323         } else if (ret == 0) {
 324             close(s->fd);
 325             s->fd = -1;
 326             return -1;
 327         } else {
 328             break;
 329         }
 330     }
 331     return ch;
 332 }
 333 #endif
 334
 335 static gdb_syscall_complete_cb gdb_current_syscall_cb;
 336
 337 static enum {
 338     GDB_SYS_UNKNOWN,
 339     GDB_SYS_ENABLED,
 340     GDB_SYS_DISABLED,
 341 } gdb_syscall_mode;
 342
 343 /* If gdb is connected when the first semihosting syscall occurs then use
 344    remote gdb syscalls.  Otherwise use native file IO.  */
 345 int use_gdb_syscalls(void)
 346 {
 347     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
 348         gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
 349                                             : GDB_SYS_DISABLED);
 350     }
 351     return gdb_syscall_mode == GDB_SYS_ENABLED;
 352 }
 353
 354 /* Resume execution.  */
 355 static inline void gdb_continue(GDBState *s)
 356 {
 357 #ifdef CONFIG_USER_ONLY
 358     s->running_state = 1;
 359 #else
 360     vm_start();
 361 #endif
 362 }
 363
 364 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
 365 {
 366 #ifdef CONFIG_USER_ONLY
 367     int ret;
 368
 369     while (len > 0) {
 370         ret = send(s->fd, buf, len, 0);
 371         if (ret < 0) {
 372             if (errno != EINTR && errno != EAGAIN)
 373                 return;
 374         } else {
 375             buf += ret;
 376             len -= ret;
 377         }
 378     }
 379 #else
 380     qemu_chr_write(s->chr, buf, len);
 381 #endif
 382 }
 383
 384 static inline int fromhex(int v)
 385 {
 386     if (v >= '0' && v <= '9')
 387         return v - '0';
 388     else if (v >= 'A' && v <= 'F')
 389         return v - 'A' + 10;
 390     else if (v >= 'a' && v <= 'f')
 391         return v - 'a' + 10;
 392     else
 393         return 0;
 394 }
 395
 396 static inline int tohex(int v)
 397 {
 398     if (v < 10)
 399         return v + '0';
 400     else
 401         return v - 10 + 'a';
 402 }
 403
 404 static void memtohex(char *buf, const uint8_t *mem, int len)
 405 {
 406     int i, c;
 407     char *q;
 408     q = buf;
 409     for(i = 0; i < len; i++) {
 410         c = mem[i];
 411         *q++ = tohex(c >> 4);
 412         *q++ = tohex(c & 0xf);
 413     }
 414     *q = '\0';
 415 }
 416
 417 static void hextomem(uint8_t *mem, const char *buf, int len)
 418 {
 419     int i;
 420
 421     for(i = 0; i < len; i++) {
 422         mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
 423         buf += 2;
 424     }
 425 }
 426
 427 /* return -1 if error, 0 if OK */
 428 static int put_packet_binary(GDBState *s, const char *buf, int len)
 429 {
 430     int csum, i;
 431     uint8_t *p;
 432
 433     for(;;) {
 434         p = s->last_packet;
 435         *(p++) = '$';
 436         memcpy(p, buf, len);
 437         p += len;
 438         csum = 0;
 439         for(i = 0; i < len; i++) {
 440             csum += buf[i];
 441         }
 442         *(p++) = '#';
 443         *(p++) = tohex((csum >> 4) & 0xf);
 444         *(p++) = tohex((csum) & 0xf);
 445
 446         s->last_packet_len = p - s->last_packet;
 447         put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
 448
 449 #ifdef CONFIG_USER_ONLY
 450         i = get_char(s);
 451         if (i < 0)
 452             return -1;
 453         if (i == '+')
 454             break;
 455 #else
 456         break;
 457 #endif
 458     }
 459     return 0;
 460 }
 461
 462 /* return -1 if error, 0 if OK */
 463 static int put_packet(GDBState *s, const char *buf)
 464 {
 465 #ifdef DEBUG_GDB
 466     printf("reply='%s'\n", buf);
 467 #endif
 468
 469     return put_packet_binary(s, buf, strlen(buf));
 470 }
 471
 472 /* The GDB remote protocol transfers values in target byte order.  This means
 473    we can use the raw memory access routines to access the value buffer.
 474    Conveniently, these also handle the case where the buffer is mis-aligned.
 475  */
 476 #define GET_REG8(val) do { \
 477     stb_p(mem_buf, val); \
 478     return 1; \
 479     } while(0)
 480 #define GET_REG16(val) do { \
 481     stw_p(mem_buf, val); \
 482     return 2; \
 483     } while(0)
 484 #define GET_REG32(val) do { \
 485     stl_p(mem_buf, val); \
 486     return 4; \
 487     } while(0)
 488 #define GET_REG64(val) do { \
 489     stq_p(mem_buf, val); \
 490     return 8; \
 491     } while(0)
 492
 493 #if TARGET_LONG_BITS == 64
 494 #define GET_REGL(val) GET_REG64(val)
 495 #define ldtul_p(addr) ldq_p(addr)
 496 #else
 497 #define GET_REGL(val) GET_REG32(val)
 498 #define ldtul_p(addr) ldl_p(addr)
 499 #endif
 500
 501 #if defined(TARGET_I386)
 502
 503 #ifdef TARGET_X86_64
 504 static const int gpr_map[16] = {
 505     R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
 506     8, 9, 10, 11, 12, 13, 14, 15
 507 };
 508 #else
 509 #define gpr_map gpr_map32
 510 #endif
 511 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 512
 513 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
 514
 515 #define IDX_IP_REG      CPU_NB_REGS
 516 #define IDX_FLAGS_REG   (IDX_IP_REG + 1)
 517 #define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
 518 #define IDX_FP_REGS     (IDX_SEG_REGS + 6)
 519 #define IDX_XMM_REGS    (IDX_FP_REGS + 16)
 520 #define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)
 521
 522 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 523 {
 524     if (n < CPU_NB_REGS) {
 525         if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 526             GET_REG64(env->regs[gpr_map[n]]);
 527         } else if (n < CPU_NB_REGS32) {
 528             GET_REG32(env->regs[gpr_map32[n]]);
 529         }
 530     } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 531 #ifdef USE_X86LDOUBLE
 532         /* FIXME: byteswap float values - after fixing fpregs layout. */
 533         memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
 534 #else
 535         memset(mem_buf, 0, 10);
 536 #endif
 537         return 10;
 538     } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 539         n -= IDX_XMM_REGS;
 540         if (n < CPU_NB_REGS32 ||
 541             (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
 542             stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
 543             stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
 544             return 16;
 545         }
 546     } else {
 547         switch (n) {
 548         case IDX_IP_REG:
 549             if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 550                 GET_REG64(env->eip);
 551             } else {
 552                 GET_REG32(env->eip);
 553             }
 554         case IDX_FLAGS_REG: GET_REG32(env->eflags);
 555
 556         case IDX_SEG_REGS:     GET_REG32(env->segs[R_CS].selector);
 557         case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
 558         case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
 559         case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
 560         case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
 561         case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
 562
 563         case IDX_FP_REGS + 8:  GET_REG32(env->fpuc);
 564         case IDX_FP_REGS + 9:  GET_REG32((env->fpus & ~0x3800) |
 565                                          (env->fpstt & 0x7) << 11);
 566         case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
 567         case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
 568         case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
 569         case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
 570         case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
 571         case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
 572
 573         case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
 574         }
 575     }
 576     return 0;
 577 }
 578
 579 static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
 580 {
 581     uint16_t selector = ldl_p(mem_buf);
 582
 583     if (selector != env->segs[sreg].selector) {
 584 #if defined(CONFIG_USER_ONLY)
 585         cpu_x86_load_seg(env, sreg, selector);
 586 #else
 587         unsigned int limit, flags;
 588         target_ulong base;
 589
 590         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 591             base = selector << 4;
 592             limit = 0xffff;
 593             flags = 0;
 594         } else {
 595             if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
 596                 return 4;
 597         }
 598         cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
 599 #endif
 600     }
 601     return 4;
 602 }
 603
 604 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 605 {
 606     uint32_t tmp;
 607
 608     if (n < CPU_NB_REGS) {
 609         if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 610             env->regs[gpr_map[n]] = ldtul_p(mem_buf);
 611             return sizeof(target_ulong);
 612         } else if (n < CPU_NB_REGS32) {
 613             n = gpr_map32[n];
 614             env->regs[n] &= ~0xffffffffUL;
 615             env->regs[n] |= (uint32_t)ldl_p(mem_buf);
 616             return 4;
 617         }
 618     } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 619 #ifdef USE_X86LDOUBLE
 620         /* FIXME: byteswap float values - after fixing fpregs layout. */
 621         memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
 622 #endif
 623         return 10;
 624     } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 625         n -= IDX_XMM_REGS;
 626         if (n < CPU_NB_REGS32 ||
 627             (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
 628             env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
 629             env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
 630             return 16;
 631         }
 632     } else {
 633         switch (n) {
 634         case IDX_IP_REG:
 635             if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 636                 env->eip = ldq_p(mem_buf);
 637                 return 8;
 638             } else {
 639                 env->eip &= ~0xffffffffUL;
 640                 env->eip |= (uint32_t)ldl_p(mem_buf);
 641                 return 4;
 642             }
 643         case IDX_FLAGS_REG:
 644             env->eflags = ldl_p(mem_buf);
 645             return 4;
 646
 647         case IDX_SEG_REGS:     return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
 648         case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
 649         case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
 650         case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
 651         case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
 652         case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
 653
 654         case IDX_FP_REGS + 8:
 655             env->fpuc = ldl_p(mem_buf);
 656             return 4;
 657         case IDX_FP_REGS + 9:
 658             tmp = ldl_p(mem_buf);
 659             env->fpstt = (tmp >> 11) & 7;
 660             env->fpus = tmp & ~0x3800;
 661             return 4;
 662         case IDX_FP_REGS + 10: /* ftag */  return 4;
 663         case IDX_FP_REGS + 11: /* fiseg */ return 4;
 664         case IDX_FP_REGS + 12: /* fioff */ return 4;
 665         case IDX_FP_REGS + 13: /* foseg */ return 4;
 666         case IDX_FP_REGS + 14: /* fooff */ return 4;
 667         case IDX_FP_REGS + 15: /* fop */   return 4;
 668
 669         case IDX_MXCSR_REG:
 670             env->mxcsr = ldl_p(mem_buf);
 671             return 4;
 672         }
 673     }
 674     /* Unrecognised register.  */
 675     return 0;
 676 }
 677
 678 #elif defined (TARGET_PPC)
 679
 680 /* Old gdb always expects FP registers.  Newer (xml-aware) gdb only
 681    expects whatever the target description contains.  Due to a
 682    historical mishap the FP registers appear in between core integer
 683    regs and PC, MSR, CR, and so forth.  We hack round this by giving the
 684    FP regs zero size when talking to a newer gdb.  */
 685 #define NUM_CORE_REGS 71
 686 #if defined (TARGET_PPC64)
 687 #define GDB_CORE_XML "power64-core.xml"
 688 #else
 689 #define GDB_CORE_XML "power-core.xml"
 690 #endif
 691
 692 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 693 {
 694     if (n < 32) {
 695         /* gprs */
 696         GET_REGL(env->gpr[n]);
 697     } else if (n < 64) {
 698         /* fprs */
 699         if (gdb_has_xml)
 700             return 0;
 701         stfq_p(mem_buf, env->fpr[n-32]);
 702         return 8;
 703     } else {
 704         switch (n) {
 705         case 64: GET_REGL(env->nip);
 706         case 65: GET_REGL(env->msr);
 707         case 66:
 708             {
 709                 uint32_t cr = 0;
 710                 int i;
 711                 for (i = 0; i < 8; i++)
 712                     cr |= env->crf[i] << (32 - ((i + 1) * 4));
 713                 GET_REG32(cr);
 714             }
 715         case 67: GET_REGL(env->lr);
 716         case 68: GET_REGL(env->ctr);
 717         case 69: GET_REGL(env->xer);
 718         case 70:
 719             {
 720                 if (gdb_has_xml)
 721                     return 0;
 722                 GET_REG32(0); /* fpscr */
 723             }
 724         }
 725     }
 726     return 0;
 727 }
 728
 729 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 730 {
 731     if (n < 32) {
 732         /* gprs */
 733         env->gpr[n] = ldtul_p(mem_buf);
 734         return sizeof(target_ulong);
 735     } else if (n < 64) {
 736         /* fprs */
 737         if (gdb_has_xml)
 738             return 0;
 739         env->fpr[n-32] = ldfq_p(mem_buf);
 740         return 8;
 741     } else {
 742         switch (n) {
 743         case 64:
 744             env->nip = ldtul_p(mem_buf);
 745             return sizeof(target_ulong);
 746         case 65:
 747             ppc_store_msr(env, ldtul_p(mem_buf));
 748             return sizeof(target_ulong);
 749         case 66:
 750             {
 751                 uint32_t cr = ldl_p(mem_buf);
 752                 int i;
 753                 for (i = 0; i < 8; i++)
 754                     env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
 755                 return 4;
 756             }
 757         case 67:
 758             env->lr = ldtul_p(mem_buf);
 759             return sizeof(target_ulong);
 760         case 68:
 761             env->ctr = ldtul_p(mem_buf);
 762             return sizeof(target_ulong);
 763         case 69:
 764             env->xer = ldtul_p(mem_buf);
 765             return sizeof(target_ulong);
 766         case 70:
 767             /* fpscr */
 768             if (gdb_has_xml)
 769                 return 0;
 770             return 4;
 771         }
 772     }
 773     return 0;
 774 }
 775
 776 #elif defined (TARGET_SPARC)
 777
 778 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
 779 #define NUM_CORE_REGS 86
 780 #else
 781 #define NUM_CORE_REGS 72
 782 #endif
 783
 784 #ifdef TARGET_ABI32
 785 #define GET_REGA(val) GET_REG32(val)
 786 #else
 787 #define GET_REGA(val) GET_REGL(val)
 788 #endif
 789
 790 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 791 {
 792     if (n < 8) {
 793         /* g0..g7 */
 794         GET_REGA(env->gregs[n]);
 795     }
 796     if (n < 32) {
 797         /* register window */
 798         GET_REGA(env->regwptr[n - 8]);
 799     }
 800 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 801     if (n < 64) {
 802         /* fprs */
 803         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 804     }
 805     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 806     switch (n) {
 807     case 64: GET_REGA(env->y);
 808     case 65: GET_REGA(GET_PSR(env));
 809     case 66: GET_REGA(env->wim);
 810     case 67: GET_REGA(env->tbr);
 811     case 68: GET_REGA(env->pc);
 812     case 69: GET_REGA(env->npc);
 813     case 70: GET_REGA(env->fsr);
 814     case 71: GET_REGA(0); /* csr */
 815     default: GET_REGA(0);
 816     }
 817 #else
 818     if (n < 64) {
 819         /* f0-f31 */
 820         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 821     }
 822     if (n < 80) {
 823         /* f32-f62 (double width, even numbers only) */
 824         uint64_t val;
 825
 826         val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
 827         val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
 828         GET_REG64(val);
 829     }
 830     switch (n) {
 831     case 80: GET_REGL(env->pc);
 832     case 81: GET_REGL(env->npc);
 833     case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
 834                            ((env->asi & 0xff) << 24) |
 835                            ((env->pstate & 0xfff) << 8) |
 836                            GET_CWP64(env));
 837     case 83: GET_REGL(env->fsr);
 838     case 84: GET_REGL(env->fprs);
 839     case 85: GET_REGL(env->y);
 840     }
 841 #endif
 842     return 0;
 843 }
 844
 845 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 846 {
 847 #if defined(TARGET_ABI32)
 848     abi_ulong tmp;
 849
 850     tmp = ldl_p(mem_buf);
 851 #else
 852     target_ulong tmp;
 853
 854     tmp = ldtul_p(mem_buf);
 855 #endif
 856
 857     if (n < 8) {
 858         /* g0..g7 */
 859         env->gregs[n] = tmp;
 860     } else if (n < 32) {
 861         /* register window */
 862         env->regwptr[n - 8] = tmp;
 863     }
 864 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 865     else if (n < 64) {
 866         /* fprs */
 867         *((uint32_t *)&env->fpr[n - 32]) = tmp;
 868     } else {
 869         /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 870         switch (n) {
 871         case 64: env->y = tmp; break;
 872         case 65: PUT_PSR(env, tmp); break;
 873         case 66: env->wim = tmp; break;
 874         case 67: env->tbr = tmp; break;
 875         case 68: env->pc = tmp; break;
 876         case 69: env->npc = tmp; break;
 877         case 70: env->fsr = tmp; break;
 878         default: return 0;
 879         }
 880     }
 881     return 4;
 882 #else
 883     else if (n < 64) {
 884         /* f0-f31 */
 885         env->fpr[n] = ldfl_p(mem_buf);
 886         return 4;
 887     } else if (n < 80) {
 888         /* f32-f62 (double width, even numbers only) */
 889         *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
 890         *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
 891     } else {
 892         switch (n) {
 893         case 80: env->pc = tmp; break;
 894         case 81: env->npc = tmp; break;
 895         case 82:
 896             PUT_CCR(env, tmp >> 32);
 897             env->asi = (tmp >> 24) & 0xff;
 898             env->pstate = (tmp >> 8) & 0xfff;
 899             PUT_CWP64(env, tmp & 0xff);
 900             break;
 901         case 83: env->fsr = tmp; break;
 902         case 84: env->fprs = tmp; break;
 903         case 85: env->y = tmp; break;
 904         default: return 0;
 905         }
 906     }
 907     return 8;
 908 #endif
 909 }
 910 #elif defined (TARGET_ARM)
 911
 912 /* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
 913    whatever the target description contains.  Due to a historical mishap
 914    the FPA registers appear in between core integer regs and the CPSR.
 915    We hack round this by giving the FPA regs zero size when talking to a
 916    newer gdb.  */
 917 #define NUM_CORE_REGS 26
 918 #define GDB_CORE_XML "arm-core.xml"
 919
 920 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 921 {
 922     if (n < 16) {
 923         /* Core integer register.  */
 924         GET_REG32(env->regs[n]);
 925     }
 926     if (n < 24) {
 927         /* FPA registers.  */
 928         if (gdb_has_xml)
 929             return 0;
 930         memset(mem_buf, 0, 12);
 931         return 12;
 932     }
 933     switch (n) {
 934     case 24:
 935         /* FPA status register.  */
 936         if (gdb_has_xml)
 937             return 0;
 938         GET_REG32(0);
 939     case 25:
 940         /* CPSR */
 941         GET_REG32(cpsr_read(env));
 942     }
 943     /* Unknown register.  */
 944     return 0;
 945 }
 946
 947 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 948 {
 949     uint32_t tmp;
 950
 951     tmp = ldl_p(mem_buf);
 952
 953     /* Mask out low bit of PC to workaround gdb bugs.  This will probably
 954        cause problems if we ever implement the Jazelle DBX extensions.  */
 955     if (n == 15)
 956         tmp &= ~1;
 957
 958     if (n < 16) {
 959         /* Core integer register.  */
 960         env->regs[n] = tmp;
 961         return 4;
 962     }
 963     if (n < 24) { /* 16-23 */
 964         /* FPA registers (ignored).  */
 965         if (gdb_has_xml)
 966             return 0;
 967         return 12;
 968     }
 969     switch (n) {
 970     case 24:
 971         /* FPA status register (ignored).  */
 972         if (gdb_has_xml)
 973             return 0;
 974         return 4;
 975     case 25:
 976         /* CPSR */
 977         cpsr_write (env, tmp, 0xffffffff);
 978         return 4;
 979     }
 980     /* Unknown register.  */
 981     return 0;
 982 }
 983
 984 #elif defined (TARGET_M68K)
 985
 986 #define NUM_CORE_REGS 18
 987
 988 #define GDB_CORE_XML "cf-core.xml"
 989
 990 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 991 {
 992     if (n < 8) {
 993         /* D0-D7 */
 994         GET_REG32(env->dregs[n]);
 995     } else if (n < 16) {
 996         /* A0-A7 */
 997         GET_REG32(env->aregs[n - 8]);
 998     } else {
 999         switch (n) {
1000         case 16: GET_REG32(env->sr);
1001         case 17: GET_REG32(env->pc);
1002         }
1003     }
1004     /* FP registers not included here because they vary between
1005        ColdFire and m68k.  Use XML bits for these.  */
1006     return 0;
1007 }
1008
1009 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1010 {
1011     uint32_t tmp;
1012
1013     tmp = ldl_p(mem_buf);
1014
1015     if (n < 8) {
1016         /* D0-D7 */
1017         env->dregs[n] = tmp;
1018     } else if (n < 8) {
1019         /* A0-A7 */
1020         env->aregs[n - 8] = tmp;
1021     } else {
1022         switch (n) {
1023         case 16: env->sr = tmp; break;
1024         case 17: env->pc = tmp; break;
1025         default: return 0;
1026         }
1027     }
1028     return 4;
1029 }
1030 #elif defined (TARGET_MIPS)
1031
1032 #define NUM_CORE_REGS 73
1033
1034 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1035 {
1036     if (n < 32) {
1037         GET_REGL(env->active_tc.gpr[n]);
1038     }
1039     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1040         if (n >= 38 && n < 70) {
1041             if (env->CP0_Status & (1 << CP0St_FR))
1042                 GET_REGL(env->active_fpu.fpr[n - 38].d);
1043             else
1044                 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1045         }
1046         switch (n) {
1047         case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1048         case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1049         }
1050     }
1051     switch (n) {
1052     case 32: GET_REGL((int32_t)env->CP0_Status);
1053     case 33: GET_REGL(env->active_tc.LO[0]);
1054     case 34: GET_REGL(env->active_tc.HI[0]);
1055     case 35: GET_REGL(env->CP0_BadVAddr);
1056     case 36: GET_REGL((int32_t)env->CP0_Cause);
1057     case 37: GET_REGL(env->active_tc.PC);
1058     case 72: GET_REGL(0); /* fp */
1059     case 89: GET_REGL((int32_t)env->CP0_PRid);
1060     }
1061     if (n >= 73 && n <= 88) {
1062         /* 16 embedded regs.  */
1063         GET_REGL(0);
1064     }
1065
1066     return 0;
1067 }
1068
1069 /* convert MIPS rounding mode in FCR31 to IEEE library */
1070 static unsigned int ieee_rm[] =
1071   {
1072     float_round_nearest_even,
1073     float_round_to_zero,
1074     float_round_up,
1075     float_round_down
1076   };
1077 #define RESTORE_ROUNDING_MODE \
1078     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1079
1080 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1081 {
1082     target_ulong tmp;
1083
1084     tmp = ldtul_p(mem_buf);
1085
1086     if (n < 32) {
1087         env->active_tc.gpr[n] = tmp;
1088         return sizeof(target_ulong);
1089     }
1090     if (env->CP0_Config1 & (1 << CP0C1_FP)
1091             && n >= 38 && n < 73) {
1092         if (n < 70) {
1093             if (env->CP0_Status & (1 << CP0St_FR))
1094               env->active_fpu.fpr[n - 38].d = tmp;
1095             else
1096               env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1097         }
1098         switch (n) {
1099         case 70:
1100             env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1101             /* set rounding mode */
1102             RESTORE_ROUNDING_MODE;
1103 #ifndef CONFIG_SOFTFLOAT
1104             /* no floating point exception for native float */
1105             SET_FP_ENABLE(env->active_fpu.fcr31, 0);
1106 #endif
1107             break;
1108         case 71: env->active_fpu.fcr0 = tmp; break;
1109         }
1110         return sizeof(target_ulong);
1111     }
1112     switch (n) {
1113     case 32: env->CP0_Status = tmp; break;
1114     case 33: env->active_tc.LO[0] = tmp; break;
1115     case 34: env->active_tc.HI[0] = tmp; break;
1116     case 35: env->CP0_BadVAddr = tmp; break;
1117     case 36: env->CP0_Cause = tmp; break;
1118     case 37: env->active_tc.PC = tmp; break;
1119     case 72: /* fp, ignored */ break;
1120     default:
1121         if (n > 89)
1122             return 0;
1123         /* Other registers are readonly.  Ignore writes.  */
1124         break;
1125     }
1126
1127     return sizeof(target_ulong);
1128 }
1129 #elif defined (TARGET_SH4)
1130
1131 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1132 /* FIXME: We should use XML for this.  */
1133
1134 #define NUM_CORE_REGS 59
1135
1136 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1137 {
1138     if (n < 8) {
1139         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1140             GET_REGL(env->gregs[n + 16]);
1141         } else {
1142             GET_REGL(env->gregs[n]);
1143         }
1144     } else if (n < 16) {
1145         GET_REGL(env->gregs[n - 8]);
1146     } else if (n >= 25 && n < 41) {
1147         GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1148     } else if (n >= 43 && n < 51) {
1149         GET_REGL(env->gregs[n - 43]);
1150     } else if (n >= 51 && n < 59) {
1151         GET_REGL(env->gregs[n - (51 - 16)]);
1152     }
1153     switch (n) {
1154     case 16: GET_REGL(env->pc);
1155     case 17: GET_REGL(env->pr);
1156     case 18: GET_REGL(env->gbr);
1157     case 19: GET_REGL(env->vbr);
1158     case 20: GET_REGL(env->mach);
1159     case 21: GET_REGL(env->macl);
1160     case 22: GET_REGL(env->sr);
1161     case 23: GET_REGL(env->fpul);
1162     case 24: GET_REGL(env->fpscr);
1163     case 41: GET_REGL(env->ssr);
1164     case 42: GET_REGL(env->spc);
1165     }
1166
1167     return 0;
1168 }
1169
1170 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1171 {
1172     uint32_t tmp;
1173
1174     tmp = ldl_p(mem_buf);
1175
1176     if (n < 8) {
1177         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1178             env->gregs[n + 16] = tmp;
1179         } else {
1180             env->gregs[n] = tmp;
1181         }
1182         return 4;
1183     } else if (n < 16) {
1184         env->gregs[n - 8] = tmp;
1185         return 4;
1186     } else if (n >= 25 && n < 41) {
1187         env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1188     } else if (n >= 43 && n < 51) {
1189         env->gregs[n - 43] = tmp;
1190         return 4;
1191     } else if (n >= 51 && n < 59) {
1192         env->gregs[n - (51 - 16)] = tmp;
1193         return 4;
1194     }
1195     switch (n) {
1196     case 16: env->pc = tmp;
1197     case 17: env->pr = tmp;
1198     case 18: env->gbr = tmp;
1199     case 19: env->vbr = tmp;
1200     case 20: env->mach = tmp;
1201     case 21: env->macl = tmp;
1202     case 22: env->sr = tmp;
1203     case 23: env->fpul = tmp;
1204     case 24: env->fpscr = tmp;
1205     case 41: env->ssr = tmp;
1206     case 42: env->spc = tmp;
1207     default: return 0;
1208     }
1209
1210     return 4;
1211 }
1212 #elif defined (TARGET_MICROBLAZE)
1213
1214 #define NUM_CORE_REGS (32 + 5)
1215
1216 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1217 {
1218     if (n < 32) {
1219         GET_REG32(env->regs[n]);
1220     } else {
1221         GET_REG32(env->sregs[n - 32]);
1222     }
1223     return 0;
1224 }
1225
1226 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1227 {
1228     uint32_t tmp;
1229
1230     if (n > NUM_CORE_REGS)
1231         return 0;
1232
1233     tmp = ldl_p(mem_buf);
1234
1235     if (n < 32) {
1236         env->regs[n] = tmp;
1237     } else {
1238         env->sregs[n - 32] = tmp;
1239     }
1240     return 4;
1241 }
1242 #elif defined (TARGET_CRIS)
1243
1244 #define NUM_CORE_REGS 49
1245
1246 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1247 {
1248     uint8_t srs;
1249
1250     srs = env->pregs[PR_SRS];
1251     if (n < 16) {
1252         GET_REG32(env->regs[n]);
1253     }
1254
1255     if (n >= 21 && n < 32) {
1256         GET_REG32(env->pregs[n - 16]);
1257     }
1258     if (n >= 33 && n < 49) {
1259         GET_REG32(env->sregs[srs][n - 33]);
1260     }
1261     switch (n) {
1262     case 16: GET_REG8(env->pregs[0]);
1263     case 17: GET_REG8(env->pregs[1]);
1264     case 18: GET_REG32(env->pregs[2]);
1265     case 19: GET_REG8(srs);
1266     case 20: GET_REG16(env->pregs[4]);
1267     case 32: GET_REG32(env->pc);
1268     }
1269
1270     return 0;
1271 }
1272
1273 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1274 {
1275     uint32_t tmp;
1276
1277     if (n > 49)
1278         return 0;
1279
1280     tmp = ldl_p(mem_buf);
1281
1282     if (n < 16) {
1283         env->regs[n] = tmp;
1284     }
1285
1286     if (n >= 21 && n < 32) {
1287         env->pregs[n - 16] = tmp;
1288     }
1289
1290     /* FIXME: Should support function regs be writable?  */
1291     switch (n) {
1292     case 16: return 1;
1293     case 17: return 1;
1294     case 18: env->pregs[PR_PID] = tmp; break;
1295     case 19: return 1;
1296     case 20: return 2;
1297     case 32: env->pc = tmp; break;
1298     }
1299
1300     return 4;
1301 }
1302 #elif defined (TARGET_ALPHA)
1303
1304 #define NUM_CORE_REGS 65
1305
1306 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1307 {
1308     if (n < 31) {
1309        GET_REGL(env->ir[n]);
1310     }
1311     else if (n == 31) {
1312        GET_REGL(0);
1313     }
1314     else if (n<63) {
1315        uint64_t val;
1316
1317        val = *((uint64_t *)&env->fir[n-32]);
1318        GET_REGL(val);
1319     }
1320     else if (n==63) {
1321        GET_REGL(env->fpcr);
1322     }
1323     else if (n==64) {
1324        GET_REGL(env->pc);
1325     }
1326     else {
1327        GET_REGL(0);
1328     }
1329
1330     return 0;
1331 }
1332
1333 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1334 {
1335     target_ulong tmp;
1336     tmp = ldtul_p(mem_buf);
1337
1338     if (n < 31) {
1339         env->ir[n] = tmp;
1340     }
1341
1342     if (n > 31 && n < 63) {
1343         env->fir[n - 32] = ldfl_p(mem_buf);
1344     }
1345
1346     if (n == 64 ) {
1347        env->pc=tmp;
1348     }
1349
1350     return 8;
1351 }
1352 #elif defined (TARGET_S390X)
1353
1354 #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1355
1356 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1357 {
1358     switch (n) {
1359         case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
1360         case S390_PSWA_REGNUM: GET_REGL(env->psw.addr); break;
1361         case S390_R0_REGNUM ... S390_R15_REGNUM:
1362             GET_REGL(env->regs[n-S390_R0_REGNUM]); break;
1363         case S390_A0_REGNUM ... S390_A15_REGNUM:
1364             GET_REG32(env->aregs[n-S390_A0_REGNUM]); break;
1365         case S390_FPC_REGNUM: GET_REG32(env->fpc); break;
1366         case S390_F0_REGNUM ... S390_F15_REGNUM:
1367             /* XXX */
1368             break;
1369         case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
1370         case S390_CC_REGNUM: GET_REG32(env->cc); break;
1371     }
1372
1373     return 0;
1374 }
1375
1376 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1377 {
1378     target_ulong tmpl;
1379     uint32_t tmp32;
1380     int r = 8;
1381     tmpl = ldtul_p(mem_buf);
1382     tmp32 = ldl_p(mem_buf);
1383
1384     switch (n) {
1385         case S390_PSWM_REGNUM: env->psw.mask = tmpl; break;
1386         case S390_PSWA_REGNUM: env->psw.addr = tmpl; break;
1387         case S390_R0_REGNUM ... S390_R15_REGNUM:
1388             env->regs[n-S390_R0_REGNUM] = tmpl; break;
1389         case S390_A0_REGNUM ... S390_A15_REGNUM:
1390             env->aregs[n-S390_A0_REGNUM] = tmp32; r=4; break;
1391         case S390_FPC_REGNUM: env->fpc = tmp32; r=4; break;
1392         case S390_F0_REGNUM ... S390_F15_REGNUM:
1393             /* XXX */
1394             break;
1395         case S390_PC_REGNUM: env->psw.addr = tmpl; break;
1396         case S390_CC_REGNUM: env->cc = tmp32; r=4; break;
1397     }
1398
1399     return r;
1400 }
1401 #else
1402
1403 #define NUM_CORE_REGS 0
1404
1405 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1406 {
1407     return 0;
1408 }
1409
1410 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1411 {
1412     return 0;
1413 }
1414
1415 #endif
1416
1417 static int num_g_regs = NUM_CORE_REGS;
1418
1419 #ifdef GDB_CORE_XML
1420 /* Encode data using the encoding for 'x' packets.  */
1421 static int memtox(char *buf, const char *mem, int len)
1422 {
1423     char *p = buf;
1424     char c;
1425
1426     while (len--) {
1427         c = *(mem++);
1428         switch (c) {
1429         case '#': case '$': case '*': case '}':
1430             *(p++) = '}';
1431             *(p++) = c ^ 0x20;
1432             break;
1433         default:
1434             *(p++) = c;
1435             break;
1436         }
1437     }
1438     return p - buf;
1439 }
1440
1441 static const char *get_feature_xml(const char *p, const char **newp)
1442 {
1443     extern const char *const xml_builtin[][2];
1444     size_t len;
1445     int i;
1446     const char *name;
1447     static char target_xml[1024];
1448
1449     len = 0;
1450     while (p[len] && p[len] != ':')
1451         len++;
1452     *newp = p + len;
1453
1454     name = NULL;
1455     if (strncmp(p, "target.xml", len) == 0) {
1456         /* Generate the XML description for this CPU.  */
1457         if (!target_xml[0]) {
1458             GDBRegisterState *r;
1459
1460             snprintf(target_xml, sizeof(target_xml),
1461                      "<?xml version=\"1.0\"?>"
1462                      "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1463                      "<target>"
1464                      "<xi:include href=\"%s\"/>",
1465                      GDB_CORE_XML);
1466
1467             for (r = first_cpu->gdb_regs; r; r = r->next) {
1468                 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1469                 pstrcat(target_xml, sizeof(target_xml), r->xml);
1470                 pstrcat(target_xml, sizeof(target_xml), "\"/>");
1471             }
1472             pstrcat(target_xml, sizeof(target_xml), "</target>");
1473         }
1474         return target_xml;
1475     }
1476     for (i = 0; ; i++) {
1477         name = xml_builtin[i][0];
1478         if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1479             break;
1480     }
1481     return name ? xml_builtin[i][1] : NULL;
1482 }
1483 #endif
1484
1485 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1486 {
1487     GDBRegisterState *r;
1488
1489     if (reg < NUM_CORE_REGS)
1490         return cpu_gdb_read_register(env, mem_buf, reg);
1491
1492     for (r = env->gdb_regs; r; r = r->next) {
1493         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1494             return r->get_reg(env, mem_buf, reg - r->base_reg);
1495         }
1496     }
1497     return 0;
1498 }
1499
1500 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1501 {
1502     GDBRegisterState *r;
1503
1504     if (reg < NUM_CORE_REGS)
1505         return cpu_gdb_write_register(env, mem_buf, reg);
1506
1507     for (r = env->gdb_regs; r; r = r->next) {
1508         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1509             return r->set_reg(env, mem_buf, reg - r->base_reg);
1510         }
1511     }
1512     return 0;
1513 }
1514
1515 /* Register a supplemental set of CPU registers.  If g_pos is nonzero it
1516    specifies the first register number and these registers are included in
1517    a standard "g" packet.  Direction is relative to gdb, i.e. get_reg is
1518    gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1519  */
1520
1521 void gdb_register_coprocessor(CPUState * env,
1522                              gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1523                              int num_regs, const char *xml, int g_pos)
1524 {
1525     GDBRegisterState *s;
1526     GDBRegisterState **p;
1527     static int last_reg = NUM_CORE_REGS;
1528
1529     s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1530     s->base_reg = last_reg;
1531     s->num_regs = num_regs;
1532     s->get_reg = get_reg;
1533     s->set_reg = set_reg;
1534     s->xml = xml;
1535     p = &env->gdb_regs;
1536     while (*p) {
1537         /* Check for duplicates.  */
1538         if (strcmp((*p)->xml, xml) == 0)
1539             return;
1540         p = &(*p)->next;
1541     }
1542     /* Add to end of list.  */
1543     last_reg += num_regs;
1544     *p = s;
1545     if (g_pos) {
1546         if (g_pos != s->base_reg) {
1547             fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1548                     "Expected %d got %d\n", xml, g_pos, s->base_reg);
1549         } else {
1550             num_g_regs = last_reg;
1551         }
1552     }
1553 }
1554
1555 #ifndef CONFIG_USER_ONLY
1556 static const int xlat_gdb_type[] = {
1557     [GDB_WATCHPOINT_WRITE]  = BP_GDB | BP_MEM_WRITE,
1558     [GDB_WATCHPOINT_READ]   = BP_GDB | BP_MEM_READ,
1559     [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1560 };
1561 #endif
1562
1563 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1564 {
1565     CPUState *env;
1566     int err = 0;
1567
1568     if (kvm_enabled())
1569         return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1570
1571     switch (type) {
1572     case GDB_BREAKPOINT_SW:
1573     case GDB_BREAKPOINT_HW:
1574         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1575             err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1576             if (err)
1577                 break;
1578         }
1579         return err;
1580 #ifndef CONFIG_USER_ONLY
1581     case GDB_WATCHPOINT_WRITE:
1582     case GDB_WATCHPOINT_READ:
1583     case GDB_WATCHPOINT_ACCESS:
1584         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1585             err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1586                                         NULL);
1587             if (err)
1588                 break;
1589         }
1590         return err;
1591 #endif
1592     default:
1593         return -ENOSYS;
1594     }
1595 }
1596
1597 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1598 {
1599     CPUState *env;
1600     int err = 0;
1601
1602     if (kvm_enabled())
1603         return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1604
1605     switch (type) {
1606     case GDB_BREAKPOINT_SW:
1607     case GDB_BREAKPOINT_HW:
1608         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1609             err = cpu_breakpoint_remove(env, addr, BP_GDB);
1610             if (err)
1611                 break;
1612         }
1613         return err;
1614 #ifndef CONFIG_USER_ONLY
1615     case GDB_WATCHPOINT_WRITE:
1616     case GDB_WATCHPOINT_READ:
1617     case GDB_WATCHPOINT_ACCESS:
1618         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1619             err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1620             if (err)
1621                 break;
1622         }
1623         return err;
1624 #endif
1625     default:
1626         return -ENOSYS;
1627     }
1628 }
1629
1630 static void gdb_breakpoint_remove_all(void)
1631 {
1632     CPUState *env;
1633
1634     if (kvm_enabled()) {
1635         kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1636         return;
1637     }
1638
1639     for (env = first_cpu; env != NULL; env = env->next_cpu) {
1640         cpu_breakpoint_remove_all(env, BP_GDB);
1641 #ifndef CONFIG_USER_ONLY
1642         cpu_watchpoint_remove_all(env, BP_GDB);
1643 #endif
1644     }
1645 }
1646
1647 static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
1648 {
1649 #if defined(TARGET_I386)
1650     cpu_synchronize_state(s->c_cpu);
1651     s->c_cpu->eip = pc;
1652 #elif defined (TARGET_PPC)
1653     s->c_cpu->nip = pc;
1654 #elif defined (TARGET_SPARC)
1655     s->c_cpu->pc = pc;
1656     s->c_cpu->npc = pc + 4;
1657 #elif defined (TARGET_ARM)
1658     s->c_cpu->regs[15] = pc;
1659 #elif defined (TARGET_SH4)
1660     s->c_cpu->pc = pc;
1661 #elif defined (TARGET_MIPS)
1662     s->c_cpu->active_tc.PC = pc;
1663 #elif defined (TARGET_MICROBLAZE)
1664     s->c_cpu->sregs[SR_PC] = pc;
1665 #elif defined (TARGET_CRIS)
1666     s->c_cpu->pc = pc;
1667 #elif defined (TARGET_ALPHA)
1668     s->c_cpu->pc = pc;
1669 #elif defined (TARGET_S390X)
1670     cpu_synchronize_state(s->c_cpu);
1671     s->c_cpu->psw.addr = pc;
1672 #endif
1673 }
1674
1675 static inline int gdb_id(CPUState *env)
1676 {
1677 #if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1678     return env->host_tid;
1679 #else
1680     return env->cpu_index + 1;
1681 #endif
1682 }
1683
1684 static CPUState *find_cpu(uint32_t thread_id)
1685 {
1686     CPUState *env;
1687
1688     for (env = first_cpu; env != NULL; env = env->next_cpu) {
1689         if (gdb_id(env) == thread_id) {
1690             return env;
1691         }
1692     }
1693
1694     return NULL;
1695 }
1696
1697 static int gdb_handle_packet(GDBState *s, const char *line_buf)
1698 {
1699     CPUState *env;
1700     const char *p;
1701     uint32_t thread;
1702     int ch, reg_size, type, res;
1703     char buf[MAX_PACKET_LENGTH];
1704     uint8_t mem_buf[MAX_PACKET_LENGTH];
1705     uint8_t *registers;
1706     target_ulong addr, len;
1707
1708 #ifdef DEBUG_GDB
1709     printf("command='%s'\n", line_buf);
1710 #endif
1711     p = line_buf;
1712     ch = *p++;
1713     switch(ch) {
1714     case '?':
1715         /* TODO: Make this return the correct value for user-mode.  */
1716         snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1717                  gdb_id(s->c_cpu));
1718         put_packet(s, buf);
1719         /* Remove all the breakpoints when this query is issued,
1720          * because gdb is doing and initial connect and the state
1721          * should be cleaned up.
1722          */
1723         gdb_breakpoint_remove_all();
1724         break;
1725     case 'c':
1726         if (*p != '\0') {
1727             addr = strtoull(p, (char **)&p, 16);
1728             gdb_set_cpu_pc(s, addr);
1729         }
1730         s->signal = 0;
1731         gdb_continue(s);
1732         return RS_IDLE;
1733     case 'C':
1734         s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1735         if (s->signal == -1)
1736             s->signal = 0;
1737         gdb_continue(s);
1738         return RS_IDLE;
1739     case 'v':
1740         if (strncmp(p, "Cont", 4) == 0) {
1741             int res_signal, res_thread;
1742
1743             p += 4;
1744             if (*p == '?') {
1745                 put_packet(s, "vCont;c;C;s;S");
1746                 break;
1747             }
1748             res = 0;
1749             res_signal = 0;
1750             res_thread = 0;
1751             while (*p) {
1752                 int action, signal;
1753
1754                 if (*p++ != ';') {
1755                     res = 0;
1756                     break;
1757                 }
1758                 action = *p++;
1759                 signal = 0;
1760                 if (action == 'C' || action == 'S') {
1761                     signal = strtoul(p, (char **)&p, 16);
1762                 } else if (action != 'c' && action != 's') {
1763                     res = 0;
1764                     break;
1765                 }
1766                 thread = 0;
1767                 if (*p == ':') {
1768                     thread = strtoull(p+1, (char **)&p, 16);
1769                 }
1770                 action = tolower(action);
1771                 if (res == 0 || (res == 'c' && action == 's')) {
1772                     res = action;
1773                     res_signal = signal;
1774                     res_thread = thread;
1775                 }
1776             }
1777             if (res) {
1778                 if (res_thread != -1 && res_thread != 0) {
1779                     env = find_cpu(res_thread);
1780                     if (env == NULL) {
1781                         put_packet(s, "E22");
1782                         break;
1783                     }
1784                     s->c_cpu = env;
1785                 }
1786                 if (res == 's') {
1787                     cpu_single_step(s->c_cpu, sstep_flags);
1788                 }
1789                 s->signal = res_signal;
1790                 gdb_continue(s);
1791                 return RS_IDLE;
1792             }
1793             break;
1794         } else {
1795             goto unknown_command;
1796         }
1797     case 'k':
1798         /* Kill the target */
1799         fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1800         exit(0);
1801     case 'D':
1802         /* Detach packet */
1803         gdb_breakpoint_remove_all();
1804         gdb_continue(s);
1805         put_packet(s, "OK");
1806         break;
1807     case 's':
1808         if (*p != '\0') {
1809             addr = strtoull(p, (char **)&p, 16);
1810             gdb_set_cpu_pc(s, addr);
1811         }
1812         cpu_single_step(s->c_cpu, sstep_flags);
1813         gdb_continue(s);
1814         return RS_IDLE;
1815     case 'F':
1816         {
1817             target_ulong ret;
1818             target_ulong err;
1819
1820             ret = strtoull(p, (char **)&p, 16);
1821             if (*p == ',') {
1822                 p++;
1823                 err = strtoull(p, (char **)&p, 16);
1824             } else {
1825                 err = 0;
1826             }
1827             if (*p == ',')
1828                 p++;
1829             type = *p;
1830             if (gdb_current_syscall_cb)
1831                 gdb_current_syscall_cb(s->c_cpu, ret, err);
1832             if (type == 'C') {
1833                 put_packet(s, "T02");
1834             } else {
1835                 gdb_continue(s);
1836             }
1837         }
1838         break;
1839     case 'g':
1840         cpu_synchronize_state(s->g_cpu);
1841         len = 0;
1842         for (addr = 0; addr < num_g_regs; addr++) {
1843             reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
1844             len += reg_size;
1845         }
1846         memtohex(buf, mem_buf, len);
1847         put_packet(s, buf);
1848         break;
1849     case 'G':
1850         cpu_synchronize_state(s->g_cpu);
1851         registers = mem_buf;
1852         len = strlen(p) / 2;
1853         hextomem((uint8_t *)registers, p, len);
1854         for (addr = 0; addr < num_g_regs && len > 0; addr++) {
1855             reg_size = gdb_write_register(s->g_cpu, registers, addr);
1856             len -= reg_size;
1857             registers += reg_size;
1858         }
1859         put_packet(s, "OK");
1860         break;
1861     case 'm':
1862         addr = strtoull(p, (char **)&p, 16);
1863         if (*p == ',')
1864             p++;
1865         len = strtoull(p, NULL, 16);
1866         if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
1867             put_packet (s, "E14");
1868         } else {
1869             memtohex(buf, mem_buf, len);
1870             put_packet(s, buf);
1871         }
1872         break;
1873     case 'M':
1874         addr = strtoull(p, (char **)&p, 16);
1875         if (*p == ',')
1876             p++;
1877         len = strtoull(p, (char **)&p, 16);
1878         if (*p == ':')
1879             p++;
1880         hextomem(mem_buf, p, len);
1881         if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
1882             put_packet(s, "E14");
1883         else
1884             put_packet(s, "OK");
1885         break;
1886     case 'p':
1887         /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1888            This works, but can be very slow.  Anything new enough to
1889            understand XML also knows how to use this properly.  */
1890         if (!gdb_has_xml)
1891             goto unknown_command;
1892         addr = strtoull(p, (char **)&p, 16);
1893         reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
1894         if (reg_size) {
1895             memtohex(buf, mem_buf, reg_size);
1896             put_packet(s, buf);
1897         } else {
1898             put_packet(s, "E14");
1899         }
1900         break;
1901     case 'P':
1902         if (!gdb_has_xml)
1903             goto unknown_command;
1904         addr = strtoull(p, (char **)&p, 16);
1905         if (*p == '=')
1906             p++;
1907         reg_size = strlen(p) / 2;
1908         hextomem(mem_buf, p, reg_size);
1909         gdb_write_register(s->g_cpu, mem_buf, addr);
1910         put_packet(s, "OK");
1911         break;
1912     case 'Z':
1913     case 'z':
1914         type = strtoul(p, (char **)&p, 16);
1915         if (*p == ',')
1916             p++;
1917         addr = strtoull(p, (char **)&p, 16);
1918         if (*p == ',')
1919             p++;
1920         len = strtoull(p, (char **)&p, 16);
1921         if (ch == 'Z')
1922             res = gdb_breakpoint_insert(addr, len, type);
1923         else
1924             res = gdb_breakpoint_remove(addr, len, type);
1925         if (res >= 0)
1926              put_packet(s, "OK");
1927         else if (res == -ENOSYS)
1928             put_packet(s, "");
1929         else
1930             put_packet(s, "E22");
1931         break;
1932     case 'H':
1933         type = *p++;
1934         thread = strtoull(p, (char **)&p, 16);
1935         if (thread == -1 || thread == 0) {
1936             put_packet(s, "OK");
1937             break;
1938         }
1939         env = find_cpu(thread);
1940         if (env == NULL) {
1941             put_packet(s, "E22");
1942             break;
1943         }
1944         switch (type) {
1945         case 'c':
1946             s->c_cpu = env;
1947             put_packet(s, "OK");
1948             break;
1949         case 'g':
1950             s->g_cpu = env;
1951             put_packet(s, "OK");
1952             break;
1953         default:
1954              put_packet(s, "E22");
1955              break;
1956         }
1957         break;
1958     case 'T':
1959         thread = strtoull(p, (char **)&p, 16);
1960         env = find_cpu(thread);
1961
1962         if (env != NULL) {
1963             put_packet(s, "OK");
1964         } else {
1965             put_packet(s, "E22");
1966         }
1967         break;
1968     case 'q':
1969     case 'Q':
1970         /* parse any 'q' packets here */
1971         if (!strcmp(p,"qemu.sstepbits")) {
1972             /* Query Breakpoint bit definitions */
1973             snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1974                      SSTEP_ENABLE,
1975                      SSTEP_NOIRQ,
1976                      SSTEP_NOTIMER);
1977             put_packet(s, buf);
1978             break;
1979         } else if (strncmp(p,"qemu.sstep",10) == 0) {
1980             /* Display or change the sstep_flags */
1981             p += 10;
1982             if (*p != '=') {
1983                 /* Display current setting */
1984                 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
1985                 put_packet(s, buf);
1986                 break;
1987             }
1988             p++;
1989             type = strtoul(p, (char **)&p, 16);
1990             sstep_flags = type;
1991             put_packet(s, "OK");
1992             break;
1993         } else if (strcmp(p,"C") == 0) {
1994             /* "Current thread" remains vague in the spec, so always return
1995              *  the first CPU (gdb returns the first thread). */
1996             put_packet(s, "QC1");
1997             break;
1998         } else if (strcmp(p,"fThreadInfo") == 0) {
1999             s->query_cpu = first_cpu;
2000             goto report_cpuinfo;
2001         } else if (strcmp(p,"sThreadInfo") == 0) {
2002         report_cpuinfo:
2003             if (s->query_cpu) {
2004                 snprintf(buf, sizeof(buf), "m%x", gdb_id(s->query_cpu));
2005                 put_packet(s, buf);
2006                 s->query_cpu = s->query_cpu->next_cpu;
2007             } else
2008                 put_packet(s, "l");
2009             break;
2010         } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2011             thread = strtoull(p+16, (char **)&p, 16);
2012             env = find_cpu(thread);
2013             if (env != NULL) {
2014                 cpu_synchronize_state(env);
2015                 len = snprintf((char *)mem_buf, sizeof(mem_buf),
2016                                "CPU#%d [%s]", env->cpu_index,
2017                                env->halted ? "halted " : "running");
2018                 memtohex(buf, mem_buf, len);
2019                 put_packet(s, buf);
2020             }
2021             break;
2022         }
2023 #ifdef CONFIG_USER_ONLY
2024         else if (strncmp(p, "Offsets", 7) == 0) {
2025             TaskState *ts = s->c_cpu->opaque;
2026
2027             snprintf(buf, sizeof(buf),
2028                      "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2029                      ";Bss=" TARGET_ABI_FMT_lx,
2030                      ts->info->code_offset,
2031                      ts->info->data_offset,
2032                      ts->info->data_offset);
2033             put_packet(s, buf);
2034             break;
2035         }
2036 #else /* !CONFIG_USER_ONLY */
2037         else if (strncmp(p, "Rcmd,", 5) == 0) {
2038             int len = strlen(p + 5);
2039
2040             if ((len % 2) != 0) {
2041                 put_packet(s, "E01");
2042                 break;
2043             }
2044             hextomem(mem_buf, p + 5, len);
2045             len = len / 2;
2046             mem_buf[len++] = 0;
2047             qemu_chr_read(s->mon_chr, mem_buf, len);
2048             put_packet(s, "OK");
2049             break;
2050         }
2051 #endif /* !CONFIG_USER_ONLY */
2052         if (strncmp(p, "Supported", 9) == 0) {
2053             snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
2054 #ifdef GDB_CORE_XML
2055             pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
2056 #endif
2057             put_packet(s, buf);
2058             break;
2059         }
2060 #ifdef GDB_CORE_XML
2061         if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2062             const char *xml;
2063             target_ulong total_len;
2064
2065             gdb_has_xml = 1;
2066             p += 19;
2067             xml = get_feature_xml(p, &p);
2068             if (!xml) {
2069                 snprintf(buf, sizeof(buf), "E00");
2070                 put_packet(s, buf);
2071                 break;
2072             }
2073
2074             if (*p == ':')
2075                 p++;
2076             addr = strtoul(p, (char **)&p, 16);
2077             if (*p == ',')
2078                 p++;
2079             len = strtoul(p, (char **)&p, 16);
2080
2081             total_len = strlen(xml);
2082             if (addr > total_len) {
2083                 snprintf(buf, sizeof(buf), "E00");
2084                 put_packet(s, buf);
2085                 break;
2086             }
2087             if (len > (MAX_PACKET_LENGTH - 5) / 2)
2088                 len = (MAX_PACKET_LENGTH - 5) / 2;
2089             if (len < total_len - addr) {
2090                 buf[0] = 'm';
2091                 len = memtox(buf + 1, xml + addr, len);
2092             } else {
2093                 buf[0] = 'l';
2094                 len = memtox(buf + 1, xml + addr, total_len - addr);
2095             }
2096             put_packet_binary(s, buf, len + 1);
2097             break;
2098         }
2099 #endif
2100         /* Unrecognised 'q' command.  */
2101         goto unknown_command;
2102
2103     default:
2104     unknown_command:
2105         /* put empty packet */
2106         buf[0] = '\0';
2107         put_packet(s, buf);
2108         break;
2109     }
2110     return RS_IDLE;
2111 }
2112
2113 void gdb_set_stop_cpu(CPUState *env)
2114 {
2115     gdbserver_state->c_cpu = env;
2116     gdbserver_state->g_cpu = env;
2117 }
2118
2119 #ifndef CONFIG_USER_ONLY
2120 static void gdb_vm_state_change(void *opaque, int running, int reason)
2121 {
2122     GDBState *s = gdbserver_state;
2123     CPUState *env = s->c_cpu;
2124     char buf[256];
2125     const char *type;
2126     int ret;
2127
2128     if (running || (reason != EXCP_DEBUG && reason != EXCP_INTERRUPT) ||
2129         s->state == RS_INACTIVE || s->state == RS_SYSCALL)
2130         return;
2131
2132     /* disable single step if it was enable */
2133     cpu_single_step(env, 0);
2134
2135     if (reason == EXCP_DEBUG) {
2136         if (env->watchpoint_hit) {
2137             switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2138             case BP_MEM_READ:
2139                 type = "r";
2140                 break;
2141             case BP_MEM_ACCESS:
2142                 type = "a";
2143                 break;
2144             default:
2145                 type = "";
2146                 break;
2147             }
2148             snprintf(buf, sizeof(buf),
2149                      "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2150                      GDB_SIGNAL_TRAP, gdb_id(env), type,
2151                      env->watchpoint_hit->vaddr);
2152             put_packet(s, buf);
2153             env->watchpoint_hit = NULL;
2154             return;
2155         }
2156         tb_flush(env);
2157         ret = GDB_SIGNAL_TRAP;
2158     } else {
2159         ret = GDB_SIGNAL_INT;
2160     }
2161     snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
2162     put_packet(s, buf);
2163 }
2164 #endif
2165
2166 /* Send a gdb syscall request.
2167    This accepts limited printf-style format specifiers, specifically:
2168     %x  - target_ulong argument printed in hex.
2169     %lx - 64-bit argument printed in hex.
2170     %s  - string pointer (target_ulong) and length (int) pair.  */
2171 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2172 {
2173     va_list va;
2174     char buf[256];
2175     char *p;
2176     target_ulong addr;
2177     uint64_t i64;
2178     GDBState *s;
2179
2180     s = gdbserver_state;
2181     if (!s)
2182         return;
2183     gdb_current_syscall_cb = cb;
2184     s->state = RS_SYSCALL;
2185 #ifndef CONFIG_USER_ONLY
2186     vm_stop(EXCP_DEBUG);
2187 #endif
2188     s->state = RS_IDLE;
2189     va_start(va, fmt);
2190     p = buf;
2191     *(p++) = 'F';
2192     while (*fmt) {
2193         if (*fmt == '%') {
2194             fmt++;
2195             switch (*fmt++) {
2196             case 'x':
2197                 addr = va_arg(va, target_ulong);
2198                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
2199                 break;
2200             case 'l':
2201                 if (*(fmt++) != 'x')
2202                     goto bad_format;
2203                 i64 = va_arg(va, uint64_t);
2204                 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
2205                 break;
2206             case 's':
2207                 addr = va_arg(va, target_ulong);
2208                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
2209                               addr, va_arg(va, int));
2210                 break;
2211             default:
2212             bad_format:
2213                 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2214                         fmt - 1);
2215                 break;
2216             }
2217         } else {
2218             *(p++) = *(fmt++);
2219         }
2220     }
2221     *p = 0;
2222     va_end(va);
2223     put_packet(s, buf);
2224 #ifdef CONFIG_USER_ONLY
2225     gdb_handlesig(s->c_cpu, 0);
2226 #else
2227     cpu_exit(s->c_cpu);
2228 #endif
2229 }
2230
2231 static void gdb_read_byte(GDBState *s, int ch)
2232 {
2233     int i, csum;
2234     uint8_t reply;
2235
2236 #ifndef CONFIG_USER_ONLY
2237     if (s->last_packet_len) {
2238         /* Waiting for a response to the last packet.  If we see the start
2239            of a new command then abandon the previous response.  */
2240         if (ch == '-') {
2241 #ifdef DEBUG_GDB
2242             printf("Got NACK, retransmitting\n");
2243 #endif
2244             put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2245         }
2246 #ifdef DEBUG_GDB
2247         else if (ch == '+')
2248             printf("Got ACK\n");
2249         else
2250             printf("Got '%c' when expecting ACK/NACK\n", ch);
2251 #endif
2252         if (ch == '+' || ch == '$')
2253             s->last_packet_len = 0;
2254         if (ch != '$')
2255             return;
2256     }
2257     if (vm_running) {
2258         /* when the CPU is running, we cannot do anything except stop
2259            it when receiving a char */
2260         vm_stop(EXCP_INTERRUPT);
2261     } else
2262 #endif
2263     {
2264         switch(s->state) {
2265         case RS_IDLE:
2266             if (ch == '$') {
2267                 s->line_buf_index = 0;
2268                 s->state = RS_GETLINE;
2269             }
2270             break;
2271         case RS_GETLINE:
2272             if (ch == '#') {
2273             s->state = RS_CHKSUM1;
2274             } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2275                 s->state = RS_IDLE;
2276             } else {
2277             s->line_buf[s->line_buf_index++] = ch;
2278             }
2279             break;
2280         case RS_CHKSUM1:
2281             s->line_buf[s->line_buf_index] = '\0';
2282             s->line_csum = fromhex(ch) << 4;
2283             s->state = RS_CHKSUM2;
2284             break;
2285         case RS_CHKSUM2:
2286             s->line_csum |= fromhex(ch);
2287             csum = 0;
2288             for(i = 0; i < s->line_buf_index; i++) {
2289                 csum += s->line_buf[i];
2290             }
2291             if (s->line_csum != (csum & 0xff)) {
2292                 reply = '-';
2293                 put_buffer(s, &reply, 1);
2294                 s->state = RS_IDLE;
2295             } else {
2296                 reply = '+';
2297                 put_buffer(s, &reply, 1);
2298                 s->state = gdb_handle_packet(s, s->line_buf);
2299             }
2300             break;
2301         default:
2302             abort();
2303         }
2304     }
2305 }
2306
2307 #ifdef CONFIG_USER_ONLY
2308 int
2309 gdb_queuesig (void)
2310 {
2311     GDBState *s;
2312
2313     s = gdbserver_state;
2314
2315     if (gdbserver_fd < 0 || s->fd < 0)
2316         return 0;
2317     else
2318         return 1;
2319 }
2320
2321 int
2322 gdb_handlesig (CPUState *env, int sig)
2323 {
2324   GDBState *s;
2325   char buf[256];
2326   int n;
2327
2328   s = gdbserver_state;
2329   if (gdbserver_fd < 0 || s->fd < 0)
2330     return sig;
2331
2332   /* disable single step if it was enabled */
2333   cpu_single_step(env, 0);
2334   tb_flush(env);
2335
2336   if (sig != 0)
2337     {
2338       snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2339       put_packet(s, buf);
2340     }
2341   /* put_packet() might have detected that the peer terminated the
2342      connection.  */
2343   if (s->fd < 0)
2344       return sig;
2345
2346   sig = 0;
2347   s->state = RS_IDLE;
2348   s->running_state = 0;
2349   while (s->running_state == 0) {
2350       n = read (s->fd, buf, 256);
2351       if (n > 0)
2352         {
2353           int i;
2354
2355           for (i = 0; i < n; i++)
2356             gdb_read_byte (s, buf[i]);
2357         }
2358       else if (n == 0 || errno != EAGAIN)
2359         {
2360           /* XXX: Connection closed.  Should probably wait for annother
2361              connection before continuing.  */
2362           return sig;
2363         }
2364   }
2365   sig = s->signal;
2366   s->signal = 0;
2367   return sig;
2368 }
2369
2370 /* Tell the remote gdb that the process has exited.  */
2371 void gdb_exit(CPUState *env, int code)
2372 {
2373   GDBState *s;
2374   char buf[4];
2375
2376   s = gdbserver_state;
2377   if (gdbserver_fd < 0 || s->fd < 0)
2378     return;
2379
2380   snprintf(buf, sizeof(buf), "W%02x", code);
2381   put_packet(s, buf);
2382 }
2383
2384 /* Tell the remote gdb that the process has exited due to SIG.  */
2385 void gdb_signalled(CPUState *env, int sig)
2386 {
2387   GDBState *s;
2388   char buf[4];
2389
2390   s = gdbserver_state;
2391   if (gdbserver_fd < 0 || s->fd < 0)
2392     return;
2393
2394   snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2395   put_packet(s, buf);
2396 }
2397
2398 static void gdb_accept(void)
2399 {
2400     GDBState *s;
2401     struct sockaddr_in sockaddr;
2402     socklen_t len;
2403     int val, fd;
2404
2405     for(;;) {
2406         len = sizeof(sockaddr);
2407         fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2408         if (fd < 0 && errno != EINTR) {
2409             perror("accept");
2410             return;
2411         } else if (fd >= 0) {
2412 #ifndef _WIN32
2413             fcntl(fd, F_SETFD, FD_CLOEXEC);
2414 #endif
2415             break;
2416         }
2417     }
2418
2419     /* set short latency */
2420     val = 1;
2421     setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2422
2423     s = qemu_mallocz(sizeof(GDBState));
2424     s->c_cpu = first_cpu;
2425     s->g_cpu = first_cpu;
2426     s->fd = fd;
2427     gdb_has_xml = 0;
2428
2429     gdbserver_state = s;
2430
2431     fcntl(fd, F_SETFL, O_NONBLOCK);
2432 }
2433
2434 static int gdbserver_open(int port)
2435 {
2436     struct sockaddr_in sockaddr;
2437     int fd, val, ret;
2438
2439     fd = socket(PF_INET, SOCK_STREAM, 0);
2440     if (fd < 0) {
2441         perror("socket");
2442         return -1;
2443     }
2444 #ifndef _WIN32
2445     fcntl(fd, F_SETFD, FD_CLOEXEC);
2446 #endif
2447
2448     /* allow fast reuse */
2449     val = 1;
2450     setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2451
2452     sockaddr.sin_family = AF_INET;
2453     sockaddr.sin_port = htons(port);
2454     sockaddr.sin_addr.s_addr = 0;
2455     ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2456     if (ret < 0) {
2457         perror("bind");
2458         return -1;
2459     }
2460     ret = listen(fd, 0);
2461     if (ret < 0) {
2462         perror("listen");
2463         return -1;
2464     }
2465     return fd;
2466 }
2467
2468 int gdbserver_start(int port)
2469 {
2470     gdbserver_fd = gdbserver_open(port);
2471     if (gdbserver_fd < 0)
2472         return -1;
2473     /* accept connections */
2474     gdb_accept();
2475     return 0;
2476 }
2477
2478 /* Disable gdb stub for child processes.  */
2479 void gdbserver_fork(CPUState *env)
2480 {
2481     GDBState *s = gdbserver_state;
2482     if (gdbserver_fd < 0 || s->fd < 0)
2483       return;
2484     close(s->fd);
2485     s->fd = -1;
2486     cpu_breakpoint_remove_all(env, BP_GDB);
2487     cpu_watchpoint_remove_all(env, BP_GDB);
2488 }
2489 #else
2490 static int gdb_chr_can_receive(void *opaque)
2491 {
2492   /* We can handle an arbitrarily large amount of data.
2493    Pick the maximum packet size, which is as good as anything.  */
2494   return MAX_PACKET_LENGTH;
2495 }
2496
2497 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2498 {
2499     int i;
2500
2501     for (i = 0; i < size; i++) {
2502         gdb_read_byte(gdbserver_state, buf[i]);
2503     }
2504 }
2505
2506 static void gdb_chr_event(void *opaque, int event)
2507 {
2508     switch (event) {
2509     case CHR_EVENT_OPENED:
2510         vm_stop(EXCP_INTERRUPT);
2511         gdb_has_xml = 0;
2512         break;
2513     default:
2514         break;
2515     }
2516 }
2517
2518 static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2519 {
2520     char buf[MAX_PACKET_LENGTH];
2521
2522     buf[0] = 'O';
2523     if (len > (MAX_PACKET_LENGTH/2) - 1)
2524         len = (MAX_PACKET_LENGTH/2) - 1;
2525     memtohex(buf + 1, (uint8_t *)msg, len);
2526     put_packet(s, buf);
2527 }
2528
2529 static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2530 {
2531     const char *p = (const char *)buf;
2532     int max_sz;
2533
2534     max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2535     for (;;) {
2536         if (len <= max_sz) {
2537             gdb_monitor_output(gdbserver_state, p, len);
2538             break;
2539         }
2540         gdb_monitor_output(gdbserver_state, p, max_sz);
2541         p += max_sz;
2542         len -= max_sz;
2543     }
2544     return len;
2545 }
2546
2547 #ifndef _WIN32
2548 static void gdb_sigterm_handler(int signal)
2549 {
2550     if (vm_running)
2551         vm_stop(EXCP_INTERRUPT);
2552 }
2553 #endif
2554
2555 int gdbserver_start(const char *device)
2556 {
2557     GDBState *s;
2558     char gdbstub_device_name[128];
2559     CharDriverState *chr = NULL;
2560     CharDriverState *mon_chr;
2561
2562     if (!device)
2563         return -1;
2564     if (strcmp(device, "none") != 0) {
2565         if (strstart(device, "tcp:", NULL)) {
2566             /* enforce required TCP attributes */
2567             snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2568                      "%s,nowait,nodelay,server", device);
2569             device = gdbstub_device_name;
2570         }
2571 #ifndef _WIN32
2572         else if (strcmp(device, "stdio") == 0) {
2573             struct sigaction act;
2574
2575             memset(&act, 0, sizeof(act));
2576             act.sa_handler = gdb_sigterm_handler;
2577             sigaction(SIGINT, &act, NULL);
2578         }
2579 #endif
2580         chr = qemu_chr_open("gdb", device, NULL);
2581         if (!chr)
2582             return -1;
2583
2584         qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2585                               gdb_chr_event, NULL);
2586     }
2587
2588     s = gdbserver_state;
2589     if (!s) {
2590         s = qemu_mallocz(sizeof(GDBState));
2591         gdbserver_state = s;
2592
2593         qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
2594
2595         /* Initialize a monitor terminal for gdb */
2596         mon_chr = qemu_mallocz(sizeof(*mon_chr));
2597         mon_chr->chr_write = gdb_monitor_write;
2598         monitor_init(mon_chr, 0);
2599     } else {
2600         if (s->chr)
2601             qemu_chr_close(s->chr);
2602         mon_chr = s->mon_chr;
2603         memset(s, 0, sizeof(GDBState));
2604     }
2605     s->c_cpu = first_cpu;
2606     s->g_cpu = first_cpu;
2607     s->chr = chr;
2608     s->state = chr ? RS_IDLE : RS_INACTIVE;
2609     s->mon_chr = mon_chr;
2610
2611     return 0;
2612 }
2613 #endif