hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29 #include "msix.h"
  30 #include "qemu-kvm.h"
  31 #include "hw/pc.h"
  32 #include "device-assignment.h"
  33
  34 //#define DEBUG_PCI
  35 #ifdef DEBUG_PCI
  36 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  37 #else
  38 # define PCI_DPRINTF(format, ...)       do { } while (0)
  39 #endif
  40
  41 struct PCIBus {
  42     BusState qbus;
  43     int bus_num;
  44     int devfn_min;
  45     pci_set_irq_fn set_irq;
  46     pci_map_irq_fn map_irq;
  47     pci_hotplug_fn hotplug;
  48     uint32_t config_reg; /* XXX: suppress */
  49     void *irq_opaque;
  50     PCIDevice *devices[256];
  51     PCIDevice *parent_dev;
  52     PCIBus *next;
  53     /* The bus IRQ state is the logical OR of the connected devices.
  54        Keep a count of the number of devices with raised IRQs.  */
  55     int nirq;
  56     int *irq_count;
  57 };
  58
  59 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  60
  61 static struct BusInfo pci_bus_info = {
  62     .name       = "PCI",
  63     .size       = sizeof(PCIBus),
  64     .print_dev  = pcibus_dev_print,
  65     .props      = (Property[]) {
  66         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  67         DEFINE_PROP_END_OF_LIST()
  68     }
  69 };
  70
  71 static void pci_update_mappings(PCIDevice *d);
  72 static void pci_set_irq(void *opaque, int irq_num, int level);
  73
  74 target_phys_addr_t pci_mem_base;
  75 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  76 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  77 static PCIBus *first_bus;
  78
  79 static const VMStateDescription vmstate_pcibus = {
  80     .name = "PCIBUS",
  81     .version_id = 1,
  82     .minimum_version_id = 1,
  83     .minimum_version_id_old = 1,
  84     .fields      = (VMStateField []) {
  85         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  86         VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq),
  87         VMSTATE_END_OF_LIST()
  88     }
  89 };
  90
  91 static inline int pci_bar(int reg)
  92 {
  93     return reg == PCI_ROM_SLOT ? PCI_ROM_ADDRESS : PCI_BASE_ADDRESS_0 + reg * 4;
  94 }
  95
  96 static void pci_device_reset(PCIDevice *dev)
  97 {
  98     memset(dev->irq_state, 0, sizeof dev->irq_state);
  99 }
 100
 101 static void pci_bus_reset(void *opaque)
 102 {
 103     PCIBus *bus = opaque;
 104     int i;
 105
 106     for (i = 0; i < bus->nirq; i++) {
 107         bus->irq_count[i] = 0;
 108     }
 109     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 110         if (bus->devices[i]) {
 111             pci_device_reset(bus->devices[i]);
 112         }
 113     }
 114 }
 115
 116 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 117                          const char *name, int devfn_min)
 118 {
 119     static int nbus = 0;
 120
 121     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 122     bus->devfn_min = devfn_min;
 123     bus->next = first_bus;
 124     first_bus = bus;
 125     vmstate_register(nbus++, &vmstate_pcibus, bus);
 126     qemu_register_reset(pci_bus_reset, bus);
 127 }
 128
 129 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 130 {
 131     PCIBus *bus;
 132
 133     bus = qemu_mallocz(sizeof(*bus));
 134     bus->qbus.qdev_allocated = 1;
 135     pci_bus_new_inplace(bus, parent, name, devfn_min);
 136     return bus;
 137 }
 138
 139 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 140                   void *irq_opaque, int nirq)
 141 {
 142     bus->set_irq = set_irq;
 143     bus->map_irq = map_irq;
 144     bus->irq_opaque = irq_opaque;
 145     bus->nirq = nirq;
 146     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 147 }
 148
 149 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 150 {
 151     bus->qbus.allow_hotplug = 1;
 152     bus->hotplug = hotplug;
 153 }
 154
 155 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 156                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 157                          void *irq_opaque, int devfn_min, int nirq)
 158 {
 159     PCIBus *bus;
 160
 161     bus = pci_bus_new(parent, name, devfn_min);
 162     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 163     return bus;
 164 }
 165
 166 static void pci_register_secondary_bus(PCIBus *bus,
 167                                        PCIDevice *dev,
 168                                        pci_map_irq_fn map_irq,
 169                                        const char *name)
 170 {
 171     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 172     bus->map_irq = map_irq;
 173     bus->parent_dev = dev;
 174     bus->next = dev->bus->next;
 175     dev->bus->next = bus;
 176 }
 177
 178 int pci_bus_num(PCIBus *s)
 179 {
 180     return s->bus_num;
 181 }
 182
 183 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 184 {
 185     PCIDevice *s = container_of(pv, PCIDevice, config);
 186     uint8_t config[size];
 187     int i;
 188
 189     qemu_get_buffer(f, config, size);
 190     for (i = 0; i < size; ++i)
 191         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 192             return -EINVAL;
 193     memcpy(s->config, config, size);
 194
 195     pci_update_mappings(s);
 196
 197     return 0;
 198 }
 199
 200 /* just put buffer */
 201 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 202 {
 203     const uint8_t *v = pv;
 204     qemu_put_buffer(f, v, size);
 205 }
 206
 207 static VMStateInfo vmstate_info_pci_config = {
 208     .name = "pci config",
 209     .get  = get_pci_config_device,
 210     .put  = put_pci_config_device,
 211 };
 212
 213 const VMStateDescription vmstate_pci_device = {
 214     .name = "PCIDevice",
 215     .version_id = 2,
 216     .minimum_version_id = 1,
 217     .minimum_version_id_old = 1,
 218     .fields      = (VMStateField []) {
 219         VMSTATE_INT32_LE(version_id, PCIDevice),
 220         VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
 221                        typeof_field(PCIDevice,config)),
 222         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2),
 223         VMSTATE_END_OF_LIST()
 224     }
 225 };
 226
 227 void pci_device_save(PCIDevice *s, QEMUFile *f)
 228 {
 229     vmstate_save_state(f, &vmstate_pci_device, s);
 230 }
 231
 232 int pci_device_load(PCIDevice *s, QEMUFile *f)
 233 {
 234     return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
 235 }
 236
 237 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 238 {
 239     uint16_t *id;
 240
 241     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 242     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 243     id[1] = cpu_to_le16(pci_default_sub_device_id);
 244     return 0;
 245 }
 246
 247 /*
 248  * Parse pci address in qemu command
 249  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 250  */
 251 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 252 {
 253     const char *p;
 254     char *e;
 255     unsigned long val;
 256     unsigned long dom = 0, bus = 0;
 257     unsigned slot = 0;
 258
 259     p = addr;
 260     val = strtoul(p, &e, 16);
 261     if (e == p)
 262         return -1;
 263     if (*e == ':') {
 264         bus = val;
 265         p = e + 1;
 266         val = strtoul(p, &e, 16);
 267         if (e == p)
 268             return -1;
 269         if (*e == ':') {
 270             dom = bus;
 271             bus = val;
 272             p = e + 1;
 273             val = strtoul(p, &e, 16);
 274             if (e == p)
 275                 return -1;
 276         }
 277     }
 278
 279     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 280         return -1;
 281
 282     slot = val;
 283
 284     if (*e)
 285         return -1;
 286
 287     /* Note: QEMU doesn't implement domains other than 0 */
 288     if (dom != 0 || pci_find_bus(bus) == NULL)
 289         return -1;
 290
 291     *domp = dom;
 292     *busp = bus;
 293     *slotp = slot;
 294     return 0;
 295 }
 296
 297 /*
 298  * Parse device bdf in device assignment command:
 299  *
 300  * -pcidevice host=bus:dev.func
 301  *
 302  * Parse <bus>:<slot>.<func> return -1 on error
 303  */
 304 int pci_parse_host_devaddr(const char *addr, int *busp,
 305                            int *slotp, int *funcp)
 306 {
 307     const char *p;
 308     char *e;
 309     int val;
 310     int bus = 0, slot = 0, func = 0;
 311
 312     p = addr;
 313     val = strtoul(p, &e, 16);
 314     if (e == p)
 315         return -1;
 316     if (*e == ':') {
 317         bus = val;
 318         p = e + 1;
 319         val = strtoul(p, &e, 16);
 320         if (e == p)
 321             return -1;
 322         if (*e == '.') {
 323             slot = val;
 324             p = e + 1;
 325             val = strtoul(p, &e, 16);
 326             if (e == p)
 327                 return -1;
 328             func = val;
 329         } else
 330             return -1;
 331     } else
 332         return -1;
 333
 334     if (bus > 0xff || slot > 0x1f || func > 0x7)
 335         return -1;
 336
 337     if (*e)
 338         return -1;
 339
 340     *busp = bus;
 341     *slotp = slot;
 342     *funcp = func;
 343     return 0;
 344 }
 345
 346 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 347                      unsigned *slotp)
 348 {
 349     /* strip legacy tag */
 350     if (!strncmp(addr, "pci_addr=", 9)) {
 351         addr += 9;
 352     }
 353     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 354         monitor_printf(mon, "Invalid pci address\n");
 355         return -1;
 356     }
 357     return 0;
 358 }
 359
 360 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 361 {
 362     int dom, bus;
 363     unsigned slot;
 364
 365     if (!devaddr) {
 366         *devfnp = -1;
 367         return pci_find_bus(0);
 368     }
 369
 370     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 371         return NULL;
 372     }
 373
 374     *devfnp = slot << 3;
 375     return pci_find_bus(bus);
 376 }
 377
 378 static void pci_init_cmask(PCIDevice *dev)
 379 {
 380     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 381     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 382     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 383     dev->cmask[PCI_REVISION_ID] = 0xff;
 384     dev->cmask[PCI_CLASS_PROG] = 0xff;
 385     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 386     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 387     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 388 }
 389
 390 static void pci_init_wmask(PCIDevice *dev)
 391 {
 392     int i;
 393     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 394     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 395     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 396                               | PCI_COMMAND_MASTER;
 397     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 398         dev->wmask[i] = 0xff;
 399 }
 400
 401 /* -1 for devfn means auto assign */
 402 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 403                                          const char *name, int devfn,
 404                                          PCIConfigReadFunc *config_read,
 405                                          PCIConfigWriteFunc *config_write)
 406 {
 407     if (devfn < 0) {
 408         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 409             if (!bus->devices[devfn])
 410                 goto found;
 411         }
 412         return NULL;
 413     found: ;
 414     } else if (bus->devices[devfn]) {
 415         return NULL;
 416     }
 417     pci_dev->bus = bus;
 418     pci_dev->devfn = devfn;
 419     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 420     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 421     pci_set_default_subsystem_id(pci_dev);
 422     pci_init_cmask(pci_dev);
 423     pci_init_wmask(pci_dev);
 424
 425     if (!config_read)
 426         config_read = pci_default_read_config;
 427     if (!config_write)
 428         config_write = pci_default_write_config;
 429     pci_dev->config_read = config_read;
 430     pci_dev->config_write = config_write;
 431     bus->devices[devfn] = pci_dev;
 432     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 433     pci_dev->version_id = 2; /* Current pci device vmstate version */
 434     return pci_dev;
 435 }
 436
 437 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 438                                int instance_size, int devfn,
 439                                PCIConfigReadFunc *config_read,
 440                                PCIConfigWriteFunc *config_write)
 441 {
 442     PCIDevice *pci_dev;
 443
 444     pci_dev = qemu_mallocz(instance_size);
 445     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 446                                      config_read, config_write);
 447     return pci_dev;
 448 }
 449 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 450 {
 451     return addr + pci_mem_base;
 452 }
 453
 454 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 455 {
 456     PCIIORegion *r;
 457     int i;
 458
 459     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 460         r = &pci_dev->io_regions[i];
 461         if (!r->size || r->addr == -1)
 462             continue;
 463         if (r->type == PCI_ADDRESS_SPACE_IO) {
 464             isa_unassign_ioport(r->addr, r->size);
 465         } else {
 466             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 467                                                      r->size,
 468                                                      IO_MEM_UNASSIGNED);
 469         }
 470     }
 471 }
 472
 473 static int pci_unregister_device(DeviceState *dev)
 474 {
 475     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 476     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 477     int ret = 0;
 478
 479     if (info->exit)
 480         ret = info->exit(pci_dev);
 481     if (ret)
 482         return ret;
 483
 484     msix_uninit(pci_dev);
 485     pci_unregister_io_regions(pci_dev);
 486
 487     qemu_free_irqs(pci_dev->irq);
 488     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 489     return 0;
 490 }
 491
 492 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 493                             uint32_t size, int type,
 494                             PCIMapIORegionFunc *map_func)
 495 {
 496     PCIIORegion *r;
 497     uint32_t addr;
 498     uint32_t wmask;
 499
 500     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 501         return;
 502
 503     if (size & (size-1)) {
 504         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 505                     "type=0x%x, size=0x%x\n", type, size);
 506         exit(1);
 507     }
 508
 509     r = &pci_dev->io_regions[region_num];
 510     r->addr = -1;
 511     r->size = size;
 512     r->type = type;
 513     r->map_func = map_func;
 514
 515     wmask = ~(size - 1);
 516     addr = pci_bar(region_num);
 517     if (region_num == PCI_ROM_SLOT) {
 518         /* ROM enable bit is writeable */
 519         wmask |= PCI_ROM_ADDRESS_ENABLE;
 520     }
 521     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 522     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 523     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 524 }
 525
 526 static void pci_update_mappings(PCIDevice *d)
 527 {
 528     PCIIORegion *r;
 529     int cmd, i;
 530     uint32_t last_addr, new_addr;
 531
 532     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 533     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 534         r = &d->io_regions[i];
 535         if (r->size != 0) {
 536             if (r->type & PCI_ADDRESS_SPACE_IO) {
 537                 if (cmd & PCI_COMMAND_IO) {
 538                     new_addr = pci_get_long(d->config + pci_bar(i));
 539                     new_addr = new_addr & ~(r->size - 1);
 540                     last_addr = new_addr + r->size - 1;
 541                     /* NOTE: we have only 64K ioports on PC */
 542                     if (last_addr <= new_addr || new_addr == 0 ||
 543                         last_addr >= 0x10000) {
 544                         new_addr = -1;
 545                     }
 546                 } else {
 547                     new_addr = -1;
 548                 }
 549             } else {
 550                 if (cmd & PCI_COMMAND_MEMORY) {
 551                     new_addr = pci_get_long(d->config + pci_bar(i));
 552                     /* the ROM slot has a specific enable bit */
 553                     if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
 554                         goto no_mem_map;
 555                     new_addr = new_addr & ~(r->size - 1);
 556                     last_addr = new_addr + r->size - 1;
 557                     /* NOTE: we do not support wrapping */
 558                     /* XXX: as we cannot support really dynamic
 559                        mappings, we handle specific values as invalid
 560                        mappings. */
 561                     if (last_addr <= new_addr || new_addr == 0 ||
 562                         last_addr == -1) {
 563                         new_addr = -1;
 564                     }
 565                 } else {
 566                 no_mem_map:
 567                     new_addr = -1;
 568                 }
 569             }
 570             /* now do the real mapping */
 571             if (new_addr != r->addr) {
 572                 if (r->addr != -1) {
 573                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 574                         int class;
 575                         /* NOTE: specific hack for IDE in PC case:
 576                            only one byte must be mapped. */
 577                         class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 578                         if (class == 0x0101 && r->size == 4) {
 579                             isa_unassign_ioport(r->addr + 2, 1);
 580                         } else {
 581                             isa_unassign_ioport(r->addr, r->size);
 582                         }
 583                     } else {
 584                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 585                                                      r->size,
 586                                                      IO_MEM_UNASSIGNED);
 587                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 588                     }
 589                 }
 590                 r->addr = new_addr;
 591                 if (r->addr != -1) {
 592                     r->map_func(d, i, r->addr, r->size, r->type);
 593                 }
 594             }
 595         }
 596     }
 597 }
 598
 599 static uint32_t pci_read_config(PCIDevice *d,
 600                                 uint32_t address, int len)
 601 {
 602     uint32_t val;
 603
 604     switch(len) {
 605     default:
 606     case 4:
 607         if (address <= 0xfc) {
 608             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 609             break;
 610         }
 611         /* fall through */
 612     case 2:
 613         if (address <= 0xfe) {
 614             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 615             break;
 616         }
 617         /* fall through */
 618     case 1:
 619         val = d->config[address];
 620         break;
 621     }
 622     return val;
 623 }
 624
 625 static void pci_write_config(PCIDevice *pci_dev,
 626                              uint32_t address, uint32_t val, int len)
 627 {
 628     int i;
 629     for (i = 0; i < len; i++) {
 630         pci_dev->config[address + i] = val & 0xff;
 631         val >>= 8;
 632     }
 633 }
 634
 635 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len)
 636 {
 637     if (pci_dev->cap.supported && address >= pci_dev->cap.start &&
 638             (address + len) < pci_dev->cap.start + pci_dev->cap.length)
 639         return 1;
 640     return 0;
 641 }
 642
 643 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 644                                      uint32_t address, int len)
 645 {
 646     return pci_read_config(pci_dev, address, len);
 647 }
 648
 649 void pci_default_cap_write_config(PCIDevice *pci_dev,
 650                                   uint32_t address, uint32_t val, int len)
 651 {
 652     pci_write_config(pci_dev, address, val, len);
 653 }
 654
 655 uint32_t pci_default_read_config(PCIDevice *d,
 656                                  uint32_t address, int len)
 657 {
 658     if (pci_access_cap_config(d, address, len))
 659         return d->cap.config_read(d, address, len);
 660
 661     return pci_read_config(d, address, len);
 662 }
 663
 664 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 665 {
 666     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 667     int i;
 668
 669     if (pci_access_cap_config(d, addr, l)) {
 670         d->cap.config_write(d, addr, val, l);
 671         return;
 672     }
 673
 674     /* not efficient, but simple */
 675     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 676     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 677         uint8_t wmask = d->wmask[addr];
 678         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 679     }
 680
 681 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
 682     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel() &&
 683         addr >= PIIX_CONFIG_IRQ_ROUTE &&
 684         addr < PIIX_CONFIG_IRQ_ROUTE + 4)
 685         assigned_dev_update_irqs();
 686 #endif /* CONFIG_KVM_DEVICE_ASSIGNMENT */
 687
 688     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 689         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 690             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 691         pci_update_mappings(d);
 692
 693 }
 694
 695 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 696 {
 697     PCIBus *s = opaque;
 698     PCIDevice *pci_dev;
 699     int config_addr, bus_num;
 700
 701 #if 0
 702     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 703                 addr, val, len);
 704 #endif
 705     bus_num = (addr >> 16) & 0xff;
 706     while (s && s->bus_num != bus_num)
 707         s = s->next;
 708     if (!s)
 709         return;
 710     pci_dev = s->devices[(addr >> 8) & 0xff];
 711     if (!pci_dev)
 712         return;
 713     config_addr = addr & 0xff;
 714     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 715                 pci_dev->name, config_addr, val, len);
 716     pci_dev->config_write(pci_dev, config_addr, val, len);
 717 }
 718
 719 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 720 {
 721     PCIBus *s = opaque;
 722     PCIDevice *pci_dev;
 723     int config_addr, bus_num;
 724     uint32_t val;
 725
 726     bus_num = (addr >> 16) & 0xff;
 727     while (s && s->bus_num != bus_num)
 728         s= s->next;
 729     if (!s)
 730         goto fail;
 731     pci_dev = s->devices[(addr >> 8) & 0xff];
 732     if (!pci_dev) {
 733     fail:
 734         switch(len) {
 735         case 1:
 736             val = 0xff;
 737             break;
 738         case 2:
 739             val = 0xffff;
 740             break;
 741         default:
 742         case 4:
 743             val = 0xffffffff;
 744             break;
 745         }
 746         goto the_end;
 747     }
 748     config_addr = addr & 0xff;
 749     val = pci_dev->config_read(pci_dev, config_addr, len);
 750     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 751                 pci_dev->name, config_addr, val, len);
 752  the_end:
 753 #if 0
 754     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 755                 addr, val, len);
 756 #endif
 757     return val;
 758 }
 759
 760 /***********************************************************/
 761 /* generic PCI irq support */
 762
 763 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 764 static void pci_set_irq(void *opaque, int irq_num, int level)
 765 {
 766     PCIDevice *pci_dev = opaque;
 767     PCIBus *bus;
 768     int change;
 769
 770     change = level - pci_dev->irq_state[irq_num];
 771     if (!change)
 772         return;
 773
 774     pci_dev->irq_state[irq_num] = level;
 775
 776 #if defined(TARGET_IA64)
 777     ioapic_set_irq(pci_dev, irq_num, level);
 778 #endif
 779
 780     for (;;) {
 781         bus = pci_dev->bus;
 782         irq_num = bus->map_irq(pci_dev, irq_num);
 783         if (bus->set_irq)
 784             break;
 785         pci_dev = bus->parent_dev;
 786     }
 787     bus->irq_count[irq_num] += change;
 788     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 789 }
 790
 791 int pci_map_irq(PCIDevice *pci_dev, int pin)
 792 {
 793     return pci_dev->bus->map_irq(pci_dev, pin);
 794 }
 795
 796 /***********************************************************/
 797 /* monitor info on PCI */
 798
 799 typedef struct {
 800     uint16_t class;
 801     const char *desc;
 802 } pci_class_desc;
 803
 804 static const pci_class_desc pci_class_descriptions[] =
 805 {
 806     { 0x0100, "SCSI controller"},
 807     { 0x0101, "IDE controller"},
 808     { 0x0102, "Floppy controller"},
 809     { 0x0103, "IPI controller"},
 810     { 0x0104, "RAID controller"},
 811     { 0x0106, "SATA controller"},
 812     { 0x0107, "SAS controller"},
 813     { 0x0180, "Storage controller"},
 814     { 0x0200, "Ethernet controller"},
 815     { 0x0201, "Token Ring controller"},
 816     { 0x0202, "FDDI controller"},
 817     { 0x0203, "ATM controller"},
 818     { 0x0280, "Network controller"},
 819     { 0x0300, "VGA controller"},
 820     { 0x0301, "XGA controller"},
 821     { 0x0302, "3D controller"},
 822     { 0x0380, "Display controller"},
 823     { 0x0400, "Video controller"},
 824     { 0x0401, "Audio controller"},
 825     { 0x0402, "Phone"},
 826     { 0x0480, "Multimedia controller"},
 827     { 0x0500, "RAM controller"},
 828     { 0x0501, "Flash controller"},
 829     { 0x0580, "Memory controller"},
 830     { 0x0600, "Host bridge"},
 831     { 0x0601, "ISA bridge"},
 832     { 0x0602, "EISA bridge"},
 833     { 0x0603, "MC bridge"},
 834     { 0x0604, "PCI bridge"},
 835     { 0x0605, "PCMCIA bridge"},
 836     { 0x0606, "NUBUS bridge"},
 837     { 0x0607, "CARDBUS bridge"},
 838     { 0x0608, "RACEWAY bridge"},
 839     { 0x0680, "Bridge"},
 840     { 0x0c03, "USB controller"},
 841     { 0, NULL}
 842 };
 843
 844 static void pci_info_device(PCIDevice *d)
 845 {
 846     Monitor *mon = cur_mon;
 847     int i, class;
 848     PCIIORegion *r;
 849     const pci_class_desc *desc;
 850
 851     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 852                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 853     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 854     monitor_printf(mon, "    ");
 855     desc = pci_class_descriptions;
 856     while (desc->desc && class != desc->class)
 857         desc++;
 858     if (desc->desc) {
 859         monitor_printf(mon, "%s", desc->desc);
 860     } else {
 861         monitor_printf(mon, "Class %04x", class);
 862     }
 863     monitor_printf(mon, ": PCI device %04x:%04x\n",
 864            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 865            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 866
 867     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 868         monitor_printf(mon, "      IRQ %d.\n",
 869                        d->config[PCI_INTERRUPT_LINE]);
 870     }
 871     if (class == 0x0604) {
 872         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 873     }
 874     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 875         r = &d->io_regions[i];
 876         if (r->size != 0) {
 877             monitor_printf(mon, "      BAR%d: ", i);
 878             if (r->type & PCI_ADDRESS_SPACE_IO) {
 879                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 880                                r->addr, r->addr + r->size - 1);
 881             } else {
 882                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 883                                r->addr, r->addr + r->size - 1);
 884             }
 885         }
 886     }
 887     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 888     if (class == 0x0604 && d->config[0x19] != 0) {
 889         pci_for_each_device(d->config[0x19], pci_info_device);
 890     }
 891 }
 892
 893 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 894 {
 895     PCIBus *bus = first_bus;
 896     PCIDevice *d;
 897     int devfn;
 898
 899     while (bus && bus->bus_num != bus_num)
 900         bus = bus->next;
 901     if (bus) {
 902         for(devfn = 0; devfn < 256; devfn++) {
 903             d = bus->devices[devfn];
 904             if (d)
 905                 fn(d);
 906         }
 907     }
 908 }
 909
 910 void pci_info(Monitor *mon)
 911 {
 912     pci_for_each_device(0, pci_info_device);
 913 }
 914
 915 static const char * const pci_nic_models[] = {
 916     "ne2k_pci",
 917     "i82551",
 918     "i82557b",
 919     "i82559er",
 920     "rtl8139",
 921     "e1000",
 922     "pcnet",
 923     "virtio",
 924     NULL
 925 };
 926
 927 static const char * const pci_nic_names[] = {
 928     "ne2k_pci",
 929     "i82551",
 930     "i82557b",
 931     "i82559er",
 932     "rtl8139",
 933     "e1000",
 934     "pcnet",
 935     "virtio-net-pci",
 936     NULL
 937 };
 938
 939 int pci_nic_supported(const char *model)
 940 {
 941     int i;
 942
 943     for (i = 0; pci_nic_names[i]; i++)
 944         if (strcmp(model, pci_nic_names[i]) == 0)
 945             return 1;
 946
 947     return 0;
 948 }
 949
 950 /* Initialize a PCI NIC.  */
 951 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 952                         const char *default_devaddr)
 953 {
 954     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 955     PCIBus *bus;
 956     int devfn;
 957     PCIDevice *pci_dev;
 958     DeviceState *dev;
 959     int i;
 960
 961     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
 962     if (i < 0)
 963         return NULL;
 964
 965     bus = pci_get_bus_devfn(&devfn, devaddr);
 966     if (!bus) {
 967         qemu_error("Invalid PCI device address %s for device %s\n",
 968                    devaddr, pci_nic_names[i]);
 969         return NULL;
 970     }
 971
 972     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
 973     dev = &pci_dev->qdev;
 974     if (nd->id)
 975         dev->id = qemu_strdup(nd->id);
 976     dev->nd = nd;
 977     if (qdev_init(dev) < 0)
 978         return NULL;
 979     nd->private = dev;
 980     return pci_dev;
 981 }
 982
 983 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 984                                const char *default_devaddr)
 985 {
 986     PCIDevice *res;
 987
 988     if (qemu_show_nic_models(nd->model, pci_nic_models))
 989         exit(0);
 990
 991     res = pci_nic_init(nd, default_model, default_devaddr);
 992     if (!res)
 993         exit(1);
 994     return res;
 995 }
 996
 997 typedef struct {
 998     PCIDevice dev;
 999     PCIBus bus;
1000     uint32_t vid;
1001     uint32_t did;
1002 } PCIBridge;
1003
1004 static void pci_bridge_write_config(PCIDevice *d,
1005                              uint32_t address, uint32_t val, int len)
1006 {
1007     PCIBridge *s = (PCIBridge *)d;
1008
1009     pci_default_write_config(d, address, val, len);
1010     s->bus.bus_num = d->config[PCI_SECONDARY_BUS];
1011 }
1012
1013 PCIBus *pci_find_bus(int bus_num)
1014 {
1015     PCIBus *bus = first_bus;
1016
1017     while (bus && bus->bus_num != bus_num)
1018         bus = bus->next;
1019
1020     return bus;
1021 }
1022
1023 PCIDevice *pci_find_device(int bus_num, int slot, int function)
1024 {
1025     PCIBus *bus = pci_find_bus(bus_num);
1026
1027     if (!bus)
1028         return NULL;
1029
1030     return bus->devices[PCI_DEVFN(slot, function)];
1031 }
1032
1033 static int pci_bridge_initfn(PCIDevice *dev)
1034 {
1035     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1036
1037     pci_config_set_vendor_id(s->dev.config, s->vid);
1038     pci_config_set_device_id(s->dev.config, s->did);
1039
1040     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
1041     s->dev.config[0x05] = 0x00;
1042     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
1043     s->dev.config[0x07] = 0x00; // status = fast devsel
1044     s->dev.config[0x08] = 0x00; // revision
1045     s->dev.config[0x09] = 0x00; // programming i/f
1046     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
1047     s->dev.config[0x0D] = 0x10; // latency_timer
1048     s->dev.config[PCI_HEADER_TYPE] =
1049         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
1050     s->dev.config[0x1E] = 0xa0; // secondary status
1051     return 0;
1052 }
1053
1054 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1055                         pci_map_irq_fn map_irq, const char *name)
1056 {
1057     PCIDevice *dev;
1058     PCIBridge *s;
1059
1060     dev = pci_create(bus, devfn, "pci-bridge");
1061     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1062     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1063     qdev_init(&dev->qdev);
1064
1065     s = DO_UPCAST(PCIBridge, dev, dev);
1066     pci_register_secondary_bus(&s->bus, &s->dev, map_irq, name);
1067     return &s->bus;
1068 }
1069
1070 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1071 {
1072     PCIDevice *pci_dev = (PCIDevice *)qdev;
1073     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1074     PCIBus *bus;
1075     int devfn, rc;
1076
1077     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1078     devfn = pci_dev->devfn;
1079     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1080                                      info->config_read, info->config_write);
1081     assert(pci_dev);
1082     rc = info->init(pci_dev);
1083     if (rc != 0)
1084         return rc;
1085     if (qdev->hotplugged)
1086         bus->hotplug(pci_dev, 1);
1087     return 0;
1088 }
1089
1090 static int pci_unplug_device(DeviceState *qdev)
1091 {
1092     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1093
1094     dev->bus->hotplug(dev, 0);
1095     return 0;
1096 }
1097
1098 void pci_qdev_register(PCIDeviceInfo *info)
1099 {
1100     info->qdev.init = pci_qdev_init;
1101     info->qdev.unplug = pci_unplug_device;
1102     info->qdev.exit = pci_unregister_device;
1103     info->qdev.bus_info = &pci_bus_info;
1104     qdev_register(&info->qdev);
1105 }
1106
1107 void pci_qdev_register_many(PCIDeviceInfo *info)
1108 {
1109     while (info->qdev.name) {
1110         pci_qdev_register(info);
1111         info++;
1112     }
1113 }
1114
1115 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1116 {
1117     DeviceState *dev;
1118
1119     dev = qdev_create(&bus->qbus, name);
1120     qdev_prop_set_uint32(dev, "addr", devfn);
1121     return DO_UPCAST(PCIDevice, qdev, dev);
1122 }
1123
1124 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1125 {
1126     PCIDevice *dev = pci_create(bus, devfn, name);
1127     qdev_init(&dev->qdev);
1128     return dev;
1129 }
1130
1131 int pci_enable_capability_support(PCIDevice *pci_dev,
1132                                   uint32_t config_start,
1133                                   PCICapConfigReadFunc *config_read,
1134                                   PCICapConfigWriteFunc *config_write,
1135                                   PCICapConfigInitFunc *config_init)
1136 {
1137     if (!pci_dev)
1138         return -ENODEV;
1139
1140     pci_dev->config[0x06] |= 0x10; // status = capabilities
1141
1142     if (config_start == 0)
1143         pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR;
1144     else if (config_start >= 0x40 && config_start < 0xff)
1145         pci_dev->cap.start = config_start;
1146     else
1147         return -EINVAL;
1148
1149     if (config_read)
1150         pci_dev->cap.config_read = config_read;
1151     else
1152         pci_dev->cap.config_read = pci_default_cap_read_config;
1153     if (config_write)
1154         pci_dev->cap.config_write = config_write;
1155     else
1156         pci_dev->cap.config_write = pci_default_cap_write_config;
1157     pci_dev->cap.supported = 1;
1158     pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start;
1159     return config_init(pci_dev);
1160 }
1161
1162 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1163 {
1164     int offset = PCI_CONFIG_HEADER_SIZE;
1165     int i;
1166     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
1167         if (pdev->used[i])
1168             offset = i + 1;
1169         else if (i - offset + 1 == size)
1170             return offset;
1171     return 0;
1172 }
1173
1174 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1175                                         uint8_t *prev_p)
1176 {
1177     uint8_t next, prev;
1178
1179     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1180         return 0;
1181
1182     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1183          prev = next + PCI_CAP_LIST_NEXT)
1184         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1185             break;
1186
1187     if (prev_p)
1188         *prev_p = prev;
1189     return next;
1190 }
1191
1192 /* Reserve space and add capability to the linked list in pci config space */
1193 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1194 {
1195     uint8_t offset = pci_find_space(pdev, size);
1196     uint8_t *config = pdev->config + offset;
1197     if (!offset)
1198         return -ENOSPC;
1199     config[PCI_CAP_LIST_ID] = cap_id;
1200     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1201     pdev->config[PCI_CAPABILITY_LIST] = offset;
1202     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1203     memset(pdev->used + offset, 0xFF, size);
1204     /* Make capability read-only by default */
1205     memset(pdev->wmask + offset, 0, size);
1206     /* Check capability by default */
1207     memset(pdev->cmask + offset, 0xFF, size);
1208     return offset;
1209 }
1210
1211 /* Unlink capability from the pci config space. */
1212 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1213 {
1214     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1215     if (!offset)
1216         return;
1217     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1218     /* Make capability writeable again */
1219     memset(pdev->wmask + offset, 0xff, size);
1220     /* Clear cmask as device-specific registers can't be checked */
1221     memset(pdev->cmask + offset, 0, size);
1222     memset(pdev->used + offset, 0, size);
1223
1224     if (!pdev->config[PCI_CAPABILITY_LIST])
1225         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1226 }
1227
1228 /* Reserve space for capability at a known offset (to call after load). */
1229 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1230 {
1231     memset(pdev->used + offset, 0xff, size);
1232 }
1233
1234 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1235 {
1236     return pci_find_capability_list(pdev, cap_id, NULL);
1237 }
1238
1239 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1240 {
1241     PCIDevice *d = (PCIDevice *)dev;
1242     const pci_class_desc *desc;
1243     char ctxt[64];
1244     PCIIORegion *r;
1245     int i, class;
1246
1247     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1248     desc = pci_class_descriptions;
1249     while (desc->desc && class != desc->class)
1250         desc++;
1251     if (desc->desc) {
1252         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1253     } else {
1254         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1255     }
1256
1257     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1258                    "pci id %04x:%04x (sub %04x:%04x)\n",
1259                    indent, "", ctxt,
1260                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1261                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1262                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1263                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1264                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1265     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1266         r = &d->io_regions[i];
1267         if (!r->size)
1268             continue;
1269         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1270                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1271                        r->addr, r->addr + r->size - 1);
1272     }
1273 }
1274
1275 static PCIDeviceInfo bridge_info = {
1276     .qdev.name    = "pci-bridge",
1277     .qdev.size    = sizeof(PCIBridge),
1278     .init         = pci_bridge_initfn,
1279     .config_write = pci_bridge_write_config,
1280     .qdev.props   = (Property[]) {
1281         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1282         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1283         DEFINE_PROP_END_OF_LIST(),
1284     }
1285 };
1286
1287 static void pci_register_devices(void)
1288 {
1289     pci_qdev_register(&bridge_info);
1290 }
1291
1292 device_init(pci_register_devices)