hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pci_host.h"
  27 #include "monitor.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "qemu-kvm.h"
  31 #include "hw/pc.h"
  32 #include "device-assignment.h"
  33
  34 //#define DEBUG_PCI
  35 #ifdef DEBUG_PCI
  36 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  37 #else
  38 # define PCI_DPRINTF(format, ...)       do { } while (0)
  39 #endif
  40
  41 struct PCIBus {
  42     BusState qbus;
  43     int devfn_min;
  44     pci_set_irq_fn set_irq;
  45     pci_map_irq_fn map_irq;
  46     pci_hotplug_fn hotplug;
  47     uint32_t config_reg; /* XXX: suppress */
  48     void *irq_opaque;
  49     PCIDevice *devices[256];
  50     PCIDevice *parent_dev;
  51
  52     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
  53     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
  54
  55     /* The bus IRQ state is the logical OR of the connected devices.
  56        Keep a count of the number of devices with raised IRQs.  */
  57     int nirq;
  58     int *irq_count;
  59 };
  60
  61 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  62
  63 static struct BusInfo pci_bus_info = {
  64     .name       = "PCI",
  65     .size       = sizeof(PCIBus),
  66     .print_dev  = pcibus_dev_print,
  67     .props      = (Property[]) {
  68         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  69         DEFINE_PROP_END_OF_LIST()
  70     }
  71 };
  72
  73 static void pci_update_mappings(PCIDevice *d);
  74 static void pci_set_irq(void *opaque, int irq_num, int level);
  75
  76 target_phys_addr_t pci_mem_base;
  77 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  78 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  79
  80 struct PCIHostBus {
  81     int domain;
  82     struct PCIBus *bus;
  83     QLIST_ENTRY(PCIHostBus) next;
  84 };
  85 static QLIST_HEAD(, PCIHostBus) host_buses;
  86
  87 static const VMStateDescription vmstate_pcibus = {
  88     .name = "PCIBUS",
  89     .version_id = 1,
  90     .minimum_version_id = 1,
  91     .minimum_version_id_old = 1,
  92     .fields      = (VMStateField []) {
  93         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  94         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  95         VMSTATE_END_OF_LIST()
  96     }
  97 };
  98
  99 static int pci_bar(PCIDevice *d, int reg)
 100 {
 101     uint8_t type;
 102
 103     if (reg != PCI_ROM_SLOT)
 104         return PCI_BASE_ADDRESS_0 + reg * 4;
 105
 106     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 107     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
 108 }
 109
 110 static void pci_device_reset(PCIDevice *dev)
 111 {
 112     int r;
 113
 114     memset(dev->irq_state, 0, sizeof dev->irq_state);
 115     dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 116                                   PCI_COMMAND_MASTER);
 117     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 118     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 119     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 120         if (!dev->io_regions[r].size) {
 121             continue;
 122         }
 123         pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
 124     }
 125     pci_update_mappings(dev);
 126 }
 127
 128 static void pci_bus_reset(void *opaque)
 129 {
 130     PCIBus *bus = opaque;
 131     int i;
 132
 133     for (i = 0; i < bus->nirq; i++) {
 134         bus->irq_count[i] = 0;
 135     }
 136     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 137         if (bus->devices[i]) {
 138             pci_device_reset(bus->devices[i]);
 139         }
 140     }
 141 }
 142
 143 static void pci_host_bus_register(int domain, PCIBus *bus)
 144 {
 145     struct PCIHostBus *host;
 146     host = qemu_mallocz(sizeof(*host));
 147     host->domain = domain;
 148     host->bus = bus;
 149     QLIST_INSERT_HEAD(&host_buses, host, next);
 150 }
 151
 152 PCIBus *pci_find_host_bus(int domain)
 153 {
 154     struct PCIHostBus *host;
 155
 156     QLIST_FOREACH(host, &host_buses, next) {
 157         if (host->domain == domain) {
 158             return host->bus;
 159         }
 160     }
 161
 162     return NULL;
 163 }
 164
 165 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 166                          const char *name, int devfn_min)
 167 {
 168     static int nbus = 0;
 169
 170     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 171     bus->devfn_min = devfn_min;
 172
 173     /* host bridge */
 174     QLIST_INIT(&bus->child);
 175     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 176
 177     vmstate_register(nbus++, &vmstate_pcibus, bus);
 178     qemu_register_reset(pci_bus_reset, bus);
 179 }
 180
 181 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 182 {
 183     PCIBus *bus;
 184
 185     bus = qemu_mallocz(sizeof(*bus));
 186     bus->qbus.qdev_allocated = 1;
 187     pci_bus_new_inplace(bus, parent, name, devfn_min);
 188     return bus;
 189 }
 190
 191 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 192                   void *irq_opaque, int nirq)
 193 {
 194     bus->set_irq = set_irq;
 195     bus->map_irq = map_irq;
 196     bus->irq_opaque = irq_opaque;
 197     bus->nirq = nirq;
 198     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 199 }
 200
 201 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 202 {
 203     bus->qbus.allow_hotplug = 1;
 204     bus->hotplug = hotplug;
 205 }
 206
 207 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 208                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 209                          void *irq_opaque, int devfn_min, int nirq)
 210 {
 211     PCIBus *bus;
 212
 213     bus = pci_bus_new(parent, name, devfn_min);
 214     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 215     return bus;
 216 }
 217
 218 static void pci_register_secondary_bus(PCIBus *parent,
 219                                        PCIBus *bus,
 220                                        PCIDevice *dev,
 221                                        pci_map_irq_fn map_irq,
 222                                        const char *name)
 223 {
 224     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 225     bus->map_irq = map_irq;
 226     bus->parent_dev = dev;
 227
 228     QLIST_INIT(&bus->child);
 229     QLIST_INSERT_HEAD(&parent->child, bus, sibling);
 230 }
 231
 232 static void pci_unregister_secondary_bus(PCIBus *bus)
 233 {
 234     assert(QLIST_EMPTY(&bus->child));
 235     QLIST_REMOVE(bus, sibling);
 236 }
 237
 238 int pci_bus_num(PCIBus *s)
 239 {
 240     if (!s->parent_dev)
 241         return 0;       /* pci host bridge */
 242     return s->parent_dev->config[PCI_SECONDARY_BUS];
 243 }
 244
 245 static uint8_t pci_sub_bus(PCIBus *s)
 246 {
 247     if (!s->parent_dev)
 248         return 255;     /* pci host bridge */
 249     return s->parent_dev->config[PCI_SUBORDINATE_BUS];
 250 }
 251
 252 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 253 {
 254     PCIDevice *s = container_of(pv, PCIDevice, config);
 255     uint8_t *config;
 256     int i;
 257
 258     assert(size == pci_config_size(s));
 259     config = qemu_malloc(size);
 260
 261     qemu_get_buffer(f, config, size);
 262     for (i = 0; i < size; ++i) {
 263         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
 264             qemu_free(config);
 265             return -EINVAL;
 266         }
 267     }
 268     memcpy(s->config, config, size);
 269
 270     pci_update_mappings(s);
 271
 272     qemu_free(config);
 273     return 0;
 274 }
 275
 276 /* just put buffer */
 277 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 278 {
 279     const uint8_t **v = pv;
 280     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 281     qemu_put_buffer(f, *v, size);
 282 }
 283
 284 static VMStateInfo vmstate_info_pci_config = {
 285     .name = "pci config",
 286     .get  = get_pci_config_device,
 287     .put  = put_pci_config_device,
 288 };
 289
 290 const VMStateDescription vmstate_pci_device = {
 291     .name = "PCIDevice",
 292     .version_id = 2,
 293     .minimum_version_id = 1,
 294     .minimum_version_id_old = 1,
 295     .fields      = (VMStateField []) {
 296         VMSTATE_INT32_LE(version_id, PCIDevice),
 297         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 298                                    vmstate_info_pci_config,
 299                                    PCI_CONFIG_SPACE_SIZE),
 300         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
 301         VMSTATE_END_OF_LIST()
 302     }
 303 };
 304
 305 const VMStateDescription vmstate_pcie_device = {
 306     .name = "PCIDevice",
 307     .version_id = 2,
 308     .minimum_version_id = 1,
 309     .minimum_version_id_old = 1,
 310     .fields      = (VMStateField []) {
 311         VMSTATE_INT32_LE(version_id, PCIDevice),
 312         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 313                                    vmstate_info_pci_config,
 314                                    PCIE_CONFIG_SPACE_SIZE),
 315         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
 316         VMSTATE_END_OF_LIST()
 317     }
 318 };
 319
 320 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 321 {
 322     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 323 }
 324
 325 void pci_device_save(PCIDevice *s, QEMUFile *f)
 326 {
 327     vmstate_save_state(f, pci_get_vmstate(s), s);
 328 }
 329
 330 int pci_device_load(PCIDevice *s, QEMUFile *f)
 331 {
 332     return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 333 }
 334
 335 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 336 {
 337     uint16_t *id;
 338
 339     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 340     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 341     id[1] = cpu_to_le16(pci_default_sub_device_id);
 342     return 0;
 343 }
 344
 345 /*
 346  * Parse pci address in qemu command
 347  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 348  */
 349 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 350 {
 351     const char *p;
 352     char *e;
 353     unsigned long val;
 354     unsigned long dom = 0, bus = 0;
 355     unsigned slot = 0;
 356
 357     p = addr;
 358     val = strtoul(p, &e, 16);
 359     if (e == p)
 360         return -1;
 361     if (*e == ':') {
 362         bus = val;
 363         p = e + 1;
 364         val = strtoul(p, &e, 16);
 365         if (e == p)
 366             return -1;
 367         if (*e == ':') {
 368             dom = bus;
 369             bus = val;
 370             p = e + 1;
 371             val = strtoul(p, &e, 16);
 372             if (e == p)
 373                 return -1;
 374         }
 375     }
 376
 377     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 378         return -1;
 379
 380     slot = val;
 381
 382     if (*e)
 383         return -1;
 384
 385     /* Note: QEMU doesn't implement domains other than 0 */
 386     if (!pci_find_bus(pci_find_host_bus(dom), bus))
 387         return -1;
 388
 389     *domp = dom;
 390     *busp = bus;
 391     *slotp = slot;
 392     return 0;
 393 }
 394
 395 /*
 396  * Parse device bdf in device assignment command:
 397  *
 398  * -pcidevice host=bus:dev.func
 399  *
 400  * Parse <bus>:<slot>.<func> return -1 on error
 401  */
 402 int pci_parse_host_devaddr(const char *addr, int *busp,
 403                            int *slotp, int *funcp)
 404 {
 405     const char *p;
 406     char *e;
 407     int val;
 408     int bus = 0, slot = 0, func = 0;
 409
 410     p = addr;
 411     val = strtoul(p, &e, 16);
 412     if (e == p)
 413         return -1;
 414     if (*e == ':') {
 415         bus = val;
 416         p = e + 1;
 417         val = strtoul(p, &e, 16);
 418         if (e == p)
 419             return -1;
 420         if (*e == '.') {
 421             slot = val;
 422             p = e + 1;
 423             val = strtoul(p, &e, 16);
 424             if (e == p)
 425                 return -1;
 426             func = val;
 427         } else
 428             return -1;
 429     } else
 430         return -1;
 431
 432     if (bus > 0xff || slot > 0x1f || func > 0x7)
 433         return -1;
 434
 435     if (*e)
 436         return -1;
 437
 438     *busp = bus;
 439     *slotp = slot;
 440     *funcp = func;
 441     return 0;
 442 }
 443
 444 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 445                      unsigned *slotp)
 446 {
 447     /* strip legacy tag */
 448     if (!strncmp(addr, "pci_addr=", 9)) {
 449         addr += 9;
 450     }
 451     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 452         monitor_printf(mon, "Invalid pci address\n");
 453         return -1;
 454     }
 455     return 0;
 456 }
 457
 458 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 459 {
 460     int dom, bus;
 461     unsigned slot;
 462
 463     if (!devaddr) {
 464         *devfnp = -1;
 465         return pci_find_bus(pci_find_host_bus(0), 0);
 466     }
 467
 468     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 469         return NULL;
 470     }
 471
 472     *devfnp = slot << 3;
 473     return pci_find_bus(pci_find_host_bus(0), bus);
 474 }
 475
 476 static void pci_init_cmask(PCIDevice *dev)
 477 {
 478     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 479     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 480     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 481     dev->cmask[PCI_REVISION_ID] = 0xff;
 482     dev->cmask[PCI_CLASS_PROG] = 0xff;
 483     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 484     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 485     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 486 }
 487
 488 static void pci_init_wmask(PCIDevice *dev)
 489 {
 490     int i;
 491     int config_size = pci_config_size(dev);
 492
 493     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 494     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 495     pci_set_word(dev->wmask + PCI_COMMAND,
 496                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 497     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
 498         dev->wmask[i] = 0xff;
 499 }
 500
 501 static void pci_init_wmask_bridge(PCIDevice *d)
 502 {
 503     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 504        PCI_SEC_LETENCY_TIMER */
 505     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 506
 507     /* base and limit */
 508     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 509     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 510     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 511                  PCI_MEMORY_RANGE_MASK & 0xffff);
 512     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 513                  PCI_MEMORY_RANGE_MASK & 0xffff);
 514     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 515                  PCI_PREF_RANGE_MASK & 0xffff);
 516     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 517                  PCI_PREF_RANGE_MASK & 0xffff);
 518
 519     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 520     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 521
 522     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 523 }
 524
 525 static void pci_config_alloc(PCIDevice *pci_dev)
 526 {
 527     int config_size = pci_config_size(pci_dev);
 528
 529     pci_dev->config = qemu_mallocz(config_size);
 530     pci_dev->cmask = qemu_mallocz(config_size);
 531     pci_dev->wmask = qemu_mallocz(config_size);
 532     pci_dev->used = qemu_mallocz(config_size);
 533 }
 534
 535 static void pci_config_free(PCIDevice *pci_dev)
 536 {
 537     qemu_free(pci_dev->config);
 538     qemu_free(pci_dev->cmask);
 539     qemu_free(pci_dev->wmask);
 540     qemu_free(pci_dev->used);
 541 }
 542
 543 /* -1 for devfn means auto assign */
 544 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 545                                          const char *name, int devfn,
 546                                          PCIConfigReadFunc *config_read,
 547                                          PCIConfigWriteFunc *config_write,
 548                                          uint8_t header_type)
 549 {
 550     if (devfn < 0) {
 551         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 552             if (!bus->devices[devfn])
 553                 goto found;
 554         }
 555         hw_error("PCI: no devfn available for %s, all in use\n", name);
 556     found: ;
 557     } else if (bus->devices[devfn]) {
 558         hw_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
 559                  name, bus->devices[devfn]->name);
 560     }
 561     pci_dev->bus = bus;
 562     pci_dev->devfn = devfn;
 563     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 564     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 565     pci_config_alloc(pci_dev);
 566
 567     header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 568     if (header_type == PCI_HEADER_TYPE_NORMAL) {
 569         pci_set_default_subsystem_id(pci_dev);
 570     }
 571     pci_init_cmask(pci_dev);
 572     pci_init_wmask(pci_dev);
 573     if (header_type == PCI_HEADER_TYPE_BRIDGE) {
 574         pci_init_wmask_bridge(pci_dev);
 575     }
 576
 577     if (!config_read)
 578         config_read = pci_default_read_config;
 579     if (!config_write)
 580         config_write = pci_default_write_config;
 581     pci_dev->config_read = config_read;
 582     pci_dev->config_write = config_write;
 583     bus->devices[devfn] = pci_dev;
 584     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 585     pci_dev->version_id = 2; /* Current pci device vmstate version */
 586     return pci_dev;
 587 }
 588
 589 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 590                                int instance_size, int devfn,
 591                                PCIConfigReadFunc *config_read,
 592                                PCIConfigWriteFunc *config_write)
 593 {
 594     PCIDevice *pci_dev;
 595
 596     pci_dev = qemu_mallocz(instance_size);
 597     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 598                                      config_read, config_write,
 599                                      PCI_HEADER_TYPE_NORMAL);
 600     return pci_dev;
 601 }
 602 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 603 {
 604     return addr + pci_mem_base;
 605 }
 606
 607 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 608 {
 609     PCIIORegion *r;
 610     int i;
 611
 612     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 613         r = &pci_dev->io_regions[i];
 614         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 615             continue;
 616         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 617             isa_unassign_ioport(r->addr, r->filtered_size);
 618         } else {
 619             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 620                                                      r->filtered_size,
 621                                                      IO_MEM_UNASSIGNED);
 622         }
 623     }
 624 }
 625
 626 static int pci_unregister_device(DeviceState *dev)
 627 {
 628     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 629     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 630     int ret = 0;
 631
 632     if (info->exit)
 633         ret = info->exit(pci_dev);
 634     if (ret)
 635         return ret;
 636
 637     pci_unregister_io_regions(pci_dev);
 638
 639     qemu_free_irqs(pci_dev->irq);
 640     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 641     pci_config_free(pci_dev);
 642     return 0;
 643 }
 644
 645 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 646                             pcibus_t size, int type,
 647                             PCIMapIORegionFunc *map_func)
 648 {
 649     PCIIORegion *r;
 650     uint32_t addr;
 651     pcibus_t wmask;
 652
 653     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 654         return;
 655
 656     if (size & (size-1)) {
 657         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 658                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 659         exit(1);
 660     }
 661
 662     r = &pci_dev->io_regions[region_num];
 663     r->addr = PCI_BAR_UNMAPPED;
 664     r->size = size;
 665     r->filtered_size = size;
 666     r->type = type;
 667     r->map_func = map_func;
 668
 669     wmask = ~(size - 1);
 670     addr = pci_bar(pci_dev, region_num);
 671     if (region_num == PCI_ROM_SLOT) {
 672         /* ROM enable bit is writeable */
 673         wmask |= PCI_ROM_ADDRESS_ENABLE;
 674     }
 675     pci_set_long(pci_dev->config + addr, type);
 676     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 677         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 678         pci_set_quad(pci_dev->wmask + addr, wmask);
 679         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 680     } else {
 681         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 682         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 683     }
 684 }
 685
 686 static uint32_t pci_config_get_io_base(PCIDevice *d,
 687                                        uint32_t base, uint32_t base_upper16)
 688 {
 689     uint32_t val;
 690
 691     val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
 692     if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
 693         val |= (uint32_t)pci_get_word(d->config + PCI_IO_BASE_UPPER16) << 16;
 694     }
 695     return val;
 696 }
 697
 698 static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
 699 {
 700     return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
 701         << 16;
 702 }
 703
 704 static uint64_t pci_config_get_pref_base(PCIDevice *d,
 705                                          uint32_t base, uint32_t upper)
 706 {
 707     uint64_t val;
 708     val = ((uint64_t)pci_get_word(d->config + base) &
 709            PCI_PREF_RANGE_MASK) << 16;
 710     val |= (uint64_t)pci_get_long(d->config + upper) << 32;
 711     return val;
 712 }
 713
 714 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
 715 {
 716     pcibus_t base;
 717     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 718         base = pci_config_get_io_base(bridge,
 719                                       PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 720     } else {
 721         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 722             base = pci_config_get_pref_base(
 723                 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 724         } else {
 725             base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 726         }
 727     }
 728
 729     return base;
 730 }
 731
 732 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
 733 {
 734     pcibus_t limit;
 735     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 736         limit = pci_config_get_io_base(bridge,
 737                                       PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 738         limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 739     } else {
 740         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 741             limit = pci_config_get_pref_base(
 742                 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 743         } else {
 744             limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 745         }
 746         limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 747     }
 748     return limit;
 749 }
 750
 751 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 752                               uint8_t type)
 753 {
 754     pcibus_t base = *addr;
 755     pcibus_t limit = *addr + *size - 1;
 756     PCIDevice *br;
 757
 758     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 759         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 760
 761         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 762             if (!(cmd & PCI_COMMAND_IO)) {
 763                 goto no_map;
 764             }
 765         } else {
 766             if (!(cmd & PCI_COMMAND_MEMORY)) {
 767                 goto no_map;
 768             }
 769         }
 770
 771         base = MAX(base, pci_bridge_get_base(br, type));
 772         limit = MIN(limit, pci_bridge_get_limit(br, type));
 773     }
 774
 775     if (base > limit) {
 776     no_map:
 777         *addr = PCI_BAR_UNMAPPED;
 778         *size = 0;
 779     } else {
 780         *addr = base;
 781         *size = limit - base + 1;
 782     }
 783 }
 784
 785 static void pci_update_mappings(PCIDevice *d)
 786 {
 787     PCIIORegion *r;
 788     int cmd, i;
 789     pcibus_t last_addr, new_addr;
 790     pcibus_t filtered_size;
 791
 792     cmd = pci_get_word(d->config + PCI_COMMAND);
 793     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 794         r = &d->io_regions[i];
 795
 796         /* this region isn't registered */
 797         if (r->size == 0)
 798             continue;
 799
 800         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 801             if (cmd & PCI_COMMAND_IO) {
 802                 new_addr = pci_get_long(d->config + pci_bar(d, i));
 803                 new_addr = new_addr & ~(r->size - 1);
 804                 last_addr = new_addr + r->size - 1;
 805                 /* NOTE: we have only 64K ioports on PC */
 806                 if (last_addr <= new_addr || new_addr == 0 ||
 807                     last_addr >= 0x10000) {
 808                     new_addr = PCI_BAR_UNMAPPED;
 809                 }
 810             } else {
 811                 new_addr = PCI_BAR_UNMAPPED;
 812             }
 813         } else {
 814             if (cmd & PCI_COMMAND_MEMORY) {
 815                 if (r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 816                     new_addr = pci_get_quad(d->config + pci_bar(d, i));
 817                 } else {
 818                     new_addr = pci_get_long(d->config + pci_bar(d, i));
 819                 }
 820                 /* the ROM slot has a specific enable bit */
 821                 if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
 822                     goto no_mem_map;
 823                 new_addr = new_addr & ~(r->size - 1);
 824                 last_addr = new_addr + r->size - 1;
 825                 /* NOTE: we do not support wrapping */
 826                 /* XXX: as we cannot support really dynamic
 827                    mappings, we handle specific values as invalid
 828                    mappings. */
 829                 if (last_addr <= new_addr || new_addr == 0 ||
 830                     last_addr == PCI_BAR_UNMAPPED ||
 831
 832                     /* Now pcibus_t is 64bit.
 833                      * Check if 32 bit BAR wrap around explicitly.
 834                      * Without this, PC ide doesn't work well.
 835                      * TODO: remove this work around.
 836                      */
 837                     (!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) &&
 838                      last_addr >= UINT32_MAX) ||
 839
 840                     /*
 841                      * OS is allowed to set BAR beyond its addressable
 842                      * bits. For example, 32 bit OS can set 64bit bar
 843                      * to >4G. Check it.
 844                      */
 845                     last_addr >= TARGET_PHYS_ADDR_MAX) {
 846                     new_addr = PCI_BAR_UNMAPPED;
 847                 }
 848             } else {
 849             no_mem_map:
 850                 new_addr = PCI_BAR_UNMAPPED;
 851             }
 852         }
 853
 854         /* bridge filtering */
 855         filtered_size = r->size;
 856         if (new_addr != PCI_BAR_UNMAPPED) {
 857             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 858         }
 859
 860         /* This bar isn't changed */
 861         if (new_addr == r->addr && filtered_size == r->filtered_size)
 862             continue;
 863
 864         /* now do the real mapping */
 865         if (r->addr != PCI_BAR_UNMAPPED) {
 866             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 867                 int class;
 868                 /* NOTE: specific hack for IDE in PC case:
 869                    only one byte must be mapped. */
 870                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 871                 if (class == 0x0101 && r->size == 4) {
 872                     isa_unassign_ioport(r->addr + 2, 1);
 873                 } else {
 874                     isa_unassign_ioport(r->addr, r->filtered_size);
 875                 }
 876             } else {
 877                 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 878                                              r->filtered_size,
 879                                              IO_MEM_UNASSIGNED);
 880                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 881             }
 882         }
 883         r->addr = new_addr;
 884         r->filtered_size = filtered_size;
 885         if (r->addr != PCI_BAR_UNMAPPED) {
 886             /*
 887              * TODO: currently almost all the map funcions assumes
 888              * filtered_size == size and addr & ~(size - 1) == addr.
 889              * However with bridge filtering, they aren't always true.
 890              * Teach them such cases, such that filtered_size < size and
 891              * addr & (size - 1) != 0.
 892              */
 893             r->map_func(d, i, r->addr, r->filtered_size, r->type);
 894         }
 895     }
 896 }
 897
 898 static uint32_t pci_read_config(PCIDevice *d,
 899                                 uint32_t address, int len)
 900 {
 901     uint32_t val = 0;
 902     assert(len == 1 || len == 2 || len == 4);
 903     len = MIN(len, pci_config_size(d) - address);
 904     memcpy(&val, d->config + address, len);
 905     return le32_to_cpu(val);
 906 }
 907
 908 static void pci_write_config(PCIDevice *pci_dev,
 909                              uint32_t address, uint32_t val, int len)
 910 {
 911     int i;
 912     for (i = 0; i < len; i++) {
 913         pci_dev->config[address + i] = val & 0xff;
 914         val >>= 8;
 915     }
 916 }
 917
 918 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len)
 919 {
 920     if (pci_dev->cap.supported && address >= pci_dev->cap.start &&
 921             (address + len) < pci_dev->cap.start + pci_dev->cap.length)
 922         return 1;
 923     return 0;
 924 }
 925
 926 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 927                                      uint32_t address, int len)
 928 {
 929     return pci_read_config(pci_dev, address, len);
 930 }
 931
 932 void pci_default_cap_write_config(PCIDevice *pci_dev,
 933                                   uint32_t address, uint32_t val, int len)
 934 {
 935     pci_write_config(pci_dev, address, val, len);
 936 }
 937
 938 uint32_t pci_default_read_config(PCIDevice *d,
 939                                  uint32_t address, int len)
 940 {
 941     if (pci_access_cap_config(d, address, len))
 942         return d->cap.config_read(d, address, len);
 943
 944     return pci_read_config(d, address, len);
 945 }
 946
 947 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 948 {
 949     int i;
 950     uint32_t config_size = pci_config_size(d);
 951
 952     if (pci_access_cap_config(d, addr, l)) {
 953         d->cap.config_write(d, addr, val, l);
 954         return;
 955     }
 956
 957     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
 958         uint8_t wmask = d->wmask[addr + i];
 959         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
 960     }
 961
 962 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
 963     if (kvm_enabled() && kvm_irqchip_in_kernel() &&
 964         addr >= PIIX_CONFIG_IRQ_ROUTE &&
 965         addr < PIIX_CONFIG_IRQ_ROUTE + 4)
 966         assigned_dev_update_irqs();
 967 #endif /* CONFIG_KVM_DEVICE_ASSIGNMENT */
 968
 969     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
 970         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
 971         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
 972         range_covers_byte(addr, l, PCI_COMMAND))
 973         pci_update_mappings(d);
 974
 975 }
 976
 977 /***********************************************************/
 978 /* generic PCI irq support */
 979
 980 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 981 static void pci_set_irq(void *opaque, int irq_num, int level)
 982 {
 983     PCIDevice *pci_dev = opaque;
 984     PCIBus *bus;
 985     int change;
 986
 987     change = level - pci_dev->irq_state[irq_num];
 988     if (!change)
 989         return;
 990
 991     pci_dev->irq_state[irq_num] = level;
 992
 993 #if defined(TARGET_IA64)
 994     ioapic_set_irq(pci_dev, irq_num, level);
 995 #endif
 996
 997     for (;;) {
 998         bus = pci_dev->bus;
 999         irq_num = bus->map_irq(pci_dev, irq_num);
1000         if (bus->set_irq)
1001             break;
1002         pci_dev = bus->parent_dev;
1003     }
1004     bus->irq_count[irq_num] += change;
1005     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
1006 }
1007
1008 int pci_map_irq(PCIDevice *pci_dev, int pin)
1009 {
1010     return pci_dev->bus->map_irq(pci_dev, pin);
1011 }
1012
1013 /***********************************************************/
1014 /* monitor info on PCI */
1015
1016 typedef struct {
1017     uint16_t class;
1018     const char *desc;
1019 } pci_class_desc;
1020
1021 static const pci_class_desc pci_class_descriptions[] =
1022 {
1023     { 0x0100, "SCSI controller"},
1024     { 0x0101, "IDE controller"},
1025     { 0x0102, "Floppy controller"},
1026     { 0x0103, "IPI controller"},
1027     { 0x0104, "RAID controller"},
1028     { 0x0106, "SATA controller"},
1029     { 0x0107, "SAS controller"},
1030     { 0x0180, "Storage controller"},
1031     { 0x0200, "Ethernet controller"},
1032     { 0x0201, "Token Ring controller"},
1033     { 0x0202, "FDDI controller"},
1034     { 0x0203, "ATM controller"},
1035     { 0x0280, "Network controller"},
1036     { 0x0300, "VGA controller"},
1037     { 0x0301, "XGA controller"},
1038     { 0x0302, "3D controller"},
1039     { 0x0380, "Display controller"},
1040     { 0x0400, "Video controller"},
1041     { 0x0401, "Audio controller"},
1042     { 0x0402, "Phone"},
1043     { 0x0480, "Multimedia controller"},
1044     { 0x0500, "RAM controller"},
1045     { 0x0501, "Flash controller"},
1046     { 0x0580, "Memory controller"},
1047     { 0x0600, "Host bridge"},
1048     { 0x0601, "ISA bridge"},
1049     { 0x0602, "EISA bridge"},
1050     { 0x0603, "MC bridge"},
1051     { 0x0604, "PCI bridge"},
1052     { 0x0605, "PCMCIA bridge"},
1053     { 0x0606, "NUBUS bridge"},
1054     { 0x0607, "CARDBUS bridge"},
1055     { 0x0608, "RACEWAY bridge"},
1056     { 0x0680, "Bridge"},
1057     { 0x0c03, "USB controller"},
1058     { 0, NULL}
1059 };
1060
1061 static void pci_info_device(PCIBus *bus, PCIDevice *d)
1062 {
1063     Monitor *mon = cur_mon;
1064     int i, class;
1065     PCIIORegion *r;
1066     const pci_class_desc *desc;
1067
1068     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
1069                    pci_bus_num(d->bus),
1070                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1071     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1072     monitor_printf(mon, "    ");
1073     desc = pci_class_descriptions;
1074     while (desc->desc && class != desc->class)
1075         desc++;
1076     if (desc->desc) {
1077         monitor_printf(mon, "%s", desc->desc);
1078     } else {
1079         monitor_printf(mon, "Class %04x", class);
1080     }
1081     monitor_printf(mon, ": PCI device %04x:%04x\n",
1082            pci_get_word(d->config + PCI_VENDOR_ID),
1083            pci_get_word(d->config + PCI_DEVICE_ID));
1084
1085     if (d->config[PCI_INTERRUPT_PIN] != 0) {
1086         monitor_printf(mon, "      IRQ %d.\n",
1087                        d->config[PCI_INTERRUPT_LINE]);
1088     }
1089     if (class == 0x0604) {
1090         uint64_t base;
1091         uint64_t limit;
1092
1093         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
1094         monitor_printf(mon, "      secondary bus %d.\n",
1095                        d->config[PCI_SECONDARY_BUS]);
1096         monitor_printf(mon, "      subordinate bus %d.\n",
1097                        d->config[PCI_SUBORDINATE_BUS]);
1098
1099         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO);
1100         limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO);
1101         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1102                        base, limit);
1103
1104         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
1105         limit= pci_config_get_memory_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
1106         monitor_printf(mon,
1107                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1108                        base, limit);
1109
1110         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1111                                    PCI_BASE_ADDRESS_MEM_PREFETCH);
1112         limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1113                                      PCI_BASE_ADDRESS_MEM_PREFETCH);
1114         monitor_printf(mon, "      prefetchable memory range "
1115                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit);
1116     }
1117     for(i = 0;i < PCI_NUM_REGIONS; i++) {
1118         r = &d->io_regions[i];
1119         if (r->size != 0) {
1120             monitor_printf(mon, "      BAR%d: ", i);
1121             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1122                 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1123                                " [0x%04"FMT_PCIBUS"].\n",
1124                                r->addr, r->addr + r->size - 1);
1125             } else {
1126                 const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
1127                     "64 bit" : "32 bit";
1128                 const char *prefetch =
1129                     r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
1130                     " prefetchable" : "";
1131
1132                 monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
1133                                " [0x%08"FMT_PCIBUS"].\n",
1134                                type, prefetch,
1135                                r->addr, r->addr + r->size - 1);
1136             }
1137         }
1138     }
1139     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
1140     if (class == 0x0604 && d->config[0x19] != 0) {
1141         pci_for_each_device(bus, d->config[0x19], pci_info_device);
1142     }
1143 }
1144
1145 static void pci_for_each_device_under_bus(PCIBus *bus,
1146                                           void (*fn)(PCIBus *b, PCIDevice *d))
1147 {
1148     PCIDevice *d;
1149     int devfn;
1150
1151     for(devfn = 0; devfn < 256; devfn++) {
1152         d = bus->devices[devfn];
1153         if (d)
1154             fn(bus, d);
1155     }
1156 }
1157
1158 void pci_for_each_device(PCIBus *bus, int bus_num,
1159                          void (*fn)(PCIBus *b, PCIDevice *d))
1160 {
1161     bus = pci_find_bus(bus, bus_num);
1162
1163     if (bus) {
1164         pci_for_each_device_under_bus(bus, fn);
1165     }
1166 }
1167
1168 void pci_info(Monitor *mon)
1169 {
1170     struct PCIHostBus *host;
1171     QLIST_FOREACH(host, &host_buses, next) {
1172         pci_for_each_device(host->bus, 0, pci_info_device);
1173     }
1174 }
1175
1176 static const char * const pci_nic_models[] = {
1177     "ne2k_pci",
1178     "i82551",
1179     "i82557b",
1180     "i82559er",
1181     "rtl8139",
1182     "e1000",
1183     "pcnet",
1184     "virtio",
1185     NULL
1186 };
1187
1188 static const char * const pci_nic_names[] = {
1189     "ne2k_pci",
1190     "i82551",
1191     "i82557b",
1192     "i82559er",
1193     "rtl8139",
1194     "e1000",
1195     "pcnet",
1196     "virtio-net-pci",
1197     NULL
1198 };
1199
1200 /* Initialize a PCI NIC.  */
1201 /* FIXME callers should check for failure, but don't */
1202 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1203                         const char *default_devaddr)
1204 {
1205     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1206     PCIBus *bus;
1207     int devfn;
1208     PCIDevice *pci_dev;
1209     DeviceState *dev;
1210     int i;
1211
1212     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1213     if (i < 0)
1214         return NULL;
1215
1216     bus = pci_get_bus_devfn(&devfn, devaddr);
1217     if (!bus) {
1218         qemu_error("Invalid PCI device address %s for device %s\n",
1219                    devaddr, pci_nic_names[i]);
1220         return NULL;
1221     }
1222
1223     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1224     dev = &pci_dev->qdev;
1225     if (nd->name)
1226         dev->id = qemu_strdup(nd->name);
1227     qdev_set_nic_properties(dev, nd);
1228     if (qdev_init(dev) < 0)
1229         return NULL;
1230     return pci_dev;
1231 }
1232
1233 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1234                                const char *default_devaddr)
1235 {
1236     PCIDevice *res;
1237
1238     if (qemu_show_nic_models(nd->model, pci_nic_models))
1239         exit(0);
1240
1241     res = pci_nic_init(nd, default_model, default_devaddr);
1242     if (!res)
1243         exit(1);
1244     return res;
1245 }
1246
1247 typedef struct {
1248     PCIDevice dev;
1249     PCIBus bus;
1250     uint32_t vid;
1251     uint32_t did;
1252 } PCIBridge;
1253
1254
1255 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1256 {
1257     pci_update_mappings(d);
1258 }
1259
1260 static void pci_bridge_update_mappings(PCIBus *b)
1261 {
1262     PCIBus *child;
1263
1264     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1265
1266     QLIST_FOREACH(child, &b->child, sibling) {
1267         pci_bridge_update_mappings(child);
1268     }
1269 }
1270
1271 static void pci_bridge_write_config(PCIDevice *d,
1272                              uint32_t address, uint32_t val, int len)
1273 {
1274     pci_default_write_config(d, address, val, len);
1275
1276     if (/* io base/limit */
1277         ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1278
1279         /* memory base/limit, prefetchable base/limit and
1280            io base/limit upper 16 */
1281         ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1282         pci_bridge_update_mappings(d->bus);
1283     }
1284 }
1285
1286 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1287 {
1288     PCIBus *sec;
1289
1290     if (!bus)
1291         return NULL;
1292
1293     if (pci_bus_num(bus) == bus_num) {
1294         return bus;
1295     }
1296
1297     /* try child bus */
1298     QLIST_FOREACH(sec, &bus->child, sibling) {
1299         if (pci_bus_num(sec) <= bus_num && bus_num <= pci_sub_bus(sec)) {
1300             return pci_find_bus(sec, bus_num);
1301         }
1302     }
1303
1304     return NULL;
1305 }
1306
1307 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1308 {
1309     bus = pci_find_bus(bus, bus_num);
1310
1311     if (!bus)
1312         return NULL;
1313
1314     return bus->devices[PCI_DEVFN(slot, function)];
1315 }
1316
1317 static int pci_bridge_initfn(PCIDevice *dev)
1318 {
1319     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1320
1321     pci_config_set_vendor_id(s->dev.config, s->vid);
1322     pci_config_set_device_id(s->dev.config, s->did);
1323
1324     /* TODO: intial value
1325      * command register:
1326      * According to PCI bridge spec, after reset
1327      *   bus master bit is off
1328      *   memory space enable bit is off
1329      * According to manual (805-1251.pdf).(See abp_pbi.c for its links.)
1330      *   the reset value should be zero unless the boot pin is tied high
1331      *   (which is tru) and thus it should be PCI_COMMAND_MEMORY.
1332      *
1333      * For now, don't touch the value.
1334      * Later command register will be set to zero and apb_pci.c will
1335      * override the value.
1336      * Same for latency timer, and multi function bit of header type.
1337      */
1338     pci_set_word(dev->config + PCI_COMMAND,
1339                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1340
1341     pci_set_word(dev->config + PCI_STATUS,
1342                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1343     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1344     dev->config[PCI_LATENCY_TIMER] = 0x10;
1345     dev->config[PCI_HEADER_TYPE] =
1346         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE;
1347     pci_set_word(dev->config + PCI_SEC_STATUS,
1348                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1349     return 0;
1350 }
1351
1352 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1353 {
1354     PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1355     PCIBus *bus = &s->bus;
1356     pci_unregister_secondary_bus(bus);
1357     return 0;
1358 }
1359
1360 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1361                         pci_map_irq_fn map_irq, const char *name)
1362 {
1363     PCIDevice *dev;
1364     PCIBridge *s;
1365
1366     dev = pci_create(bus, devfn, "pci-bridge");
1367     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1368     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1369     qdev_init_nofail(&dev->qdev);
1370
1371     s = DO_UPCAST(PCIBridge, dev, dev);
1372     pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1373     return &s->bus;
1374 }
1375
1376 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1377 {
1378     PCIDevice *pci_dev = (PCIDevice *)qdev;
1379     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1380     PCIBus *bus;
1381     int devfn, rc;
1382
1383     /* initialize cap_present for pci_is_express() and pci_config_size() */
1384     if (info->is_express) {
1385         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1386     }
1387
1388     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1389     devfn = pci_dev->devfn;
1390     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1391                                      info->config_read, info->config_write,
1392                                      info->header_type);
1393     rc = info->init(pci_dev);
1394     if (rc != 0)
1395         return rc;
1396     if (qdev->hotplugged)
1397         bus->hotplug(pci_dev, 1);
1398     return 0;
1399 }
1400
1401 static int pci_unplug_device(DeviceState *qdev)
1402 {
1403     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1404
1405     dev->bus->hotplug(dev, 0);
1406     return 0;
1407 }
1408
1409 void pci_qdev_register(PCIDeviceInfo *info)
1410 {
1411     info->qdev.init = pci_qdev_init;
1412     info->qdev.unplug = pci_unplug_device;
1413     info->qdev.exit = pci_unregister_device;
1414     info->qdev.bus_info = &pci_bus_info;
1415     qdev_register(&info->qdev);
1416 }
1417
1418 void pci_qdev_register_many(PCIDeviceInfo *info)
1419 {
1420     while (info->qdev.name) {
1421         pci_qdev_register(info);
1422         info++;
1423     }
1424 }
1425
1426 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1427 {
1428     DeviceState *dev;
1429
1430     dev = qdev_create(&bus->qbus, name);
1431     qdev_prop_set_uint32(dev, "addr", devfn);
1432     return DO_UPCAST(PCIDevice, qdev, dev);
1433 }
1434
1435 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1436 {
1437     PCIDevice *dev = pci_create(bus, devfn, name);
1438     qdev_init_nofail(&dev->qdev);
1439     return dev;
1440 }
1441
1442 int pci_enable_capability_support(PCIDevice *pci_dev,
1443                                   uint32_t config_start,
1444                                   PCICapConfigReadFunc *config_read,
1445                                   PCICapConfigWriteFunc *config_write,
1446                                   PCICapConfigInitFunc *config_init)
1447 {
1448     if (!pci_dev)
1449         return -ENODEV;
1450
1451     pci_dev->config[0x06] |= 0x10; // status = capabilities
1452
1453     if (config_start == 0)
1454         pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR;
1455     else if (config_start >= 0x40 && config_start < 0xff)
1456         pci_dev->cap.start = config_start;
1457     else
1458         return -EINVAL;
1459
1460     if (config_read)
1461         pci_dev->cap.config_read = config_read;
1462     else
1463         pci_dev->cap.config_read = pci_default_cap_read_config;
1464     if (config_write)
1465         pci_dev->cap.config_write = config_write;
1466     else
1467         pci_dev->cap.config_write = pci_default_cap_write_config;
1468     pci_dev->cap.supported = 1;
1469     pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start;
1470     return config_init(pci_dev);
1471 }
1472
1473 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1474 {
1475     int config_size = pci_config_size(pdev);
1476     int offset = PCI_CONFIG_HEADER_SIZE;
1477     int i;
1478     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1479         if (pdev->used[i])
1480             offset = i + 1;
1481         else if (i - offset + 1 == size)
1482             return offset;
1483     return 0;
1484 }
1485
1486 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1487                                         uint8_t *prev_p)
1488 {
1489     uint8_t next, prev;
1490
1491     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1492         return 0;
1493
1494     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1495          prev = next + PCI_CAP_LIST_NEXT)
1496         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1497             break;
1498
1499     if (prev_p)
1500         *prev_p = prev;
1501     return next;
1502 }
1503
1504 /* Reserve space and add capability to the linked list in pci config space */
1505 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1506 {
1507     uint8_t offset = pci_find_space(pdev, size);
1508     uint8_t *config = pdev->config + offset;
1509     if (!offset)
1510         return -ENOSPC;
1511     config[PCI_CAP_LIST_ID] = cap_id;
1512     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1513     pdev->config[PCI_CAPABILITY_LIST] = offset;
1514     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1515     memset(pdev->used + offset, 0xFF, size);
1516     /* Make capability read-only by default */
1517     memset(pdev->wmask + offset, 0, size);
1518     /* Check capability by default */
1519     memset(pdev->cmask + offset, 0xFF, size);
1520     return offset;
1521 }
1522
1523 /* Unlink capability from the pci config space. */
1524 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1525 {
1526     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1527     if (!offset)
1528         return;
1529     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1530     /* Make capability writeable again */
1531     memset(pdev->wmask + offset, 0xff, size);
1532     /* Clear cmask as device-specific registers can't be checked */
1533     memset(pdev->cmask + offset, 0, size);
1534     memset(pdev->used + offset, 0, size);
1535
1536     if (!pdev->config[PCI_CAPABILITY_LIST])
1537         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1538 }
1539
1540 /* Reserve space for capability at a known offset (to call after load). */
1541 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1542 {
1543     memset(pdev->used + offset, 0xff, size);
1544 }
1545
1546 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1547 {
1548     return pci_find_capability_list(pdev, cap_id, NULL);
1549 }
1550
1551 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1552 {
1553     PCIDevice *d = (PCIDevice *)dev;
1554     const pci_class_desc *desc;
1555     char ctxt[64];
1556     PCIIORegion *r;
1557     int i, class;
1558
1559     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1560     desc = pci_class_descriptions;
1561     while (desc->desc && class != desc->class)
1562         desc++;
1563     if (desc->desc) {
1564         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1565     } else {
1566         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1567     }
1568
1569     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1570                    "pci id %04x:%04x (sub %04x:%04x)\n",
1571                    indent, "", ctxt,
1572                    d->config[PCI_SECONDARY_BUS],
1573                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1574                    pci_get_word(d->config + PCI_VENDOR_ID),
1575                    pci_get_word(d->config + PCI_DEVICE_ID),
1576                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1577                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1578     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1579         r = &d->io_regions[i];
1580         if (!r->size)
1581             continue;
1582         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1583                        " [0x%"FMT_PCIBUS"]\n",
1584                        indent, "",
1585                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1586                        r->addr, r->addr + r->size - 1);
1587     }
1588 }
1589
1590 static PCIDeviceInfo bridge_info = {
1591     .qdev.name    = "pci-bridge",
1592     .qdev.size    = sizeof(PCIBridge),
1593     .init         = pci_bridge_initfn,
1594     .exit         = pci_bridge_exitfn,
1595     .config_write = pci_bridge_write_config,
1596     .qdev.props   = (Property[]) {
1597         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1598         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1599         DEFINE_PROP_END_OF_LIST(),
1600     }
1601 };
1602
1603 static void pci_register_devices(void)
1604 {
1605     pci_qdev_register(&bridge_info);
1606 }
1607
1608 device_init(pci_register_devices)