2 * CRIS virtual CPU header
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #define TARGET_LONG_BITS 32
25 #define CPUState struct CPUCRISState
29 #define TARGET_HAS_ICE 1
31 #define ELF_MACHINE EM_CRIS
35 #define EXCP_BUSFAULT 3
39 /* Register aliases. R0 - R15 */
44 /* Support regs, P0 - P15 */
52 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
64 #define Q_FLAG 0x80000000
65 #define M_FLAG 0x40000000
66 #define PFIX_FLAG 0x800 /* CRISv10 Only. */
77 #define ALU_FLAGS 0x1F
79 /* Condition codes. */
97 #define NB_MMU_MODES 2
99 typedef struct CPUCRISState
{
101 /* P0 - P15 are referred to as special registers in the docs. */
104 /* Pseudo register for the PC. Not directly accessable on CRIS. */
107 /* Pseudo register for the kernel stack. */
115 /* Condition flag tracking. */
121 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
123 /* X flag at the time of cc snapshot. */
126 /* CRIS has certain insns that lockout interrupts. */
128 int interrupt_vector
;
132 /* FIXME: add a check in the translator to avoid writing to support
133 register sets beyond the 4th. The ISA allows up to 256! but in
134 practice there is no core that implements more than 4.
136 Support function registers are used to control units close to the
137 core. Accesses do not pass down the normal hierarchy.
139 uint32_t sregs
[4][16];
141 /* Linear feedback shift reg in the mmu. Used to provide pseudo
142 randomness for the 'hint' the mmu gives to sw for chosing valid
143 sets on TLB refills. */
144 uint32_t mmu_rand_lfsr
;
147 * We just store the stores to the tlbset here for later evaluation
148 * when the hw needs access to them.
150 * One for I and another for D.
160 /* Members after CPU_COMMON are preserved across resets. */
164 CPUCRISState
*cpu_cris_init(const char *cpu_model
);
165 int cpu_cris_exec(CPUCRISState
*s
);
166 void cpu_cris_close(CPUCRISState
*s
);
167 void do_interrupt(CPUCRISState
*env
);
168 /* you can call this signal handler from your SIGBUS and SIGSEGV
169 signal handlers to inform the virtual CPU of exceptions. non zero
170 is returned if the signal was handled by the virtual CPU. */
171 int cpu_cris_signal_handler(int host_signum
, void *pinfo
,
175 CC_OP_DYNAMIC
, /* Use env->cc_op */
202 /* CRIS uses 8k pages. */
203 #define TARGET_PAGE_BITS 13
204 #define MMAP_SHIFT TARGET_PAGE_BITS
206 #define TARGET_PHYS_ADDR_SPACE_BITS 32
207 #define TARGET_VIRT_ADDR_SPACE_BITS 32
209 #define cpu_init cpu_cris_init
210 #define cpu_exec cpu_cris_exec
211 #define cpu_gen_code cpu_cris_gen_code
212 #define cpu_signal_handler cpu_cris_signal_handler
214 #define CPU_SAVE_VERSION 1
216 /* MMU modes definitions */
217 #define MMU_MODE0_SUFFIX _kernel
218 #define MMU_MODE1_SUFFIX _user
219 #define MMU_USER_IDX 1
220 static inline int cpu_mmu_index (CPUState
*env
)
222 return !!(env
->pregs
[PR_CCS
] & U_FLAG
);
225 int cpu_cris_handle_mmu_fault(CPUState
*env
, target_ulong address
, int rw
,
226 int mmu_idx
, int is_softmmu
);
227 #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
229 #if defined(CONFIG_USER_ONLY)
230 static inline void cpu_clone_regs(CPUState
*env
, target_ulong newsp
)
233 env
->regs
[14] = newsp
;
238 static inline void cpu_set_tls(CPUCRISState
*env
, target_ulong newtls
)
240 env
->pregs
[PR_PID
] = (env
->pregs
[PR_PID
] & 0xff) | newtls
;
243 /* Support function regs. */
244 #define SFR_RW_GC_CFG 0][0
245 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
246 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
247 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
248 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
249 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
250 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
251 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
255 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
256 target_ulong
*cs_base
, int *flags
)
260 *flags
= env
->dslot
|
261 (env
->pregs
[PR_CCS
] & (S_FLAG
| P_FLAG
| U_FLAG
262 | X_FLAG
| PFIX_FLAG
));
265 #define cpu_list cris_cpu_list
266 void cris_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));