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Declare no_hpet variable for all targets
[qemu/qemu-dev-zwu.git] / qemu-kvm-x86.c
blob403337a577593b6861557a16490f0eaca7da3d29
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm.h"
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
23
24 #include "kvm.h"
25 #include "hw/apic.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 int r;
39 /*
40 * Tell fw_cfg to notify the BIOS to reserve the range.
41 */
42 if (e820_add_entry(addr, 0x4000, E820_RESERVED) < 0) {
43 perror("e820_add_entry() table is full");
44 exit(1);
45 }
46
47 r = kvm_vm_ioctl(kvm_state, KVM_SET_TSS_ADDR, addr);
48 if (r < 0) {
49 fprintf(stderr, "kvm_set_tss_addr: %m\n");
50 return r;
51 }
52 return 0;
53 }
54
55 static int kvm_init_tss(kvm_context_t kvm)
56 {
57 int r;
58
59 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfeffd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70 } else {
71 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
72 }
73 return 0;
74 }
75
76 static int kvm_set_identity_map_addr(kvm_context_t kvm, uint64_t addr)
77 {
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
79 int r;
80
81 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
82 if (r > 0) {
83 r = kvm_vm_ioctl(kvm_state, KVM_SET_IDENTITY_MAP_ADDR, &addr);
84 if (r == -1) {
85 fprintf(stderr, "kvm_set_identity_map_addr: %m\n");
86 return -errno;
87 }
88 return 0;
89 }
90 #endif
91 return -ENOSYS;
92 }
93
94 static int kvm_init_identity_map_page(kvm_context_t kvm)
95 {
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
97 int r;
98
99 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
100 if (r > 0) {
101 /*
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
104 */
105 r = kvm_set_identity_map_addr(kvm, 0xfeffc000);
106 if (r < 0) {
107 fprintf(stderr, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
109 return r;
110 }
111
112 }
113 #endif
114 return 0;
115 }
116
117 static int kvm_create_pit(kvm_context_t kvm)
118 {
119 #ifdef KVM_CAP_PIT
120 int r;
121
122 kvm_state->pit_in_kernel = 0;
123 if (!kvm->no_pit_creation) {
124 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
125 if (r > 0) {
126 r = kvm_vm_ioctl(kvm_state, KVM_CREATE_PIT);
127 if (r >= 0)
128 kvm_state->pit_in_kernel = 1;
129 else {
130 fprintf(stderr, "Create kernel PIC irqchip failed\n");
131 return r;
132 }
133 }
134 }
135 #endif
136 return 0;
137 }
138
139 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
140 void **vm_mem)
141 {
142 int r = 0;
143
144 r = kvm_init_tss(kvm);
145 if (r < 0)
146 return r;
147
148 r = kvm_init_identity_map_page(kvm);
149 if (r < 0)
150 return r;
151
152 r = kvm_create_pit(kvm);
153 if (r < 0)
154 return r;
155
156 r = kvm_init_coalesced_mmio(kvm);
157 if (r < 0)
158 return r;
159
160 return 0;
161 }
162
163 #ifdef KVM_EXIT_TPR_ACCESS
164
165 static int kvm_handle_tpr_access(CPUState *env)
166 {
167 struct kvm_run *run = env->kvm_run;
168 kvm_tpr_access_report(env,
169 run->tpr_access.rip,
170 run->tpr_access.is_write);
171 return 0;
172 }
173
174
175 int kvm_enable_vapic(CPUState *env, uint64_t vapic)
176 {
177 struct kvm_vapic_addr va = {
178 .vapic_addr = vapic,
179 };
180
181 return kvm_vcpu_ioctl(env, KVM_SET_VAPIC_ADDR, &va);
182 }
183
184 #endif
185
186 int kvm_arch_run(CPUState *env)
187 {
188 int r = 0;
189 struct kvm_run *run = env->kvm_run;
190
191
192 switch (run->exit_reason) {
193 #ifdef KVM_EXIT_SET_TPR
194 case KVM_EXIT_SET_TPR:
195 break;
196 #endif
197 #ifdef KVM_EXIT_TPR_ACCESS
198 case KVM_EXIT_TPR_ACCESS:
199 r = kvm_handle_tpr_access(env);
200 break;
201 #endif
202 default:
203 r = 1;
204 break;
205 }
206
207 return r;
208 }
209
210 #ifdef KVM_CAP_IRQCHIP
211
212 int kvm_get_lapic(CPUState *env, struct kvm_lapic_state *s)
213 {
214 int r = 0;
215
216 if (!kvm_irqchip_in_kernel())
217 return r;
218
219 r = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, s);
220 if (r < 0)
221 fprintf(stderr, "KVM_GET_LAPIC failed\n");
222 return r;
223 }
224
225 int kvm_set_lapic(CPUState *env, struct kvm_lapic_state *s)
226 {
227 int r = 0;
228
229 if (!kvm_irqchip_in_kernel())
230 return 0;
231
232 r = kvm_vcpu_ioctl(env, KVM_SET_LAPIC, s);
233
234 if (r < 0)
235 fprintf(stderr, "KVM_SET_LAPIC failed\n");
236 return r;
237 }
238
239 #endif
240
241 #ifdef KVM_CAP_PIT
242
243 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
244 {
245 if (!kvm_pit_in_kernel())
246 return 0;
247 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT, s);
248 }
249
250 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
251 {
252 if (!kvm_pit_in_kernel())
253 return 0;
254 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT, s);
255 }
256
257 #ifdef KVM_CAP_PIT_STATE2
258 int kvm_get_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
259 {
260 if (!kvm_pit_in_kernel())
261 return 0;
262 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT2, ps2);
263 }
264
265 int kvm_set_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
266 {
267 if (!kvm_pit_in_kernel())
268 return 0;
269 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT2, ps2);
270 }
271
272 #endif
273 #endif
274
275 int kvm_has_pit_state2(kvm_context_t kvm)
276 {
277 int r = 0;
278
279 #ifdef KVM_CAP_PIT_STATE2
280 r = kvm_check_extension(kvm_state, KVM_CAP_PIT_STATE2);
281 #endif
282 return r;
283 }
284
285 void kvm_show_code(CPUState *env)
286 {
287 #define SHOW_CODE_LEN 50
288 struct kvm_regs regs;
289 struct kvm_sregs sregs;
290 int r, n;
291 int back_offset;
292 unsigned char code;
293 char code_str[SHOW_CODE_LEN * 3 + 1];
294 unsigned long rip;
295
296 r = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
297 if (r < 0 ) {
298 perror("KVM_GET_SREGS");
299 return;
300 }
301 r = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
302 if (r < 0) {
303 perror("KVM_GET_REGS");
304 return;
305 }
306 rip = sregs.cs.base + regs.rip;
307 back_offset = regs.rip;
308 if (back_offset > 20)
309 back_offset = 20;
310 *code_str = 0;
311 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
312 if (n == 0)
313 strcat(code_str, " -->");
314 cpu_physical_memory_rw(rip + n, &code, 1, 1);
315 sprintf(code_str + strlen(code_str), " %02x", code);
316 }
317 fprintf(stderr, "code:%s\n", code_str);
318 }
319
320
321 /*
322 * Returns available msr list. User must free.
323 */
324 static struct kvm_msr_list *kvm_get_msr_list(void)
325 {
326 struct kvm_msr_list sizer, *msrs;
327 int r;
328
329 sizer.nmsrs = 0;
330 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, &sizer);
331 if (r < 0 && r != -E2BIG)
332 return NULL;
333 /* Old kernel modules had a bug and could write beyond the provided
334 memory. Allocate at least a safe amount of 1K. */
335 msrs = qemu_malloc(MAX(1024, sizeof(*msrs) +
336 sizer.nmsrs * sizeof(*msrs->indices)));
337
338 msrs->nmsrs = sizer.nmsrs;
339 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, msrs);
340 if (r < 0) {
341 free(msrs);
342 errno = r;
343 return NULL;
344 }
345 return msrs;
346 }
347
348 int kvm_get_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
349 {
350 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
351 int r;
352
353 kmsrs->nmsrs = n;
354 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
355 r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
356 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
357 free(kmsrs);
358 return r;
359 }
360
361 int kvm_set_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
362 {
363 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
364 int r;
365
366 kmsrs->nmsrs = n;
367 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
368 r = kvm_vcpu_ioctl(env, KVM_SET_MSRS, kmsrs);
369 free(kmsrs);
370 return r;
371 }
372
373 int kvm_get_mce_cap_supported(kvm_context_t kvm, uint64_t *mce_cap,
374 int *max_banks)
375 {
376 #ifdef KVM_CAP_MCE
377 int r;
378
379 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
380 if (r > 0) {
381 *max_banks = r;
382 return kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
383 }
384 #endif
385 return -ENOSYS;
386 }
387
388 int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
389 {
390 #ifdef KVM_CAP_MCE
391 return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
392 #else
393 return -ENOSYS;
394 #endif
395 }
396
397 int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
398 {
399 #ifdef KVM_CAP_MCE
400 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
401 #else
402 return -ENOSYS;
403 #endif
404 }
405
406 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
407 {
408 fprintf(stderr,
409 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
410 " g %d avl %d)\n",
411 name, seg->selector, seg->base, seg->limit, seg->present,
412 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
413 seg->avl);
414 }
415
416 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
417 {
418 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
419 }
420
421 void kvm_show_regs(CPUState *env)
422 {
423 struct kvm_regs regs;
424 struct kvm_sregs sregs;
425 int r;
426
427 r = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
428 if (r < 0) {
429 perror("KVM_GET_REGS");
430 return;
431 }
432 fprintf(stderr,
433 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
434 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
435 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
436 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
437 "rip %016llx rflags %08llx\n",
438 regs.rax, regs.rbx, regs.rcx, regs.rdx,
439 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
440 regs.r8, regs.r9, regs.r10, regs.r11,
441 regs.r12, regs.r13, regs.r14, regs.r15,
442 regs.rip, regs.rflags);
443 r = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
444 if (r < 0) {
445 perror("KVM_GET_SREGS");
446 return;
447 }
448 print_seg(stderr, "cs", &sregs.cs);
449 print_seg(stderr, "ds", &sregs.ds);
450 print_seg(stderr, "es", &sregs.es);
451 print_seg(stderr, "ss", &sregs.ss);
452 print_seg(stderr, "fs", &sregs.fs);
453 print_seg(stderr, "gs", &sregs.gs);
454 print_seg(stderr, "tr", &sregs.tr);
455 print_seg(stderr, "ldt", &sregs.ldt);
456 print_dt(stderr, "gdt", &sregs.gdt);
457 print_dt(stderr, "idt", &sregs.idt);
458 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
459 " efer %llx\n",
460 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
461 sregs.efer);
462 }
463
464 static void kvm_set_cr8(CPUState *env, uint64_t cr8)
465 {
466 env->kvm_run->cr8 = cr8;
467 }
468
469 int kvm_setup_cpuid(CPUState *env, int nent,
470 struct kvm_cpuid_entry *entries)
471 {
472 struct kvm_cpuid *cpuid;
473 int r;
474
475 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
476
477 cpuid->nent = nent;
478 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
479 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID, cpuid);
480
481 free(cpuid);
482 return r;
483 }
484
485 int kvm_setup_cpuid2(CPUState *env, int nent,
486 struct kvm_cpuid_entry2 *entries)
487 {
488 struct kvm_cpuid2 *cpuid;
489 int r;
490
491 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
492
493 cpuid->nent = nent;
494 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
495 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, cpuid);
496 free(cpuid);
497 return r;
498 }
499
500 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
501 {
502 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
503 int r;
504
505 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
506 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
507 if (r > 0) {
508 r = kvm_vm_ioctl(kvm_state, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
509 if (r < 0) {
510 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
511 return r;
512 }
513 return 0;
514 }
515 #endif
516 return -1;
517 }
518
519 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
520 {
521 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
522 int r;
523
524 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
525 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
526 if (r > 0) {
527 *nrshadow_pages = kvm_vm_ioctl(kvm_state, KVM_GET_NR_MMU_PAGES);
528 return 0;
529 }
530 #endif
531 return -1;
532 }
533
534 #ifdef KVM_CAP_VAPIC
535 static int kvm_enable_tpr_access_reporting(CPUState *env)
536 {
537 int r;
538 struct kvm_tpr_access_ctl tac = { .enabled = 1 };
539
540 r = kvm_ioctl(env->kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
541 if (r <= 0)
542 return -ENOSYS;
543 return kvm_vcpu_ioctl(env, KVM_TPR_ACCESS_REPORTING, &tac);
544 }
545 #endif
546
547 #ifdef KVM_CAP_ADJUST_CLOCK
548 static struct kvm_clock_data kvmclock_data;
549
550 static void kvmclock_pre_save(void *opaque)
551 {
552 struct kvm_clock_data *cl = opaque;
553
554 kvm_vm_ioctl(kvm_state, KVM_GET_CLOCK, cl);
555 }
556
557 static int kvmclock_post_load(void *opaque, int version_id)
558 {
559 struct kvm_clock_data *cl = opaque;
560
561 return kvm_vm_ioctl(kvm_state, KVM_SET_CLOCK, cl);
562 }
563
564 static const VMStateDescription vmstate_kvmclock= {
565 .name = "kvmclock",
566 .version_id = 1,
567 .minimum_version_id = 1,
568 .minimum_version_id_old = 1,
569 .pre_save = kvmclock_pre_save,
570 .post_load = kvmclock_post_load,
571 .fields = (VMStateField []) {
572 VMSTATE_U64(clock, struct kvm_clock_data),
573 VMSTATE_END_OF_LIST()
574 }
575 };
576 #endif
577
578 int kvm_arch_qemu_create_context(void)
579 {
580 int i, r;
581 struct utsname utsname;
582
583 uname(&utsname);
584 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
585
586 if (kvm_shadow_memory)
587 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
588
589 kvm_msr_list = kvm_get_msr_list();
590 if (!kvm_msr_list)
591 return -1;
592 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
593 if (kvm_msr_list->indices[i] == MSR_STAR)
594 kvm_has_msr_star = 1;
595 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
596 kvm_has_vm_hsave_pa = 1;
597 }
598
599 #ifdef KVM_CAP_ADJUST_CLOCK
600 if (kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK))
601 vmstate_register(0, &vmstate_kvmclock, &kvmclock_data);
602 #endif
603
604 r = kvm_set_boot_cpu_id(0);
605 if (r < 0 && r != -ENOSYS) {
606 return r;
607 }
608
609 return 0;
610 }
611
612 /* returns 0 on success, non-0 on failure */
613 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
614 {
615 switch (entry->index) {
616 case MSR_IA32_SYSENTER_CS:
617 env->sysenter_cs = entry->data;
618 break;
619 case MSR_IA32_SYSENTER_ESP:
620 env->sysenter_esp = entry->data;
621 break;
622 case MSR_IA32_SYSENTER_EIP:
623 env->sysenter_eip = entry->data;
624 break;
625 case MSR_STAR:
626 env->star = entry->data;
627 break;
628 #ifdef TARGET_X86_64
629 case MSR_CSTAR:
630 env->cstar = entry->data;
631 break;
632 case MSR_KERNELGSBASE:
633 env->kernelgsbase = entry->data;
634 break;
635 case MSR_FMASK:
636 env->fmask = entry->data;
637 break;
638 case MSR_LSTAR:
639 env->lstar = entry->data;
640 break;
641 #endif
642 case MSR_IA32_TSC:
643 env->tsc = entry->data;
644 break;
645 case MSR_VM_HSAVE_PA:
646 env->vm_hsave = entry->data;
647 break;
648 case MSR_KVM_SYSTEM_TIME:
649 env->system_time_msr = entry->data;
650 break;
651 case MSR_KVM_WALL_CLOCK:
652 env->wall_clock_msr = entry->data;
653 break;
654 #ifdef KVM_CAP_MCE
655 case MSR_MCG_STATUS:
656 env->mcg_status = entry->data;
657 break;
658 case MSR_MCG_CTL:
659 env->mcg_ctl = entry->data;
660 break;
661 #endif
662 default:
663 #ifdef KVM_CAP_MCE
664 if (entry->index >= MSR_MC0_CTL && \
665 entry->index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
666 env->mce_banks[entry->index - MSR_MC0_CTL] = entry->data;
667 break;
668 }
669 #endif
670 printf("Warning unknown msr index 0x%x\n", entry->index);
671 return 1;
672 }
673 return 0;
674 }
675
676 static void kvm_arch_save_mpstate(CPUState *env)
677 {
678 #ifdef KVM_CAP_MP_STATE
679 int r;
680 struct kvm_mp_state mp_state;
681
682 r = kvm_get_mpstate(env, &mp_state);
683 if (r < 0) {
684 env->mp_state = -1;
685 } else {
686 env->mp_state = mp_state.mp_state;
687 if (kvm_irqchip_in_kernel()) {
688 env->halted = (env->mp_state == KVM_MP_STATE_HALTED);
689 }
690 }
691 #else
692 env->mp_state = -1;
693 #endif
694 }
695
696 static void kvm_arch_load_mpstate(CPUState *env)
697 {
698 #ifdef KVM_CAP_MP_STATE
699 struct kvm_mp_state mp_state;
700
701 /*
702 * -1 indicates that the host did not support GET_MP_STATE ioctl,
703 * so don't touch it.
704 */
705 if (env->mp_state != -1) {
706 mp_state.mp_state = env->mp_state;
707 kvm_set_mpstate(env, &mp_state);
708 }
709 #endif
710 }
711
712 static void kvm_reset_mpstate(CPUState *env)
713 {
714 #ifdef KVM_CAP_MP_STATE
715 if (kvm_check_extension(kvm_state, KVM_CAP_MP_STATE)) {
716 if (kvm_irqchip_in_kernel()) {
717 env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
718 KVM_MP_STATE_UNINITIALIZED;
719 } else {
720 env->mp_state = KVM_MP_STATE_RUNNABLE;
721 }
722 }
723 #endif
724 }
725
726 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
727 {
728 lhs->selector = rhs->selector;
729 lhs->base = rhs->base;
730 lhs->limit = rhs->limit;
731 lhs->type = 3;
732 lhs->present = 1;
733 lhs->dpl = 3;
734 lhs->db = 0;
735 lhs->s = 1;
736 lhs->l = 0;
737 lhs->g = 0;
738 lhs->avl = 0;
739 lhs->unusable = 0;
740 }
741
742 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
743 {
744 unsigned flags = rhs->flags;
745 lhs->selector = rhs->selector;
746 lhs->base = rhs->base;
747 lhs->limit = rhs->limit;
748 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
749 lhs->present = (flags & DESC_P_MASK) != 0;
750 lhs->dpl = rhs->selector & 3;
751 lhs->db = (flags >> DESC_B_SHIFT) & 1;
752 lhs->s = (flags & DESC_S_MASK) != 0;
753 lhs->l = (flags >> DESC_L_SHIFT) & 1;
754 lhs->g = (flags & DESC_G_MASK) != 0;
755 lhs->avl = (flags & DESC_AVL_MASK) != 0;
756 lhs->unusable = 0;
757 }
758
759 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
760 {
761 lhs->selector = rhs->selector;
762 lhs->base = rhs->base;
763 lhs->limit = rhs->limit;
764 lhs->flags =
765 (rhs->type << DESC_TYPE_SHIFT)
766 | (rhs->present * DESC_P_MASK)
767 | (rhs->dpl << DESC_DPL_SHIFT)
768 | (rhs->db << DESC_B_SHIFT)
769 | (rhs->s * DESC_S_MASK)
770 | (rhs->l << DESC_L_SHIFT)
771 | (rhs->g * DESC_G_MASK)
772 | (rhs->avl * DESC_AVL_MASK);
773 }
774
775 #define XSAVE_CWD_RIP 2
776 #define XSAVE_CWD_RDP 4
777 #define XSAVE_MXCSR 6
778 #define XSAVE_ST_SPACE 8
779 #define XSAVE_XMM_SPACE 40
780 #define XSAVE_XSTATE_BV 128
781 #define XSAVE_YMMH_SPACE 144
782
783 void kvm_arch_load_regs(CPUState *env, int level)
784 {
785 struct kvm_regs regs;
786 struct kvm_fpu fpu;
787 struct kvm_sregs sregs;
788 struct kvm_msr_entry msrs[100];
789 int rc, n, i;
790
791 assert(kvm_cpu_is_stopped(env) || env->thread_id == kvm_get_thread_id());
792
793 regs.rax = env->regs[R_EAX];
794 regs.rbx = env->regs[R_EBX];
795 regs.rcx = env->regs[R_ECX];
796 regs.rdx = env->regs[R_EDX];
797 regs.rsi = env->regs[R_ESI];
798 regs.rdi = env->regs[R_EDI];
799 regs.rsp = env->regs[R_ESP];
800 regs.rbp = env->regs[R_EBP];
801 #ifdef TARGET_X86_64
802 regs.r8 = env->regs[8];
803 regs.r9 = env->regs[9];
804 regs.r10 = env->regs[10];
805 regs.r11 = env->regs[11];
806 regs.r12 = env->regs[12];
807 regs.r13 = env->regs[13];
808 regs.r14 = env->regs[14];
809 regs.r15 = env->regs[15];
810 #endif
811
812 regs.rflags = env->eflags;
813 regs.rip = env->eip;
814
815 kvm_set_regs(env, &regs);
816
817 #ifdef KVM_CAP_XSAVE
818 if (kvm_check_extension(kvm_state, KVM_CAP_XSAVE)) {
819 struct kvm_xsave* xsave;
820
821 uint16_t cwd, swd, twd, fop;
822
823 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
824 memset(xsave, 0, sizeof(struct kvm_xsave));
825 cwd = swd = twd = fop = 0;
826 swd = env->fpus & ~(7 << 11);
827 swd |= (env->fpstt & 7) << 11;
828 cwd = env->fpuc;
829 for (i = 0; i < 8; ++i)
830 twd |= (!env->fptags[i]) << i;
831 xsave->region[0] = (uint32_t)(swd << 16) + cwd;
832 xsave->region[1] = (uint32_t)(fop << 16) + twd;
833 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
834 sizeof env->fpregs);
835 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
836 sizeof env->xmm_regs);
837 xsave->region[XSAVE_MXCSR] = env->mxcsr;
838 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
839 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
840 sizeof env->ymmh_regs);
841 kvm_set_xsave(env, xsave);
842 if (kvm_check_extension(kvm_state, KVM_CAP_XCRS)) {
843 struct kvm_xcrs xcrs;
844
845 xcrs.nr_xcrs = 1;
846 xcrs.flags = 0;
847 xcrs.xcrs[0].xcr = 0;
848 xcrs.xcrs[0].value = env->xcr0;
849 kvm_set_xcrs(env, &xcrs);
850 }
851 } else {
852 #endif
853 memset(&fpu, 0, sizeof fpu);
854 fpu.fsw = env->fpus & ~(7 << 11);
855 fpu.fsw |= (env->fpstt & 7) << 11;
856 fpu.fcw = env->fpuc;
857 for (i = 0; i < 8; ++i)
858 fpu.ftwx |= (!env->fptags[i]) << i;
859 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
860 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
861 fpu.mxcsr = env->mxcsr;
862 kvm_set_fpu(env, &fpu);
863 #ifdef KVM_CAP_XSAVE
864 }
865 #endif
866
867 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
868 if (env->interrupt_injected >= 0) {
869 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
870 (uint64_t)1 << (env->interrupt_injected % 64);
871 }
872
873 if ((env->eflags & VM_MASK)) {
874 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
875 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
876 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
877 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
878 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
879 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
880 } else {
881 set_seg(&sregs.cs, &env->segs[R_CS]);
882 set_seg(&sregs.ds, &env->segs[R_DS]);
883 set_seg(&sregs.es, &env->segs[R_ES]);
884 set_seg(&sregs.fs, &env->segs[R_FS]);
885 set_seg(&sregs.gs, &env->segs[R_GS]);
886 set_seg(&sregs.ss, &env->segs[R_SS]);
887
888 if (env->cr[0] & CR0_PE_MASK) {
889 /* force ss cpl to cs cpl */
890 sregs.ss.selector = (sregs.ss.selector & ~3) |
891 (sregs.cs.selector & 3);
892 sregs.ss.dpl = sregs.ss.selector & 3;
893 }
894 }
895
896 set_seg(&sregs.tr, &env->tr);
897 set_seg(&sregs.ldt, &env->ldt);
898
899 sregs.idt.limit = env->idt.limit;
900 sregs.idt.base = env->idt.base;
901 sregs.gdt.limit = env->gdt.limit;
902 sregs.gdt.base = env->gdt.base;
903
904 sregs.cr0 = env->cr[0];
905 sregs.cr2 = env->cr[2];
906 sregs.cr3 = env->cr[3];
907 sregs.cr4 = env->cr[4];
908
909 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
910 sregs.apic_base = cpu_get_apic_base(env->apic_state);
911
912 sregs.efer = env->efer;
913
914 kvm_set_sregs(env, &sregs);
915
916 /* msrs */
917 n = 0;
918 /* Remember to increase msrs size if you add new registers below */
919 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
920 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
921 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
922 if (kvm_has_msr_star)
923 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
924 if (kvm_has_vm_hsave_pa)
925 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
926 #ifdef TARGET_X86_64
927 if (lm_capable_kernel) {
928 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
929 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
930 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
931 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR , env->lstar);
932 }
933 #endif
934 if (level == KVM_PUT_FULL_STATE) {
935 /*
936 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
937 * writeback. Until this is fixed, we only write the offset to SMP
938 * guests after migration, desynchronizing the VCPUs, but avoiding
939 * huge jump-backs that would occur without any writeback at all.
940 */
941 if (smp_cpus == 1 || env->tsc != 0) {
942 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
943 }
944 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr);
945 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
946 }
947 #ifdef KVM_CAP_MCE
948 if (env->mcg_cap) {
949 if (level == KVM_PUT_RESET_STATE)
950 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
951 else if (level == KVM_PUT_FULL_STATE) {
952 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
953 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
954 for (i = 0; i < (env->mcg_cap & 0xff); i++)
955 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
956 }
957 }
958 #endif
959
960 rc = kvm_set_msrs(env, msrs, n);
961 if (rc == -1)
962 perror("kvm_set_msrs FAILED");
963
964 if (level >= KVM_PUT_RESET_STATE) {
965 kvm_arch_load_mpstate(env);
966 kvm_load_lapic(env);
967 }
968 if (level == KVM_PUT_FULL_STATE) {
969 if (env->kvm_vcpu_update_vapic)
970 kvm_tpr_enable_vapic(env);
971 }
972
973 kvm_put_vcpu_events(env, level);
974 kvm_put_debugregs(env);
975
976 /* must be last */
977 kvm_guest_debug_workarounds(env);
978 }
979
980 void kvm_arch_save_regs(CPUState *env)
981 {
982 struct kvm_regs regs;
983 struct kvm_fpu fpu;
984 struct kvm_sregs sregs;
985 struct kvm_msr_entry msrs[100];
986 uint32_t hflags;
987 uint32_t i, n, rc, bit;
988
989 assert(kvm_cpu_is_stopped(env) || env->thread_id == kvm_get_thread_id());
990
991 kvm_get_regs(env, &regs);
992
993 env->regs[R_EAX] = regs.rax;
994 env->regs[R_EBX] = regs.rbx;
995 env->regs[R_ECX] = regs.rcx;
996 env->regs[R_EDX] = regs.rdx;
997 env->regs[R_ESI] = regs.rsi;
998 env->regs[R_EDI] = regs.rdi;
999 env->regs[R_ESP] = regs.rsp;
1000 env->regs[R_EBP] = regs.rbp;
1001 #ifdef TARGET_X86_64
1002 env->regs[8] = regs.r8;
1003 env->regs[9] = regs.r9;
1004 env->regs[10] = regs.r10;
1005 env->regs[11] = regs.r11;
1006 env->regs[12] = regs.r12;
1007 env->regs[13] = regs.r13;
1008 env->regs[14] = regs.r14;
1009 env->regs[15] = regs.r15;
1010 #endif
1011
1012 env->eflags = regs.rflags;
1013 env->eip = regs.rip;
1014
1015 #ifdef KVM_CAP_XSAVE
1016 if (kvm_check_extension(kvm_state, KVM_CAP_XSAVE)) {
1017 struct kvm_xsave* xsave;
1018 uint16_t cwd, swd, twd, fop;
1019 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
1020 kvm_get_xsave(env, xsave);
1021 cwd = (uint16_t)xsave->region[0];
1022 swd = (uint16_t)(xsave->region[0] >> 16);
1023 twd = (uint16_t)xsave->region[1];
1024 fop = (uint16_t)(xsave->region[1] >> 16);
1025 env->fpstt = (swd >> 11) & 7;
1026 env->fpus = swd;
1027 env->fpuc = cwd;
1028 for (i = 0; i < 8; ++i)
1029 env->fptags[i] = !((twd >> i) & 1);
1030 env->mxcsr = xsave->region[XSAVE_MXCSR];
1031 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1032 sizeof env->fpregs);
1033 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1034 sizeof env->xmm_regs);
1035 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1036 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1037 sizeof env->ymmh_regs);
1038 if (kvm_check_extension(kvm_state, KVM_CAP_XCRS)) {
1039 struct kvm_xcrs xcrs;
1040
1041 kvm_get_xcrs(env, &xcrs);
1042 if (xcrs.xcrs[0].xcr == 0)
1043 env->xcr0 = xcrs.xcrs[0].value;
1044 }
1045 } else {
1046 #endif
1047 kvm_get_fpu(env, &fpu);
1048 env->fpstt = (fpu.fsw >> 11) & 7;
1049 env->fpus = fpu.fsw;
1050 env->fpuc = fpu.fcw;
1051 for (i = 0; i < 8; ++i)
1052 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1053 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1054 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1055 env->mxcsr = fpu.mxcsr;
1056 #ifdef KVM_CAP_XSAVE
1057 }
1058 #endif
1059
1060 kvm_get_sregs(env, &sregs);
1061
1062 /* There can only be one pending IRQ set in the bitmap at a time, so try
1063 to find it and save its number instead (-1 for none). */
1064 env->interrupt_injected = -1;
1065 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1066 if (sregs.interrupt_bitmap[i]) {
1067 bit = ctz64(sregs.interrupt_bitmap[i]);
1068 env->interrupt_injected = i * 64 + bit;
1069 break;
1070 }
1071 }
1072
1073 get_seg(&env->segs[R_CS], &sregs.cs);
1074 get_seg(&env->segs[R_DS], &sregs.ds);
1075 get_seg(&env->segs[R_ES], &sregs.es);
1076 get_seg(&env->segs[R_FS], &sregs.fs);
1077 get_seg(&env->segs[R_GS], &sregs.gs);
1078 get_seg(&env->segs[R_SS], &sregs.ss);
1079
1080 get_seg(&env->tr, &sregs.tr);
1081 get_seg(&env->ldt, &sregs.ldt);
1082
1083 env->idt.limit = sregs.idt.limit;
1084 env->idt.base = sregs.idt.base;
1085 env->gdt.limit = sregs.gdt.limit;
1086 env->gdt.base = sregs.gdt.base;
1087
1088 env->cr[0] = sregs.cr0;
1089 env->cr[2] = sregs.cr2;
1090 env->cr[3] = sregs.cr3;
1091 env->cr[4] = sregs.cr4;
1092
1093 cpu_set_apic_base(env->apic_state, sregs.apic_base);
1094
1095 env->efer = sregs.efer;
1096 //cpu_set_apic_tpr(env, sregs.cr8);
1097
1098 #define HFLAG_COPY_MASK ~( \
1099 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1100 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1101 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1102 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1103
1104
1105
1106 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1107 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1108 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1109 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1110 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1111 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1112 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1113
1114 if (env->efer & MSR_EFER_LMA) {
1115 hflags |= HF_LMA_MASK;
1116 }
1117
1118 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1119 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1120 } else {
1121 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1122 (DESC_B_SHIFT - HF_CS32_SHIFT);
1123 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1124 (DESC_B_SHIFT - HF_SS32_SHIFT);
1125 if (!(env->cr[0] & CR0_PE_MASK) ||
1126 (env->eflags & VM_MASK) ||
1127 !(hflags & HF_CS32_MASK)) {
1128 hflags |= HF_ADDSEG_MASK;
1129 } else {
1130 hflags |= ((env->segs[R_DS].base |
1131 env->segs[R_ES].base |
1132 env->segs[R_SS].base) != 0) <<
1133 HF_ADDSEG_SHIFT;
1134 }
1135 }
1136 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1137
1138 /* msrs */
1139 n = 0;
1140 /* Remember to increase msrs size if you add new registers below */
1141 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1142 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1143 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1144 if (kvm_has_msr_star)
1145 msrs[n++].index = MSR_STAR;
1146 msrs[n++].index = MSR_IA32_TSC;
1147 if (kvm_has_vm_hsave_pa)
1148 msrs[n++].index = MSR_VM_HSAVE_PA;
1149 #ifdef TARGET_X86_64
1150 if (lm_capable_kernel) {
1151 msrs[n++].index = MSR_CSTAR;
1152 msrs[n++].index = MSR_KERNELGSBASE;
1153 msrs[n++].index = MSR_FMASK;
1154 msrs[n++].index = MSR_LSTAR;
1155 }
1156 #endif
1157 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1158 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1159
1160 #ifdef KVM_CAP_MCE
1161 if (env->mcg_cap) {
1162 msrs[n++].index = MSR_MCG_STATUS;
1163 msrs[n++].index = MSR_MCG_CTL;
1164 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
1165 msrs[n++].index = MSR_MC0_CTL + i;
1166 }
1167 #endif
1168
1169 rc = kvm_get_msrs(env, msrs, n);
1170 if (rc == -1) {
1171 perror("kvm_get_msrs FAILED");
1172 }
1173 else {
1174 n = rc; /* actual number of MSRs */
1175 for (i=0 ; i<n; i++) {
1176 if (get_msr_entry(&msrs[i], env))
1177 return;
1178 }
1179 }
1180 kvm_arch_save_mpstate(env);
1181 kvm_save_lapic(env);
1182 kvm_get_vcpu_events(env);
1183 kvm_get_debugregs(env);
1184 }
1185
1186 static int _kvm_arch_init_vcpu(CPUState *env)
1187 {
1188 kvm_arch_reset_vcpu(env);
1189
1190 #ifdef KVM_CAP_MCE
1191 if (((env->cpuid_version >> 8)&0xF) >= 6
1192 && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
1193 && kvm_check_extension(kvm_state, KVM_CAP_MCE) > 0) {
1194 uint64_t mcg_cap;
1195 int banks;
1196
1197 if (kvm_get_mce_cap_supported(kvm_context, &mcg_cap, &banks))
1198 perror("kvm_get_mce_cap_supported FAILED");
1199 else {
1200 if (banks > MCE_BANKS_DEF)
1201 banks = MCE_BANKS_DEF;
1202 mcg_cap &= MCE_CAP_DEF;
1203 mcg_cap |= banks;
1204 if (kvm_setup_mce(env, &mcg_cap))
1205 perror("kvm_setup_mce FAILED");
1206 else
1207 env->mcg_cap = mcg_cap;
1208 }
1209 }
1210 #endif
1211
1212 #ifdef KVM_EXIT_TPR_ACCESS
1213 kvm_enable_tpr_access_reporting(env);
1214 #endif
1215 kvm_reset_mpstate(env);
1216 return 0;
1217 }
1218
1219 int kvm_arch_halt(CPUState *env)
1220 {
1221
1222 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1223 (env->eflags & IF_MASK)) &&
1224 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1225 env->halted = 1;
1226 }
1227 return 1;
1228 }
1229
1230 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1231 {
1232 if (!kvm_irqchip_in_kernel())
1233 kvm_set_cr8(env, cpu_get_apic_tpr(env->apic_state));
1234 return 0;
1235 }
1236
1237 int kvm_arch_has_work(CPUState *env)
1238 {
1239 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1240 (env->eflags & IF_MASK)) ||
1241 (env->interrupt_request & CPU_INTERRUPT_NMI))
1242 return 1;
1243 return 0;
1244 }
1245
1246 int kvm_arch_try_push_interrupts(void *opaque)
1247 {
1248 CPUState *env = cpu_single_env;
1249 int r, irq;
1250
1251 if (kvm_is_ready_for_interrupt_injection(env) &&
1252 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1253 (env->eflags & IF_MASK)) {
1254 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1255 irq = cpu_get_pic_interrupt(env);
1256 if (irq >= 0) {
1257 r = kvm_inject_irq(env, irq);
1258 if (r < 0)
1259 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1260 }
1261 }
1262
1263 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1264 }
1265
1266 #ifdef KVM_CAP_USER_NMI
1267 void kvm_arch_push_nmi(void *opaque)
1268 {
1269 CPUState *env = cpu_single_env;
1270 int r;
1271
1272 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1273 return;
1274
1275 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1276 r = kvm_inject_nmi(env);
1277 if (r < 0)
1278 printf("cpu %d fail inject NMI\n", env->cpu_index);
1279 }
1280 #endif /* KVM_CAP_USER_NMI */
1281
1282 static int kvm_reset_msrs(CPUState *env)
1283 {
1284 struct {
1285 struct kvm_msrs info;
1286 struct kvm_msr_entry entries[100];
1287 } msr_data;
1288 int n;
1289 struct kvm_msr_entry *msrs = msr_data.entries;
1290
1291 if (!kvm_msr_list)
1292 return -1;
1293
1294 for (n = 0; n < kvm_msr_list->nmsrs; n++) {
1295 kvm_msr_entry_set(&msrs[n], kvm_msr_list->indices[n], 0);
1296 }
1297
1298 msr_data.info.nmsrs = n;
1299
1300 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1301 }
1302
1303
1304 void kvm_arch_cpu_reset(CPUState *env)
1305 {
1306 kvm_reset_msrs(env);
1307 kvm_arch_reset_vcpu(env);
1308 kvm_reset_mpstate(env);
1309 }
1310
1311 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1312 void kvm_arch_do_ioperm(void *_data)
1313 {
1314 struct ioperm_data *data = _data;
1315 ioperm(data->start_port, data->num, data->turn_on);
1316 }
1317 #endif
1318
1319 /*
1320 * Setup x86 specific IRQ routing
1321 */
1322 int kvm_arch_init_irq_routing(void)
1323 {
1324 int i, r;
1325
1326 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1327 kvm_clear_gsi_routes(kvm_context);
1328 for (i = 0; i < 8; ++i) {
1329 if (i == 2)
1330 continue;
1331 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1332 if (r < 0)
1333 return r;
1334 }
1335 for (i = 8; i < 16; ++i) {
1336 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1337 if (r < 0)
1338 return r;
1339 }
1340 for (i = 0; i < 24; ++i) {
1341 if (i == 0) {
1342 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2);
1343 } else if (i != 2) {
1344 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1345 }
1346 if (r < 0)
1347 return r;
1348 }
1349 kvm_commit_irq_routes(kvm_context);
1350 }
1351 return 0;
1352 }
1353
1354 void kvm_arch_process_irqchip_events(CPUState *env)
1355 {
1356 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1357 kvm_cpu_synchronize_state(env);
1358 do_cpu_init(env);
1359 }
1360 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1361 kvm_cpu_synchronize_state(env);
1362 do_cpu_sipi(env);
1363 }
1364 }
Zhi Yong Wu's QEmu Source Tree - dev