2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 //#define HARD_DEBUG_PPC_IO
37 //#define DEBUG_PPC_IO
39 /* SMP is not enabled, for now */
44 #define BIOS_FILENAME "ppc_rom.bin"
45 #define KERNEL_LOAD_ADDR 0x01000000
46 #define INITRD_LOAD_ADDR 0x01800000
48 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
52 #if defined (HARD_DEBUG_PPC_IO)
53 #define PPC_IO_DPRINTF(fmt, args...) \
55 if (loglevel & CPU_LOG_IOPORT) { \
56 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
58 printf("%s : " fmt, __func__ , ##args); \
61 #elif defined (DEBUG_PPC_IO)
62 #define PPC_IO_DPRINTF(fmt, args...) \
64 if (loglevel & CPU_LOG_IOPORT) { \
65 fprintf(logfile, "%s: " fmt, __func__ , ##args); \
69 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
72 /* Constants for devices init */
73 static const int ide_iobase
[2] = { 0x1f0, 0x170 };
74 static const int ide_iobase2
[2] = { 0x3f6, 0x376 };
75 static const int ide_irq
[2] = { 13, 13 };
77 #define NE2000_NB_MAX 6
79 static uint32_t ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
80 static int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
82 //static PITState *pit;
84 /* ISA IO ports bridge */
85 #define PPC_IO_BASE 0x80000000
88 /* Speaker port 0x61 */
89 static int speaker_data_on
;
90 static int dummy_refresh_clock
;
93 static void speaker_ioport_write (void *opaque
, uint32_t addr
, uint32_t val
)
96 speaker_data_on
= (val
>> 1) & 1;
97 pit_set_gate(pit
, 2, val
& 1);
101 static uint32_t speaker_ioport_read (void *opaque
, uint32_t addr
)
105 out
= pit_get_out(pit
, 2, qemu_get_clock(vm_clock
));
106 dummy_refresh_clock
^= 1;
107 return (speaker_data_on
<< 1) | pit_get_gate(pit
, 2) | (out
<< 5) |
108 (dummy_refresh_clock
<< 4);
113 /* PCI intack register */
114 /* Read-only register (?) */
115 static void _PPC_intack_write (void *opaque
,
116 target_phys_addr_t addr
, uint32_t value
)
118 // printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
121 static always_inline
uint32_t _PPC_intack_read (target_phys_addr_t addr
)
125 if ((addr
& 0xf) == 0)
126 retval
= pic_intack_read(isa_pic
);
127 // printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
132 static uint32_t PPC_intack_readb (void *opaque
, target_phys_addr_t addr
)
134 return _PPC_intack_read(addr
);
137 static uint32_t PPC_intack_readw (void *opaque
, target_phys_addr_t addr
)
139 #ifdef TARGET_WORDS_BIGENDIAN
140 return bswap16(_PPC_intack_read(addr
));
142 return _PPC_intack_read(addr
);
146 static uint32_t PPC_intack_readl (void *opaque
, target_phys_addr_t addr
)
148 #ifdef TARGET_WORDS_BIGENDIAN
149 return bswap32(_PPC_intack_read(addr
));
151 return _PPC_intack_read(addr
);
155 static CPUWriteMemoryFunc
*PPC_intack_write
[] = {
161 static CPUReadMemoryFunc
*PPC_intack_read
[] = {
167 /* PowerPC control and status registers */
173 /* Control and status */
178 /* General purpose registers */
191 /* Error diagnostic */
194 static void PPC_XCSR_writeb (void *opaque
,
195 target_phys_addr_t addr
, uint32_t value
)
197 printf("%s: 0x" PADDRX
" => 0x%08" PRIx32
"\n", __func__
, addr
, value
);
200 static void PPC_XCSR_writew (void *opaque
,
201 target_phys_addr_t addr
, uint32_t value
)
203 #ifdef TARGET_WORDS_BIGENDIAN
204 value
= bswap16(value
);
206 printf("%s: 0x" PADDRX
" => 0x%08" PRIx32
"\n", __func__
, addr
, value
);
209 static void PPC_XCSR_writel (void *opaque
,
210 target_phys_addr_t addr
, uint32_t value
)
212 #ifdef TARGET_WORDS_BIGENDIAN
213 value
= bswap32(value
);
215 printf("%s: 0x" PADDRX
" => 0x%08" PRIx32
"\n", __func__
, addr
, value
);
218 static uint32_t PPC_XCSR_readb (void *opaque
, target_phys_addr_t addr
)
222 printf("%s: 0x" PADDRX
" <= %08" PRIx32
"\n", __func__
, addr
, retval
);
227 static uint32_t PPC_XCSR_readw (void *opaque
, target_phys_addr_t addr
)
231 printf("%s: 0x" PADDRX
" <= %08" PRIx32
"\n", __func__
, addr
, retval
);
232 #ifdef TARGET_WORDS_BIGENDIAN
233 retval
= bswap16(retval
);
239 static uint32_t PPC_XCSR_readl (void *opaque
, target_phys_addr_t addr
)
243 printf("%s: 0x" PADDRX
" <= %08" PRIx32
"\n", __func__
, addr
, retval
);
244 #ifdef TARGET_WORDS_BIGENDIAN
245 retval
= bswap32(retval
);
251 static CPUWriteMemoryFunc
*PPC_XCSR_write
[] = {
257 static CPUReadMemoryFunc
*PPC_XCSR_read
[] = {
264 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
265 typedef struct sysctrl_t
{
276 STATE_HARDFILE
= 0x01,
279 static sysctrl_t
*sysctrl
;
281 static void PREP_io_write (void *opaque
, uint32_t addr
, uint32_t val
)
283 sysctrl_t
*sysctrl
= opaque
;
285 PPC_IO_DPRINTF("0x%08" PRIx32
" => 0x%02" PRIx32
"\n", addr
- PPC_IO_BASE
,
287 sysctrl
->fake_io
[addr
- 0x0398] = val
;
290 static uint32_t PREP_io_read (void *opaque
, uint32_t addr
)
292 sysctrl_t
*sysctrl
= opaque
;
294 PPC_IO_DPRINTF("0x%08" PRIx32
" <= 0x%02" PRIx32
"\n", addr
- PPC_IO_BASE
,
295 sysctrl
->fake_io
[addr
- 0x0398]);
296 return sysctrl
->fake_io
[addr
- 0x0398];
299 static void PREP_io_800_writeb (void *opaque
, uint32_t addr
, uint32_t val
)
301 sysctrl_t
*sysctrl
= opaque
;
303 PPC_IO_DPRINTF("0x%08" PRIx32
" => 0x%02" PRIx32
"\n",
304 addr
- PPC_IO_BASE
, val
);
307 /* Special port 92 */
308 /* Check soft reset asked */
310 qemu_irq_raise(sysctrl
->reset_irq
);
312 qemu_irq_lower(sysctrl
->reset_irq
);
322 /* Motorola CPU configuration register : read-only */
325 /* Motorola base module feature register : read-only */
328 /* Motorola base module status register : read-only */
331 /* Hardfile light register */
333 sysctrl
->state
|= STATE_HARDFILE
;
335 sysctrl
->state
&= ~STATE_HARDFILE
;
338 /* Password protect 1 register */
339 if (sysctrl
->nvram
!= NULL
)
340 m48t59_toggle_lock(sysctrl
->nvram
, 1);
343 /* Password protect 2 register */
344 if (sysctrl
->nvram
!= NULL
)
345 m48t59_toggle_lock(sysctrl
->nvram
, 2);
348 /* L2 invalidate register */
349 // tlb_flush(first_cpu, 1);
352 /* system control register */
353 sysctrl
->syscontrol
= val
& 0x0F;
356 /* I/O map type register */
357 sysctrl
->contiguous_map
= val
& 0x01;
360 printf("ERROR: unaffected IO port write: %04" PRIx32
361 " => %02" PRIx32
"\n", addr
, val
);
366 static uint32_t PREP_io_800_readb (void *opaque
, uint32_t addr
)
368 sysctrl_t
*sysctrl
= opaque
;
369 uint32_t retval
= 0xFF;
373 /* Special port 92 */
377 /* Motorola CPU configuration register */
378 retval
= 0xEF; /* MPC750 */
381 /* Motorola Base module feature register */
382 retval
= 0xAD; /* No ESCC, PMC slot neither ethernet */
385 /* Motorola base module status register */
386 retval
= 0xE0; /* Standard MPC750 */
389 /* Equipment present register:
391 * no upgrade processor
392 * no cards in PCI slots
398 /* Motorola base module extended feature register */
399 retval
= 0x39; /* No USB, CF and PCI bridge. NVRAM present */
402 /* L2 invalidate: don't care */
409 /* system control register
410 * 7 - 6 / 1 - 0: L2 cache enable
412 retval
= sysctrl
->syscontrol
;
416 retval
= 0x03; /* no L2 cache */
419 /* I/O map type register */
420 retval
= sysctrl
->contiguous_map
;
423 printf("ERROR: unaffected IO port: %04" PRIx32
" read\n", addr
);
426 PPC_IO_DPRINTF("0x%08" PRIx32
" <= 0x%02" PRIx32
"\n",
427 addr
- PPC_IO_BASE
, retval
);
432 static always_inline target_phys_addr_t
prep_IO_address (sysctrl_t
*sysctrl
,
436 if (sysctrl
->contiguous_map
== 0) {
437 /* 64 KB contiguous space for IOs */
440 /* 8 MB non-contiguous space for IOs */
441 addr
= (addr
& 0x1F) | ((addr
& 0x007FFF000) >> 7);
447 static void PPC_prep_io_writeb (void *opaque
, target_phys_addr_t addr
,
450 sysctrl_t
*sysctrl
= opaque
;
452 addr
= prep_IO_address(sysctrl
, addr
);
453 cpu_outb(NULL
, addr
, value
);
456 static uint32_t PPC_prep_io_readb (void *opaque
, target_phys_addr_t addr
)
458 sysctrl_t
*sysctrl
= opaque
;
461 addr
= prep_IO_address(sysctrl
, addr
);
462 ret
= cpu_inb(NULL
, addr
);
467 static void PPC_prep_io_writew (void *opaque
, target_phys_addr_t addr
,
470 sysctrl_t
*sysctrl
= opaque
;
472 addr
= prep_IO_address(sysctrl
, addr
);
473 #ifdef TARGET_WORDS_BIGENDIAN
474 value
= bswap16(value
);
476 PPC_IO_DPRINTF("0x" PADDRX
" => 0x%08" PRIx32
"\n", addr
, value
);
477 cpu_outw(NULL
, addr
, value
);
480 static uint32_t PPC_prep_io_readw (void *opaque
, target_phys_addr_t addr
)
482 sysctrl_t
*sysctrl
= opaque
;
485 addr
= prep_IO_address(sysctrl
, addr
);
486 ret
= cpu_inw(NULL
, addr
);
487 #ifdef TARGET_WORDS_BIGENDIAN
490 PPC_IO_DPRINTF("0x" PADDRX
" <= 0x%08" PRIx32
"\n", addr
, ret
);
495 static void PPC_prep_io_writel (void *opaque
, target_phys_addr_t addr
,
498 sysctrl_t
*sysctrl
= opaque
;
500 addr
= prep_IO_address(sysctrl
, addr
);
501 #ifdef TARGET_WORDS_BIGENDIAN
502 value
= bswap32(value
);
504 PPC_IO_DPRINTF("0x" PADDRX
" => 0x%08" PRIx32
"\n", addr
, value
);
505 cpu_outl(NULL
, addr
, value
);
508 static uint32_t PPC_prep_io_readl (void *opaque
, target_phys_addr_t addr
)
510 sysctrl_t
*sysctrl
= opaque
;
513 addr
= prep_IO_address(sysctrl
, addr
);
514 ret
= cpu_inl(NULL
, addr
);
515 #ifdef TARGET_WORDS_BIGENDIAN
518 PPC_IO_DPRINTF("0x" PADDRX
" <= 0x%08" PRIx32
"\n", addr
, ret
);
523 static CPUWriteMemoryFunc
*PPC_prep_io_write
[] = {
529 static CPUReadMemoryFunc
*PPC_prep_io_read
[] = {
535 #define NVRAM_SIZE 0x2000
537 /* PowerPC PREP hardware initialisation */
538 static void ppc_prep_init (ram_addr_t ram_size
, int vga_ram_size
,
539 const char *boot_device
, DisplayState
*ds
,
540 const char *kernel_filename
,
541 const char *kernel_cmdline
,
542 const char *initrd_filename
,
543 const char *cpu_model
)
545 CPUState
*env
= NULL
, *envs
[MAX_CPUS
];
550 int linux_boot
, i
, nb_nics1
, bios_size
;
551 unsigned long bios_offset
;
552 uint32_t kernel_base
, kernel_size
, initrd_base
, initrd_size
;
557 BlockDriverState
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
558 BlockDriverState
*fd
[MAX_FD
];
560 sysctrl
= qemu_mallocz(sizeof(sysctrl_t
));
564 linux_boot
= (kernel_filename
!= NULL
);
567 if (cpu_model
== NULL
)
568 cpu_model
= "default";
569 for (i
= 0; i
< smp_cpus
; i
++) {
570 env
= cpu_init(cpu_model
);
572 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
575 if (env
->flags
& POWERPC_FLAG_RTC_CLK
) {
576 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
577 cpu_ppc_tb_init(env
, 7812500UL);
579 /* Set time-base frequency to 100 Mhz */
580 cpu_ppc_tb_init(env
, 100UL * 1000UL * 1000UL);
582 qemu_register_reset(&cpu_ppc_reset
, env
);
587 cpu_register_physical_memory(0, ram_size
, IO_MEM_RAM
);
589 /* allocate and load BIOS */
590 bios_offset
= ram_size
+ vga_ram_size
;
591 if (bios_name
== NULL
)
592 bios_name
= BIOS_FILENAME
;
593 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, bios_name
);
594 bios_size
= load_image(buf
, phys_ram_base
+ bios_offset
);
595 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
596 cpu_abort(env
, "qemu: could not load PPC PREP bios '%s'\n", buf
);
599 if (env
->nip
< 0xFFF80000 && bios_size
< 0x00100000) {
600 cpu_abort(env
, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
602 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
603 cpu_register_physical_memory((uint32_t)(-bios_size
),
604 bios_size
, bios_offset
| IO_MEM_ROM
);
607 kernel_base
= KERNEL_LOAD_ADDR
;
608 /* now we can load the kernel */
609 kernel_size
= load_image(kernel_filename
, phys_ram_base
+ kernel_base
);
610 if (kernel_size
< 0) {
611 cpu_abort(env
, "qemu: could not load kernel '%s'\n",
616 if (initrd_filename
) {
617 initrd_base
= INITRD_LOAD_ADDR
;
618 initrd_size
= load_image(initrd_filename
,
619 phys_ram_base
+ initrd_base
);
620 if (initrd_size
< 0) {
621 cpu_abort(env
, "qemu: could not load initial ram disk '%s'\n",
629 ppc_boot_device
= 'm';
635 ppc_boot_device
= '\0';
636 /* For now, OHW cannot boot from the network. */
637 for (i
= 0; boot_device
[i
] != '\0'; i
++) {
638 if (boot_device
[i
] >= 'a' && boot_device
[i
] <= 'f') {
639 ppc_boot_device
= boot_device
[i
];
643 if (ppc_boot_device
== '\0') {
644 fprintf(stderr
, "No valid boot device for Mac99 machine\n");
649 isa_mem_base
= 0xc0000000;
650 if (PPC_INPUT(env
) != PPC_FLAGS_INPUT_6xx
) {
651 cpu_abort(env
, "Only 6xx bus is supported on PREP machine\n");
654 i8259
= i8259_init(first_cpu
->irq_inputs
[PPC6xx_INPUT_INT
]);
655 pci_bus
= pci_prep_init(i8259
);
656 // pci_bus = i440fx_init();
657 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
658 PPC_io_memory
= cpu_register_io_memory(0, PPC_prep_io_read
,
659 PPC_prep_io_write
, sysctrl
);
660 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory
);
662 /* init basic PC hardware */
663 pci_vga_init(pci_bus
, ds
, phys_ram_base
+ ram_size
, ram_size
,
665 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
666 // pit = pit_init(0x40, i8259[0]);
667 rtc_init(0x70, i8259
[8]);
669 serial_init(0x3f8, i8259
[4], 115200, serial_hds
[0]);
671 if (nb_nics1
> NE2000_NB_MAX
)
672 nb_nics1
= NE2000_NB_MAX
;
673 for(i
= 0; i
< nb_nics1
; i
++) {
674 if (nd_table
[i
].model
== NULL
) {
675 nd_table
[i
].model
= "ne2k_isa";
677 if (strcmp(nd_table
[i
].model
, "ne2k_isa") == 0) {
678 isa_ne2000_init(ne2000_io
[i
], i8259
[ne2000_irq
[i
]], &nd_table
[i
]);
680 pci_nic_init(pci_bus
, &nd_table
[i
], -1, "ne2k_pci");
684 if (drive_get_max_bus(IF_IDE
) >= MAX_IDE_BUS
) {
685 fprintf(stderr
, "qemu: too many IDE bus\n");
689 for(i
= 0; i
< MAX_IDE_BUS
* MAX_IDE_DEVS
; i
++) {
690 index
= drive_get_index(IF_IDE
, i
/ MAX_IDE_DEVS
, i
% MAX_IDE_DEVS
);
692 hd
[i
] = drives_table
[index
].bdrv
;
697 for(i
= 0; i
< MAX_IDE_BUS
; i
++) {
698 isa_ide_init(ide_iobase
[i
], ide_iobase2
[i
], i8259
[ide_irq
[i
]],
702 i8042_init(i8259
[1], i8259
[12], 0x60);
707 for(i
= 0; i
< MAX_FD
; i
++) {
708 index
= drive_get_index(IF_FLOPPY
, 0, i
);
710 fd
[i
] = drives_table
[index
].bdrv
;
714 fdctrl_init(i8259
[6], 2, 0, 0x3f0, fd
);
716 /* Register speaker port */
717 register_ioport_read(0x61, 1, 1, speaker_ioport_read
, NULL
);
718 register_ioport_write(0x61, 1, 1, speaker_ioport_write
, NULL
);
719 /* Register fake IO ports for PREP */
720 sysctrl
->reset_irq
= first_cpu
->irq_inputs
[PPC6xx_INPUT_HRESET
];
721 register_ioport_read(0x398, 2, 1, &PREP_io_read
, sysctrl
);
722 register_ioport_write(0x398, 2, 1, &PREP_io_write
, sysctrl
);
723 /* System control ports */
724 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb
, sysctrl
);
725 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb
, sysctrl
);
726 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb
, sysctrl
);
727 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb
, sysctrl
);
728 /* PCI intack location */
729 PPC_io_memory
= cpu_register_io_memory(0, PPC_intack_read
,
730 PPC_intack_write
, NULL
);
731 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory
);
732 /* PowerPC control and status register group */
734 PPC_io_memory
= cpu_register_io_memory(0, PPC_XCSR_read
, PPC_XCSR_write
,
736 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory
);
740 usb_ohci_init_pci(pci_bus
, 3, -1);
743 m48t59
= m48t59_init(i8259
[8], 0, 0x0074, NVRAM_SIZE
, 59);
746 sysctrl
->nvram
= m48t59
;
748 /* Initialise NVRAM */
749 nvram
.opaque
= m48t59
;
750 nvram
.read_fn
= &m48t59_read
;
751 nvram
.write_fn
= &m48t59_write
;
752 PPC_NVRAM_set_params(&nvram
, NVRAM_SIZE
, "PREP", ram_size
, ppc_boot_device
,
753 kernel_base
, kernel_size
,
755 initrd_base
, initrd_size
,
756 /* XXX: need an option to load a NVRAM image */
758 graphic_width
, graphic_height
, graphic_depth
);
760 /* Special port to get debug messages from Open-Firmware */
761 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write
, NULL
);
764 QEMUMachine prep_machine
= {
766 .desc
= "PowerPC PREP platform",
767 .init
= ppc_prep_init
,
768 .ram_require
= BIOS_SIZE
+ VGA_RAM_SIZE
,
769 .max_cpus
= MAX_CPUS
,