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CRIS: Avoid more cpu_T usage.
[qemu/qemu-JZ.git] / target-cris / translate.c
blob4e34b4464602ec89f976e3da1a222ce858fc1279
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 * FIXME:
24 * The condition code translation is in need of attention.
25 */
26
27 #include <stdarg.h>
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <string.h>
31 #include <inttypes.h>
32 #include <assert.h>
33
34 #include "cpu.h"
35 #include "exec-all.h"
36 #include "disas.h"
37 #include "tcg-op.h"
38 #include "helper.h"
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
41
42 #define DISAS_CRIS 0
43 #if DISAS_CRIS
44 #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
45 #else
46 #define DIS(x)
47 #endif
48
49 #define D(x)
50 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51 #define BUG_ON(x) ({if (x) BUG();})
52
53 #define DISAS_SWI 5
54
55 /* Used by the decoder. */
56 #define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
58
59 #define CC_MASK_NZ 0xc
60 #define CC_MASK_NZV 0xe
61 #define CC_MASK_NZVC 0xf
62 #define CC_MASK_RNZV 0x10e
63
64 static TCGv cpu_env;
65 static TCGv cpu_T[2];
66 static TCGv cpu_R[16];
67 static TCGv cpu_PR[16];
68 static TCGv cc_x;
69 static TCGv cc_src;
70 static TCGv cc_dest;
71 static TCGv cc_result;
72 static TCGv cc_op;
73 static TCGv cc_size;
74 static TCGv cc_mask;
75
76 static TCGv env_btaken;
77 static TCGv env_btarget;
78 static TCGv env_pc;
79
80 #include "gen-icount.h"
81
82 /* This is the state at translation time. */
83 typedef struct DisasContext {
84 CPUState *env;
85 target_ulong pc, ppc;
86
87 /* Decoder. */
88 uint32_t ir;
89 uint32_t opcode;
90 unsigned int op1;
91 unsigned int op2;
92 unsigned int zsize, zzsize;
93 unsigned int mode;
94 unsigned int postinc;
95
96 int update_cc;
97 int cc_op;
98 int cc_size;
99 uint32_t cc_mask;
100
101 int cc_size_uptodate; /* -1 invalid or last written value. */
102
103 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
104 int flags_uptodate; /* Wether or not $ccs is uptodate. */
105 int flagx_known; /* Wether or not flags_x has the x flag known at
106 translation time. */
107 int flags_x;
108
109 int clear_x; /* Clear x after this insn? */
110 int cpustate_changed;
111 unsigned int tb_flags; /* tb dependent flags. */
112 int is_jmp;
113
114 #define JMP_NOJMP 0
115 #define JMP_DIRECT 1
116 #define JMP_INDIRECT 2
117 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
118 uint32_t jmp_pc;
119
120 int delayed_branch;
121
122 struct TranslationBlock *tb;
123 int singlestep_enabled;
124 } DisasContext;
125
126 static void gen_BUG(DisasContext *dc, const char *file, int line)
127 {
128 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
129 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
130 cpu_abort(dc->env, "%s:%d\n", file, line);
131 }
132
133 static const char *regnames[] =
134 {
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
139 };
140 static const char *pregnames[] =
141 {
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
146 };
147
148 /* We need this table to handle preg-moves with implicit width. */
149 static int preg_sizes[] = {
150 1, /* bz. */
151 1, /* vr. */
152 4, /* pid. */
153 1, /* srs. */
154 2, /* wz. */
155 4, 4, 4,
156 4, 4, 4, 4,
157 4, 4, 4, 4,
158 };
159
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
164
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
166 {
167 if (r < 0 || r > 15)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
170 }
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
172 {
173 if (r < 0 || r > 15)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
176 }
177
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
179 {
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
183 }
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
185 {
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
189 }
190
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
192 {
193 if (r < 0 || r > 15)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
197 else if (r == PR_VR)
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EDA) {
200 printf("read from EDA!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
202 }
203 else
204 tcg_gen_mov_tl(tn, cpu_PR[r]);
205 }
206 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
207 {
208 if (r < 0 || r > 15)
209 fprintf(stderr, "wrong register write $p%d\n", r);
210 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
211 return;
212 else if (r == PR_SRS)
213 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
214 else {
215 if (r == PR_PID)
216 tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
217 if (dc->tb_flags & S_FLAG && r == PR_SPC)
218 tcg_gen_helper_0_1(helper_spc_write, tn);
219 else if (r == PR_CCS)
220 dc->cpustate_changed = 1;
221 tcg_gen_mov_tl(cpu_PR[r], tn);
222 }
223 }
224
225 static inline void t_gen_raise_exception(uint32_t index)
226 {
227 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
228 }
229
230 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
231 {
232 TCGv t0, t_31;
233
234 t0 = tcg_temp_new(TCG_TYPE_TL);
235 t_31 = tcg_temp_new(TCG_TYPE_TL);
236 tcg_gen_shl_tl(d, a, b);
237
238 tcg_gen_movi_tl(t_31, 31);
239 tcg_gen_sub_tl(t0, t_31, b);
240 tcg_gen_sar_tl(t0, t0, t_31);
241 tcg_gen_and_tl(t0, t0, d);
242 tcg_gen_xor_tl(d, d, t0);
243 tcg_temp_free(t0);
244 tcg_temp_free(t_31);
245 }
246
247 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
248 {
249 TCGv t0, t_31;
250
251 t0 = tcg_temp_new(TCG_TYPE_TL);
252 t_31 = tcg_temp_new(TCG_TYPE_TL);
253 tcg_gen_shr_tl(d, a, b);
254
255 tcg_gen_movi_tl(t_31, 31);
256 tcg_gen_sub_tl(t0, t_31, b);
257 tcg_gen_sar_tl(t0, t0, t_31);
258 tcg_gen_and_tl(t0, t0, d);
259 tcg_gen_xor_tl(d, d, t0);
260 tcg_temp_free(t0);
261 tcg_temp_free(t_31);
262 }
263
264 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
265 {
266 TCGv t0, t_31;
267
268 t0 = tcg_temp_new(TCG_TYPE_TL);
269 t_31 = tcg_temp_new(TCG_TYPE_TL);
270 tcg_gen_sar_tl(d, a, b);
271
272 tcg_gen_movi_tl(t_31, 31);
273 tcg_gen_sub_tl(t0, t_31, b);
274 tcg_gen_sar_tl(t0, t0, t_31);
275 tcg_gen_or_tl(d, d, t0);
276 tcg_temp_free(t0);
277 tcg_temp_free(t_31);
278 }
279
280 /* 64-bit signed mul, lower result in d and upper in d2. */
281 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
282 {
283 TCGv t0, t1;
284
285 t0 = tcg_temp_new(TCG_TYPE_I64);
286 t1 = tcg_temp_new(TCG_TYPE_I64);
287
288 tcg_gen_ext32s_i64(t0, a);
289 tcg_gen_ext32s_i64(t1, b);
290 tcg_gen_mul_i64(t0, t0, t1);
291
292 tcg_gen_trunc_i64_i32(d, t0);
293 tcg_gen_shri_i64(t0, t0, 32);
294 tcg_gen_trunc_i64_i32(d2, t0);
295
296 tcg_temp_free(t0);
297 tcg_temp_free(t1);
298 }
299
300 /* 64-bit unsigned muls, lower result in d and upper in d2. */
301 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
302 {
303 TCGv t0, t1;
304
305 t0 = tcg_temp_new(TCG_TYPE_I64);
306 t1 = tcg_temp_new(TCG_TYPE_I64);
307
308 tcg_gen_extu_i32_i64(t0, a);
309 tcg_gen_extu_i32_i64(t1, b);
310 tcg_gen_mul_i64(t0, t0, t1);
311
312 tcg_gen_trunc_i64_i32(d, t0);
313 tcg_gen_shri_i64(t0, t0, 32);
314 tcg_gen_trunc_i64_i32(d2, t0);
315
316 tcg_temp_free(t0);
317 tcg_temp_free(t1);
318 }
319
320 /* 32bit branch-free binary search for counting leading zeros. */
321 static void t_gen_lz_i32(TCGv d, TCGv x)
322 {
323 TCGv y, m, n;
324
325 y = tcg_temp_new(TCG_TYPE_I32);
326 m = tcg_temp_new(TCG_TYPE_I32);
327 n = tcg_temp_new(TCG_TYPE_I32);
328
329 /* y = -(x >> 16) */
330 tcg_gen_shri_i32(y, x, 16);
331 tcg_gen_neg_i32(y, y);
332
333 /* m = (y >> 16) & 16 */
334 tcg_gen_sari_i32(m, y, 16);
335 tcg_gen_andi_i32(m, m, 16);
336
337 /* n = 16 - m */
338 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
339 /* x = x >> m */
340 tcg_gen_shr_i32(x, x, m);
341
342 /* y = x - 0x100 */
343 tcg_gen_subi_i32(y, x, 0x100);
344 /* m = (y >> 16) & 8 */
345 tcg_gen_sari_i32(m, y, 16);
346 tcg_gen_andi_i32(m, m, 8);
347 /* n = n + m */
348 tcg_gen_add_i32(n, n, m);
349 /* x = x << m */
350 tcg_gen_shl_i32(x, x, m);
351
352 /* y = x - 0x1000 */
353 tcg_gen_subi_i32(y, x, 0x1000);
354 /* m = (y >> 16) & 4 */
355 tcg_gen_sari_i32(m, y, 16);
356 tcg_gen_andi_i32(m, m, 4);
357 /* n = n + m */
358 tcg_gen_add_i32(n, n, m);
359 /* x = x << m */
360 tcg_gen_shl_i32(x, x, m);
361
362 /* y = x - 0x4000 */
363 tcg_gen_subi_i32(y, x, 0x4000);
364 /* m = (y >> 16) & 2 */
365 tcg_gen_sari_i32(m, y, 16);
366 tcg_gen_andi_i32(m, m, 2);
367 /* n = n + m */
368 tcg_gen_add_i32(n, n, m);
369 /* x = x << m */
370 tcg_gen_shl_i32(x, x, m);
371
372 /* y = x >> 14 */
373 tcg_gen_shri_i32(y, x, 14);
374 /* m = y & ~(y >> 1) */
375 tcg_gen_sari_i32(m, y, 1);
376 tcg_gen_not_i32(m, m);
377 tcg_gen_and_i32(m, m, y);
378
379 /* d = n + 2 - m */
380 tcg_gen_addi_i32(d, n, 2);
381 tcg_gen_sub_i32(d, d, m);
382
383 tcg_temp_free(y);
384 tcg_temp_free(m);
385 tcg_temp_free(n);
386 }
387
388 static void t_gen_btst(TCGv d, TCGv a, TCGv b)
389 {
390 TCGv sbit;
391 TCGv bset;
392 TCGv t0;
393 int l1;
394
395 /* des ref:
396 The N flag is set according to the selected bit in the dest reg.
397 The Z flag is set if the selected bit and all bits to the right are
398 zero.
399 The X flag is cleared.
400 Other flags are left untouched.
401 The destination reg is not affected.
402
403 unsigned int fz, sbit, bset, mask, masked_t0;
404
405 sbit = T1 & 31;
406 bset = !!(T0 & (1 << sbit));
407 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
408 masked_t0 = T0 & mask;
409 fz = !(masked_t0 | bset);
410
411 // Clear the X, N and Z flags.
412 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
413 // Set the N and Z flags accordingly.
414 T0 |= (bset << 3) | (fz << 2);
415 */
416
417 l1 = gen_new_label();
418 sbit = tcg_temp_new(TCG_TYPE_TL);
419 bset = tcg_temp_new(TCG_TYPE_TL);
420 t0 = tcg_temp_new(TCG_TYPE_TL);
421
422 /* Compute bset and sbit. */
423 tcg_gen_andi_tl(sbit, b, 31);
424 tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
425 tcg_gen_and_tl(bset, a, t0);
426 tcg_gen_shr_tl(bset, bset, sbit);
427 /* Displace to N_FLAG. */
428 tcg_gen_shli_tl(bset, bset, 3);
429
430 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
431 tcg_gen_subi_tl(sbit, sbit, 1);
432 tcg_gen_and_tl(sbit, a, sbit);
433
434 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
435 /* or in the N_FLAG. */
436 tcg_gen_or_tl(d, d, bset);
437 tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
438 /* or in the Z_FLAG. */
439 tcg_gen_ori_tl(d, d, Z_FLAG);
440 gen_set_label(l1);
441
442 tcg_temp_free(sbit);
443 tcg_temp_free(bset);
444 }
445
446 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
447 {
448 int l1;
449
450 l1 = gen_new_label();
451
452 /*
453 * d <<= 1
454 * if (d >= s)
455 * d -= s;
456 */
457 tcg_gen_shli_tl(d, a, 1);
458 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
459 tcg_gen_sub_tl(d, d, b);
460 gen_set_label(l1);
461 }
462
463 /* Extended arithmetics on CRIS. */
464 static inline void t_gen_add_flag(TCGv d, int flag)
465 {
466 TCGv c;
467
468 c = tcg_temp_new(TCG_TYPE_TL);
469 t_gen_mov_TN_preg(c, PR_CCS);
470 /* Propagate carry into d. */
471 tcg_gen_andi_tl(c, c, 1 << flag);
472 if (flag)
473 tcg_gen_shri_tl(c, c, flag);
474 tcg_gen_add_tl(d, d, c);
475 tcg_temp_free(c);
476 }
477
478 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
479 {
480 if (dc->flagx_known) {
481 if (dc->flags_x) {
482 TCGv c;
483
484 c = tcg_temp_new(TCG_TYPE_TL);
485 t_gen_mov_TN_preg(c, PR_CCS);
486 /* C flag is already at bit 0. */
487 tcg_gen_andi_tl(c, c, C_FLAG);
488 tcg_gen_add_tl(d, d, c);
489 tcg_temp_free(c);
490 }
491 } else {
492 TCGv x, c;
493
494 x = tcg_temp_new(TCG_TYPE_TL);
495 c = tcg_temp_new(TCG_TYPE_TL);
496 t_gen_mov_TN_preg(x, PR_CCS);
497 tcg_gen_mov_tl(c, x);
498
499 /* Propagate carry into d if X is set. Branch free. */
500 tcg_gen_andi_tl(c, c, C_FLAG);
501 tcg_gen_andi_tl(x, x, X_FLAG);
502 tcg_gen_shri_tl(x, x, 4);
503
504 tcg_gen_and_tl(x, x, c);
505 tcg_gen_add_tl(d, d, x);
506 tcg_temp_free(x);
507 tcg_temp_free(c);
508 }
509 }
510
511 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
512 {
513 if (dc->flagx_known) {
514 if (dc->flags_x) {
515 TCGv c;
516
517 c = tcg_temp_new(TCG_TYPE_TL);
518 t_gen_mov_TN_preg(c, PR_CCS);
519 /* C flag is already at bit 0. */
520 tcg_gen_andi_tl(c, c, C_FLAG);
521 tcg_gen_sub_tl(d, d, c);
522 tcg_temp_free(c);
523 }
524 } else {
525 TCGv x, c;
526
527 x = tcg_temp_new(TCG_TYPE_TL);
528 c = tcg_temp_new(TCG_TYPE_TL);
529 t_gen_mov_TN_preg(x, PR_CCS);
530 tcg_gen_mov_tl(c, x);
531
532 /* Propagate carry into d if X is set. Branch free. */
533 tcg_gen_andi_tl(c, c, C_FLAG);
534 tcg_gen_andi_tl(x, x, X_FLAG);
535 tcg_gen_shri_tl(x, x, 4);
536
537 tcg_gen_and_tl(x, x, c);
538 tcg_gen_sub_tl(d, d, x);
539 tcg_temp_free(x);
540 tcg_temp_free(c);
541 }
542 }
543
544 /* Swap the two bytes within each half word of the s operand.
545 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
546 static inline void t_gen_swapb(TCGv d, TCGv s)
547 {
548 TCGv t, org_s;
549
550 t = tcg_temp_new(TCG_TYPE_TL);
551 org_s = tcg_temp_new(TCG_TYPE_TL);
552
553 /* d and s may refer to the same object. */
554 tcg_gen_mov_tl(org_s, s);
555 tcg_gen_shli_tl(t, org_s, 8);
556 tcg_gen_andi_tl(d, t, 0xff00ff00);
557 tcg_gen_shri_tl(t, org_s, 8);
558 tcg_gen_andi_tl(t, t, 0x00ff00ff);
559 tcg_gen_or_tl(d, d, t);
560 tcg_temp_free(t);
561 tcg_temp_free(org_s);
562 }
563
564 /* Swap the halfwords of the s operand. */
565 static inline void t_gen_swapw(TCGv d, TCGv s)
566 {
567 TCGv t;
568 /* d and s refer the same object. */
569 t = tcg_temp_new(TCG_TYPE_TL);
570 tcg_gen_mov_tl(t, s);
571 tcg_gen_shli_tl(d, t, 16);
572 tcg_gen_shri_tl(t, t, 16);
573 tcg_gen_or_tl(d, d, t);
574 tcg_temp_free(t);
575 }
576
577 /* Reverse the within each byte.
578 T0 = (((T0 << 7) & 0x80808080) |
579 ((T0 << 5) & 0x40404040) |
580 ((T0 << 3) & 0x20202020) |
581 ((T0 << 1) & 0x10101010) |
582 ((T0 >> 1) & 0x08080808) |
583 ((T0 >> 3) & 0x04040404) |
584 ((T0 >> 5) & 0x02020202) |
585 ((T0 >> 7) & 0x01010101));
586 */
587 static inline void t_gen_swapr(TCGv d, TCGv s)
588 {
589 struct {
590 int shift; /* LSL when positive, LSR when negative. */
591 uint32_t mask;
592 } bitrev [] = {
593 {7, 0x80808080},
594 {5, 0x40404040},
595 {3, 0x20202020},
596 {1, 0x10101010},
597 {-1, 0x08080808},
598 {-3, 0x04040404},
599 {-5, 0x02020202},
600 {-7, 0x01010101}
601 };
602 int i;
603 TCGv t, org_s;
604
605 /* d and s refer the same object. */
606 t = tcg_temp_new(TCG_TYPE_TL);
607 org_s = tcg_temp_new(TCG_TYPE_TL);
608 tcg_gen_mov_tl(org_s, s);
609
610 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
611 tcg_gen_andi_tl(d, t, bitrev[0].mask);
612 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
613 if (bitrev[i].shift >= 0) {
614 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
615 } else {
616 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
617 }
618 tcg_gen_andi_tl(t, t, bitrev[i].mask);
619 tcg_gen_or_tl(d, d, t);
620 }
621 tcg_temp_free(t);
622 tcg_temp_free(org_s);
623 }
624
625 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
626 {
627 TCGv btaken;
628 int l1;
629
630 l1 = gen_new_label();
631 btaken = tcg_temp_new(TCG_TYPE_TL);
632
633 /* Conditional jmp. */
634 tcg_gen_mov_tl(btaken, env_btaken);
635 tcg_gen_mov_tl(env_pc, pc_false);
636 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
637 tcg_gen_mov_tl(env_pc, pc_true);
638 gen_set_label(l1);
639
640 tcg_temp_free(btaken);
641 }
642
643 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
644 {
645 TranslationBlock *tb;
646 tb = dc->tb;
647 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
648 tcg_gen_goto_tb(n);
649 tcg_gen_movi_tl(env_pc, dest);
650 tcg_gen_exit_tb((long)tb + n);
651 } else {
652 tcg_gen_movi_tl(env_pc, dest);
653 tcg_gen_exit_tb(0);
654 }
655 }
656
657 /* Sign extend at translation time. */
658 static int sign_extend(unsigned int val, unsigned int width)
659 {
660 int sval;
661
662 /* LSL. */
663 val <<= 31 - width;
664 sval = val;
665 /* ASR. */
666 sval >>= 31 - width;
667 return sval;
668 }
669
670 static inline void cris_clear_x_flag(DisasContext *dc)
671 {
672 if (dc->flagx_known && dc->flags_x)
673 dc->flags_uptodate = 0;
674
675 dc->flagx_known = 1;
676 dc->flags_x = 0;
677 }
678
679 static void cris_flush_cc_state(DisasContext *dc)
680 {
681 if (dc->cc_size_uptodate != dc->cc_size) {
682 tcg_gen_movi_tl(cc_size, dc->cc_size);
683 dc->cc_size_uptodate = dc->cc_size;
684 }
685 tcg_gen_movi_tl(cc_op, dc->cc_op);
686 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
687 }
688
689 static void cris_evaluate_flags(DisasContext *dc)
690 {
691 if (!dc->flags_uptodate) {
692 cris_flush_cc_state(dc);
693
694 switch (dc->cc_op)
695 {
696 case CC_OP_MCP:
697 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
698 break;
699 case CC_OP_MULS:
700 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
701 break;
702 case CC_OP_MULU:
703 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
704 break;
705 case CC_OP_MOVE:
706 case CC_OP_AND:
707 case CC_OP_OR:
708 case CC_OP_XOR:
709 case CC_OP_ASR:
710 case CC_OP_LSR:
711 case CC_OP_LSL:
712 switch (dc->cc_size)
713 {
714 case 4:
715 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
716 break;
717 case 2:
718 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
719 break;
720 default:
721 tcg_gen_helper_0_0(helper_evaluate_flags);
722 break;
723 }
724 break;
725 case CC_OP_FLAGS:
726 /* live. */
727 break;
728 default:
729 {
730 switch (dc->cc_size)
731 {
732 case 4:
733 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
734 break;
735 default:
736 tcg_gen_helper_0_0(helper_evaluate_flags);
737 break;
738 }
739 }
740 break;
741 }
742 if (dc->flagx_known) {
743 if (dc->flags_x)
744 tcg_gen_ori_tl(cpu_PR[PR_CCS],
745 cpu_PR[PR_CCS], X_FLAG);
746 else
747 tcg_gen_andi_tl(cpu_PR[PR_CCS],
748 cpu_PR[PR_CCS], ~X_FLAG);
749 }
750
751 dc->flags_uptodate = 1;
752 }
753 }
754
755 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
756 {
757 uint32_t ovl;
758
759 if (!mask) {
760 dc->update_cc = 0;
761 return;
762 }
763
764 /* Check if we need to evaluate the condition codes due to
765 CC overlaying. */
766 ovl = (dc->cc_mask ^ mask) & ~mask;
767 if (ovl) {
768 /* TODO: optimize this case. It trigs all the time. */
769 cris_evaluate_flags (dc);
770 }
771 dc->cc_mask = mask;
772 dc->update_cc = 1;
773 }
774
775 static void cris_update_cc_op(DisasContext *dc, int op, int size)
776 {
777 dc->cc_op = op;
778 dc->cc_size = size;
779 dc->flags_uptodate = 0;
780 }
781
782 static inline void cris_update_cc_x(DisasContext *dc)
783 {
784 /* Save the x flag state at the time of the cc snapshot. */
785 if (dc->flagx_known) {
786 if (dc->cc_x_uptodate == (2 | dc->flags_x))
787 return;
788 tcg_gen_movi_tl(cc_x, dc->flags_x);
789 dc->cc_x_uptodate = 2 | dc->flags_x;
790 }
791 else {
792 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
793 dc->cc_x_uptodate = 1;
794 }
795 }
796
797 /* Update cc prior to executing ALU op. Needs source operands untouched. */
798 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
799 TCGv dst, TCGv src, int size)
800 {
801 if (dc->update_cc) {
802 cris_update_cc_op(dc, op, size);
803 tcg_gen_mov_tl(cc_src, src);
804
805 if (op != CC_OP_MOVE
806 && op != CC_OP_AND
807 && op != CC_OP_OR
808 && op != CC_OP_XOR
809 && op != CC_OP_ASR
810 && op != CC_OP_LSR
811 && op != CC_OP_LSL)
812 tcg_gen_mov_tl(cc_dest, dst);
813
814 cris_update_cc_x(dc);
815 }
816 }
817
818 /* Update cc after executing ALU op. needs the result. */
819 static inline void cris_update_result(DisasContext *dc, TCGv res)
820 {
821 if (dc->update_cc) {
822 if (dc->cc_size == 4 &&
823 (dc->cc_op == CC_OP_SUB
824 || dc->cc_op == CC_OP_ADD))
825 return;
826 tcg_gen_mov_tl(cc_result, res);
827 }
828 }
829
830 /* Returns one if the write back stage should execute. */
831 static void cris_alu_op_exec(DisasContext *dc, int op,
832 TCGv dst, TCGv a, TCGv b, int size)
833 {
834 /* Emit the ALU insns. */
835 switch (op)
836 {
837 case CC_OP_ADD:
838 tcg_gen_add_tl(dst, a, b);
839 /* Extended arithmetics. */
840 t_gen_addx_carry(dc, dst);
841 break;
842 case CC_OP_ADDC:
843 tcg_gen_add_tl(dst, a, b);
844 t_gen_add_flag(dst, 0); /* C_FLAG. */
845 break;
846 case CC_OP_MCP:
847 tcg_gen_add_tl(dst, a, b);
848 t_gen_add_flag(dst, 8); /* R_FLAG. */
849 break;
850 case CC_OP_SUB:
851 tcg_gen_sub_tl(dst, a, b);
852 /* Extended arithmetics. */
853 t_gen_subx_carry(dc, dst);
854 break;
855 case CC_OP_MOVE:
856 tcg_gen_mov_tl(dst, b);
857 break;
858 case CC_OP_OR:
859 tcg_gen_or_tl(dst, a, b);
860 break;
861 case CC_OP_AND:
862 tcg_gen_and_tl(dst, a, b);
863 break;
864 case CC_OP_XOR:
865 tcg_gen_xor_tl(dst, a, b);
866 break;
867 case CC_OP_LSL:
868 t_gen_lsl(dst, a, b);
869 break;
870 case CC_OP_LSR:
871 t_gen_lsr(dst, a, b);
872 break;
873 case CC_OP_ASR:
874 t_gen_asr(dst, a, b);
875 break;
876 case CC_OP_NEG:
877 tcg_gen_neg_tl(dst, b);
878 /* Extended arithmetics. */
879 t_gen_subx_carry(dc, dst);
880 break;
881 case CC_OP_LZ:
882 t_gen_lz_i32(dst, b);
883 break;
884 case CC_OP_BTST:
885 t_gen_btst(dst, a, b);
886 break;
887 case CC_OP_MULS:
888 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
889 break;
890 case CC_OP_MULU:
891 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
892 break;
893 case CC_OP_DSTEP:
894 t_gen_cris_dstep(dst, a, b);
895 break;
896 case CC_OP_BOUND:
897 {
898 int l1;
899 l1 = gen_new_label();
900 tcg_gen_mov_tl(dst, a);
901 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
902 tcg_gen_mov_tl(dst, b);
903 gen_set_label(l1);
904 }
905 break;
906 case CC_OP_CMP:
907 tcg_gen_sub_tl(dst, a, b);
908 /* Extended arithmetics. */
909 t_gen_subx_carry(dc, dst);
910 break;
911 default:
912 fprintf (logfile, "illegal ALU op.\n");
913 BUG();
914 break;
915 }
916
917 if (size == 1)
918 tcg_gen_andi_tl(dst, dst, 0xff);
919 else if (size == 2)
920 tcg_gen_andi_tl(dst, dst, 0xffff);
921 }
922
923 static void cris_alu(DisasContext *dc, int op,
924 TCGv d, TCGv op_a, TCGv op_b, int size)
925 {
926 TCGv tmp;
927 int writeback;
928
929 writeback = 1;
930 tmp = cpu_T[0];
931 if (op == CC_OP_CMP)
932 writeback = 0;
933 else if (size == 4) {
934 tmp = d;
935 writeback = 0;
936 }
937
938 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
939 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
940 cris_update_result(dc, tmp);
941
942 /* Writeback. */
943 if (writeback) {
944 if (size == 1)
945 tcg_gen_andi_tl(d, d, ~0xff);
946 else
947 tcg_gen_andi_tl(d, d, ~0xffff);
948 tcg_gen_or_tl(d, d, tmp);
949 }
950 }
951
952 static int arith_cc(DisasContext *dc)
953 {
954 if (dc->update_cc) {
955 switch (dc->cc_op) {
956 case CC_OP_ADDC: return 1;
957 case CC_OP_ADD: return 1;
958 case CC_OP_SUB: return 1;
959 case CC_OP_DSTEP: return 1;
960 case CC_OP_LSL: return 1;
961 case CC_OP_LSR: return 1;
962 case CC_OP_ASR: return 1;
963 case CC_OP_CMP: return 1;
964 case CC_OP_NEG: return 1;
965 case CC_OP_OR: return 1;
966 case CC_OP_XOR: return 1;
967 case CC_OP_MULU: return 1;
968 case CC_OP_MULS: return 1;
969 default:
970 return 0;
971 }
972 }
973 return 0;
974 }
975
976 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
977 {
978 int arith_opt, move_opt;
979
980 /* TODO: optimize more condition codes. */
981
982 /*
983 * If the flags are live, we've gotta look into the bits of CCS.
984 * Otherwise, if we just did an arithmetic operation we try to
985 * evaluate the condition code faster.
986 *
987 * When this function is done, T0 should be non-zero if the condition
988 * code is true.
989 */
990 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
991 move_opt = (dc->cc_op == CC_OP_MOVE) && dc->flags_uptodate;
992 switch (cond) {
993 case CC_EQ:
994 if (arith_opt || move_opt) {
995 /* If cc_result is zero, T0 should be
996 non-zero otherwise T0 should be zero. */
997 int l1;
998 l1 = gen_new_label();
999 tcg_gen_movi_tl(cc, 0);
1000 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
1001 0, l1);
1002 tcg_gen_movi_tl(cc, 1);
1003 gen_set_label(l1);
1004 }
1005 else {
1006 cris_evaluate_flags(dc);
1007 tcg_gen_andi_tl(cc,
1008 cpu_PR[PR_CCS], Z_FLAG);
1009 }
1010 break;
1011 case CC_NE:
1012 if (arith_opt || move_opt)
1013 tcg_gen_mov_tl(cc, cc_result);
1014 else {
1015 cris_evaluate_flags(dc);
1016 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1017 Z_FLAG);
1018 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1019 }
1020 break;
1021 case CC_CS:
1022 cris_evaluate_flags(dc);
1023 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
1024 break;
1025 case CC_CC:
1026 cris_evaluate_flags(dc);
1027 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
1028 tcg_gen_andi_tl(cc, cc, C_FLAG);
1029 break;
1030 case CC_VS:
1031 cris_evaluate_flags(dc);
1032 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
1033 break;
1034 case CC_VC:
1035 cris_evaluate_flags(dc);
1036 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1037 V_FLAG);
1038 tcg_gen_andi_tl(cc, cc, V_FLAG);
1039 break;
1040 case CC_PL:
1041 if (arith_opt || move_opt) {
1042 int bits = 31;
1043
1044 if (dc->cc_size == 1)
1045 bits = 7;
1046 else if (dc->cc_size == 2)
1047 bits = 15;
1048
1049 tcg_gen_shri_tl(cc, cc_result, bits);
1050 tcg_gen_xori_tl(cc, cc, 1);
1051 } else {
1052 cris_evaluate_flags(dc);
1053 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1054 N_FLAG);
1055 tcg_gen_andi_tl(cc, cc, N_FLAG);
1056 }
1057 break;
1058 case CC_MI:
1059 if (arith_opt || move_opt) {
1060 int bits = 31;
1061
1062 if (dc->cc_size == 1)
1063 bits = 7;
1064 else if (dc->cc_size == 2)
1065 bits = 15;
1066
1067 tcg_gen_shri_tl(cc, cc_result, 31);
1068 }
1069 else {
1070 cris_evaluate_flags(dc);
1071 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1072 N_FLAG);
1073 }
1074 break;
1075 case CC_LS:
1076 cris_evaluate_flags(dc);
1077 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1078 C_FLAG | Z_FLAG);
1079 break;
1080 case CC_HI:
1081 cris_evaluate_flags(dc);
1082 {
1083 TCGv tmp;
1084
1085 tmp = tcg_temp_new(TCG_TYPE_TL);
1086 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1087 C_FLAG | Z_FLAG);
1088 /* Overlay the C flag on top of the Z. */
1089 tcg_gen_shli_tl(cc, tmp, 2);
1090 tcg_gen_and_tl(cc, tmp, cc);
1091 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1092
1093 tcg_temp_free(tmp);
1094 }
1095 break;
1096 case CC_GE:
1097 cris_evaluate_flags(dc);
1098 /* Overlay the V flag on top of the N. */
1099 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1100 tcg_gen_xor_tl(cc,
1101 cpu_PR[PR_CCS], cc);
1102 tcg_gen_andi_tl(cc, cc, N_FLAG);
1103 tcg_gen_xori_tl(cc, cc, N_FLAG);
1104 break;
1105 case CC_LT:
1106 cris_evaluate_flags(dc);
1107 /* Overlay the V flag on top of the N. */
1108 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1109 tcg_gen_xor_tl(cc,
1110 cpu_PR[PR_CCS], cc);
1111 tcg_gen_andi_tl(cc, cc, N_FLAG);
1112 break;
1113 case CC_GT:
1114 cris_evaluate_flags(dc);
1115 {
1116 TCGv n, z;
1117
1118 n = tcg_temp_new(TCG_TYPE_TL);
1119 z = tcg_temp_new(TCG_TYPE_TL);
1120
1121 /* To avoid a shift we overlay everything on
1122 the V flag. */
1123 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1124 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1125 /* invert Z. */
1126 tcg_gen_xori_tl(z, z, 2);
1127
1128 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1129 tcg_gen_xori_tl(n, n, 2);
1130 tcg_gen_and_tl(cc, z, n);
1131 tcg_gen_andi_tl(cc, cc, 2);
1132
1133 tcg_temp_free(n);
1134 tcg_temp_free(z);
1135 }
1136 break;
1137 case CC_LE:
1138 cris_evaluate_flags(dc);
1139 {
1140 TCGv n, z;
1141
1142 n = tcg_temp_new(TCG_TYPE_TL);
1143 z = tcg_temp_new(TCG_TYPE_TL);
1144
1145 /* To avoid a shift we overlay everything on
1146 the V flag. */
1147 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1148 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1149
1150 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1151 tcg_gen_or_tl(cc, z, n);
1152 tcg_gen_andi_tl(cc, cc, 2);
1153
1154 tcg_temp_free(n);
1155 tcg_temp_free(z);
1156 }
1157 break;
1158 case CC_P:
1159 cris_evaluate_flags(dc);
1160 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1161 break;
1162 case CC_A:
1163 tcg_gen_movi_tl(cc, 1);
1164 break;
1165 default:
1166 BUG();
1167 break;
1168 };
1169 }
1170
1171 static void cris_store_direct_jmp(DisasContext *dc)
1172 {
1173 /* Store the direct jmp state into the cpu-state. */
1174 if (dc->jmp == JMP_DIRECT) {
1175 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1176 tcg_gen_movi_tl(env_btaken, 1);
1177 }
1178 }
1179
1180 static void cris_prepare_cc_branch (DisasContext *dc,
1181 int offset, int cond)
1182 {
1183 /* This helps us re-schedule the micro-code to insns in delay-slots
1184 before the actual jump. */
1185 dc->delayed_branch = 2;
1186 dc->jmp_pc = dc->pc + offset;
1187
1188 if (cond != CC_A)
1189 {
1190 dc->jmp = JMP_INDIRECT;
1191 gen_tst_cc (dc, env_btaken, cond);
1192 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1193 } else {
1194 /* Allow chaining. */
1195 dc->jmp = JMP_DIRECT;
1196 }
1197 }
1198
1199
1200 /* jumps, when the dest is in a live reg for example. Direct should be set
1201 when the dest addr is constant to allow tb chaining. */
1202 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1203 {
1204 /* This helps us re-schedule the micro-code to insns in delay-slots
1205 before the actual jump. */
1206 dc->delayed_branch = 2;
1207 dc->jmp = type;
1208 if (type == JMP_INDIRECT)
1209 tcg_gen_movi_tl(env_btaken, 1);
1210 }
1211
1212 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1213 unsigned int size, int sign)
1214 {
1215 int mem_index = cpu_mmu_index(dc->env);
1216
1217 /* If we get a fault on a delayslot we must keep the jmp state in
1218 the cpu-state to be able to re-execute the jmp. */
1219 if (dc->delayed_branch == 1)
1220 cris_store_direct_jmp(dc);
1221
1222 if (size == 1) {
1223 if (sign)
1224 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1225 else
1226 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1227 }
1228 else if (size == 2) {
1229 if (sign)
1230 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1231 else
1232 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1233 }
1234 else if (size == 4) {
1235 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1236 }
1237 else if (size == 8) {
1238 tcg_gen_qemu_ld64(dst, addr, mem_index);
1239 }
1240 }
1241
1242 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1243 unsigned int size)
1244 {
1245 int mem_index = cpu_mmu_index(dc->env);
1246
1247 /* If we get a fault on a delayslot we must keep the jmp state in
1248 the cpu-state to be able to re-execute the jmp. */
1249 if (dc->delayed_branch == 1)
1250 cris_store_direct_jmp(dc);
1251
1252
1253 /* Conditional writes. We only support the kind were X and P are known
1254 at translation time. */
1255 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1256 dc->postinc = 0;
1257 cris_evaluate_flags(dc);
1258 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1259 return;
1260 }
1261
1262 if (size == 1)
1263 tcg_gen_qemu_st8(val, addr, mem_index);
1264 else if (size == 2)
1265 tcg_gen_qemu_st16(val, addr, mem_index);
1266 else
1267 tcg_gen_qemu_st32(val, addr, mem_index);
1268
1269 if (dc->flagx_known && dc->flags_x) {
1270 cris_evaluate_flags(dc);
1271 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1272 }
1273 }
1274
1275 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1276 {
1277 if (size == 1)
1278 tcg_gen_ext8s_i32(d, s);
1279 else if (size == 2)
1280 tcg_gen_ext16s_i32(d, s);
1281 else if(GET_TCGV(d) != GET_TCGV(s))
1282 tcg_gen_mov_tl(d, s);
1283 }
1284
1285 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1286 {
1287 if (size == 1)
1288 tcg_gen_ext8u_i32(d, s);
1289 else if (size == 2)
1290 tcg_gen_ext16u_i32(d, s);
1291 else if (GET_TCGV(d) != GET_TCGV(s))
1292 tcg_gen_mov_tl(d, s);
1293 }
1294
1295 #if DISAS_CRIS
1296 static char memsize_char(int size)
1297 {
1298 switch (size)
1299 {
1300 case 1: return 'b'; break;
1301 case 2: return 'w'; break;
1302 case 4: return 'd'; break;
1303 default:
1304 return 'x';
1305 break;
1306 }
1307 }
1308 #endif
1309
1310 static inline unsigned int memsize_z(DisasContext *dc)
1311 {
1312 return dc->zsize + 1;
1313 }
1314
1315 static inline unsigned int memsize_zz(DisasContext *dc)
1316 {
1317 switch (dc->zzsize)
1318 {
1319 case 0: return 1;
1320 case 1: return 2;
1321 default:
1322 return 4;
1323 }
1324 }
1325
1326 static inline void do_postinc (DisasContext *dc, int size)
1327 {
1328 if (dc->postinc)
1329 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1330 }
1331
1332 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1333 int size, int s_ext, TCGv dst)
1334 {
1335 if (s_ext)
1336 t_gen_sext(dst, cpu_R[rs], size);
1337 else
1338 t_gen_zext(dst, cpu_R[rs], size);
1339 }
1340
1341 /* Prepare T0 and T1 for a register alu operation.
1342 s_ext decides if the operand1 should be sign-extended or zero-extended when
1343 needed. */
1344 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1345 int size, int s_ext, TCGv dst, TCGv src)
1346 {
1347 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1348
1349 if (s_ext)
1350 t_gen_sext(dst, cpu_R[rd], size);
1351 else
1352 t_gen_zext(dst, cpu_R[rd], size);
1353 }
1354
1355 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1356 TCGv dst)
1357 {
1358 unsigned int rs, rd;
1359 uint32_t imm;
1360 int is_imm;
1361 int insn_len = 2;
1362
1363 rs = dc->op1;
1364 rd = dc->op2;
1365 is_imm = rs == 15 && dc->postinc;
1366
1367 /* Load [$rs] onto T1. */
1368 if (is_imm) {
1369 insn_len = 2 + memsize;
1370 if (memsize == 1)
1371 insn_len++;
1372
1373 if (memsize != 4) {
1374 if (s_ext) {
1375 if (memsize == 1)
1376 imm = ldsb_code(dc->pc + 2);
1377 else
1378 imm = ldsw_code(dc->pc + 2);
1379 } else {
1380 if (memsize == 1)
1381 imm = ldub_code(dc->pc + 2);
1382 else
1383 imm = lduw_code(dc->pc + 2);
1384 }
1385 } else
1386 imm = ldl_code(dc->pc + 2);
1387
1388 tcg_gen_movi_tl(dst, imm);
1389 dc->postinc = 0;
1390 } else {
1391 cris_flush_cc_state(dc);
1392 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1393 if (s_ext)
1394 t_gen_sext(dst, dst, memsize);
1395 else
1396 t_gen_zext(dst, dst, memsize);
1397 }
1398 return insn_len;
1399 }
1400
1401 /* Prepare T0 and T1 for a memory + alu operation.
1402 s_ext decides if the operand1 should be sign-extended or zero-extended when
1403 needed. */
1404 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1405 {
1406 int insn_len;
1407
1408 insn_len = dec_prep_move_m(dc, s_ext, memsize, cpu_T[1]);
1409
1410 /* put dest in T0. */
1411 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
1412 return insn_len;
1413 }
1414
1415 #if DISAS_CRIS
1416 static const char *cc_name(int cc)
1417 {
1418 static const char *cc_names[16] = {
1419 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1420 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1421 };
1422 assert(cc < 16);
1423 return cc_names[cc];
1424 }
1425 #endif
1426
1427 /* Start of insn decoders. */
1428
1429 static unsigned int dec_bccq(DisasContext *dc)
1430 {
1431 int32_t offset;
1432 int sign;
1433 uint32_t cond = dc->op2;
1434 int tmp;
1435
1436 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1437 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1438
1439 offset *= 2;
1440 offset |= sign << 8;
1441 tmp = offset;
1442 offset = sign_extend(offset, 8);
1443
1444 DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
1445
1446 /* op2 holds the condition-code. */
1447 cris_cc_mask(dc, 0);
1448 cris_prepare_cc_branch (dc, offset, cond);
1449 return 2;
1450 }
1451 static unsigned int dec_addoq(DisasContext *dc)
1452 {
1453 int32_t imm;
1454
1455 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1456 imm = sign_extend(dc->op1, 7);
1457
1458 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1459 cris_cc_mask(dc, 0);
1460 /* Fetch register operand, */
1461 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1462
1463 return 2;
1464 }
1465 static unsigned int dec_addq(DisasContext *dc)
1466 {
1467 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1468
1469 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1470
1471 cris_cc_mask(dc, CC_MASK_NZVC);
1472
1473 cris_alu(dc, CC_OP_ADD,
1474 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1475 return 2;
1476 }
1477 static unsigned int dec_moveq(DisasContext *dc)
1478 {
1479 uint32_t imm;
1480
1481 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1482 imm = sign_extend(dc->op1, 5);
1483 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1484
1485 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1486 return 2;
1487 }
1488 static unsigned int dec_subq(DisasContext *dc)
1489 {
1490 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1491
1492 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1493
1494 cris_cc_mask(dc, CC_MASK_NZVC);
1495 cris_alu(dc, CC_OP_SUB,
1496 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1497 return 2;
1498 }
1499 static unsigned int dec_cmpq(DisasContext *dc)
1500 {
1501 uint32_t imm;
1502 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1503 imm = sign_extend(dc->op1, 5);
1504
1505 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1506 cris_cc_mask(dc, CC_MASK_NZVC);
1507
1508 cris_alu(dc, CC_OP_CMP,
1509 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1510 return 2;
1511 }
1512 static unsigned int dec_andq(DisasContext *dc)
1513 {
1514 uint32_t imm;
1515 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1516 imm = sign_extend(dc->op1, 5);
1517
1518 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1519 cris_cc_mask(dc, CC_MASK_NZ);
1520
1521 cris_alu(dc, CC_OP_AND,
1522 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1523 return 2;
1524 }
1525 static unsigned int dec_orq(DisasContext *dc)
1526 {
1527 uint32_t imm;
1528 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1529 imm = sign_extend(dc->op1, 5);
1530 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1531 cris_cc_mask(dc, CC_MASK_NZ);
1532
1533 cris_alu(dc, CC_OP_OR,
1534 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1535 return 2;
1536 }
1537 static unsigned int dec_btstq(DisasContext *dc)
1538 {
1539 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1540 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1541
1542 cris_cc_mask(dc, CC_MASK_NZ);
1543
1544 cris_alu(dc, CC_OP_BTST,
1545 cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1546 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1547 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1548 dc->flags_uptodate = 1;
1549 return 2;
1550 }
1551 static unsigned int dec_asrq(DisasContext *dc)
1552 {
1553 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1554 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1555 cris_cc_mask(dc, CC_MASK_NZ);
1556
1557 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1558 cris_alu(dc, CC_OP_MOVE,
1559 cpu_R[dc->op2],
1560 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1561 return 2;
1562 }
1563 static unsigned int dec_lslq(DisasContext *dc)
1564 {
1565 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1566 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1567
1568 cris_cc_mask(dc, CC_MASK_NZ);
1569
1570 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1571
1572 cris_alu(dc, CC_OP_MOVE,
1573 cpu_R[dc->op2],
1574 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1575 return 2;
1576 }
1577 static unsigned int dec_lsrq(DisasContext *dc)
1578 {
1579 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1580 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1581
1582 cris_cc_mask(dc, CC_MASK_NZ);
1583
1584 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1585 cris_alu(dc, CC_OP_MOVE,
1586 cpu_R[dc->op2],
1587 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1588 return 2;
1589 }
1590
1591 static unsigned int dec_move_r(DisasContext *dc)
1592 {
1593 int size = memsize_zz(dc);
1594
1595 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1596 memsize_char(size), dc->op1, dc->op2));
1597
1598 cris_cc_mask(dc, CC_MASK_NZ);
1599 if (size == 4) {
1600 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1601 cris_cc_mask(dc, CC_MASK_NZ);
1602 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1603 cris_update_cc_x(dc);
1604 cris_update_result(dc, cpu_R[dc->op2]);
1605 }
1606 else {
1607 TCGv t0;
1608
1609 t0 = tcg_temp_new(TCG_TYPE_TL);
1610 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1611 cris_alu(dc, CC_OP_MOVE,
1612 cpu_R[dc->op2],
1613 cpu_R[dc->op2], t0, size);
1614 tcg_temp_free(t0);
1615 }
1616 return 2;
1617 }
1618
1619 static unsigned int dec_scc_r(DisasContext *dc)
1620 {
1621 int cond = dc->op2;
1622
1623 DIS(fprintf (logfile, "s%s $r%u\n",
1624 cc_name(cond), dc->op1));
1625
1626 if (cond != CC_A)
1627 {
1628 int l1;
1629
1630 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1631 l1 = gen_new_label();
1632 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1633 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1634 gen_set_label(l1);
1635 }
1636 else
1637 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1638
1639 cris_cc_mask(dc, 0);
1640 return 2;
1641 }
1642
1643 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1644 {
1645 if (size == 4) {
1646 t[0] = cpu_R[dc->op2];
1647 t[1] = cpu_R[dc->op1];
1648 } else {
1649 t[0] = tcg_temp_new(TCG_TYPE_TL);
1650 t[1] = tcg_temp_new(TCG_TYPE_TL);
1651 }
1652 }
1653
1654 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1655 {
1656 if (size != 4) {
1657 tcg_temp_free(t[0]);
1658 tcg_temp_free(t[1]);
1659 }
1660 }
1661
1662 static unsigned int dec_and_r(DisasContext *dc)
1663 {
1664 TCGv t[2];
1665 int size = memsize_zz(dc);
1666
1667 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1668 memsize_char(size), dc->op1, dc->op2));
1669
1670 cris_cc_mask(dc, CC_MASK_NZ);
1671
1672 cris_alu_alloc_temps(dc, size, t);
1673 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1674 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1675 cris_alu_free_temps(dc, size, t);
1676 return 2;
1677 }
1678
1679 static unsigned int dec_lz_r(DisasContext *dc)
1680 {
1681 TCGv t0;
1682 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1683 dc->op1, dc->op2));
1684 cris_cc_mask(dc, CC_MASK_NZ);
1685 t0 = tcg_temp_new(TCG_TYPE_TL);
1686 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1687 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1688 tcg_temp_free(t0);
1689 return 2;
1690 }
1691
1692 static unsigned int dec_lsl_r(DisasContext *dc)
1693 {
1694 TCGv t[2];
1695 int size = memsize_zz(dc);
1696
1697 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1698 memsize_char(size), dc->op1, dc->op2));
1699
1700 cris_cc_mask(dc, CC_MASK_NZ);
1701 cris_alu_alloc_temps(dc, size, t);
1702 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1703 tcg_gen_andi_tl(t[1], t[1], 63);
1704 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1705 cris_alu_alloc_temps(dc, size, t);
1706 return 2;
1707 }
1708
1709 static unsigned int dec_lsr_r(DisasContext *dc)
1710 {
1711 TCGv t[2];
1712 int size = memsize_zz(dc);
1713
1714 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1715 memsize_char(size), dc->op1, dc->op2));
1716
1717 cris_cc_mask(dc, CC_MASK_NZ);
1718 cris_alu_alloc_temps(dc, size, t);
1719 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1720 tcg_gen_andi_tl(t[1], t[1], 63);
1721 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1722 cris_alu_free_temps(dc, size, t);
1723 return 2;
1724 }
1725
1726 static unsigned int dec_asr_r(DisasContext *dc)
1727 {
1728 TCGv t[2];
1729 int size = memsize_zz(dc);
1730
1731 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1732 memsize_char(size), dc->op1, dc->op2));
1733
1734 cris_cc_mask(dc, CC_MASK_NZ);
1735 cris_alu_alloc_temps(dc, size, t);
1736 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1737 tcg_gen_andi_tl(t[1], t[1], 63);
1738 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1739 cris_alu_free_temps(dc, size, t);
1740 return 2;
1741 }
1742
1743 static unsigned int dec_muls_r(DisasContext *dc)
1744 {
1745 TCGv t[2];
1746 int size = memsize_zz(dc);
1747
1748 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1749 memsize_char(size), dc->op1, dc->op2));
1750 cris_cc_mask(dc, CC_MASK_NZV);
1751 cris_alu_alloc_temps(dc, size, t);
1752 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1753
1754 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1755 cris_alu_free_temps(dc, size, t);
1756 return 2;
1757 }
1758
1759 static unsigned int dec_mulu_r(DisasContext *dc)
1760 {
1761 TCGv t[2];
1762 int size = memsize_zz(dc);
1763
1764 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1765 memsize_char(size), dc->op1, dc->op2));
1766 cris_cc_mask(dc, CC_MASK_NZV);
1767 cris_alu_alloc_temps(dc, size, t);
1768 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1769
1770 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1771 cris_alu_alloc_temps(dc, size, t);
1772 return 2;
1773 }
1774
1775
1776 static unsigned int dec_dstep_r(DisasContext *dc)
1777 {
1778 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1779 cris_cc_mask(dc, CC_MASK_NZ);
1780 cris_alu(dc, CC_OP_DSTEP,
1781 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1782 return 2;
1783 }
1784
1785 static unsigned int dec_xor_r(DisasContext *dc)
1786 {
1787 TCGv t[2];
1788 int size = memsize_zz(dc);
1789 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1790 memsize_char(size), dc->op1, dc->op2));
1791 BUG_ON(size != 4); /* xor is dword. */
1792 cris_cc_mask(dc, CC_MASK_NZ);
1793 cris_alu_alloc_temps(dc, size, t);
1794 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1795
1796 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1797 cris_alu_free_temps(dc, size, t);
1798 return 2;
1799 }
1800
1801 static unsigned int dec_bound_r(DisasContext *dc)
1802 {
1803 TCGv l0;
1804 int size = memsize_zz(dc);
1805 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1806 memsize_char(size), dc->op1, dc->op2));
1807 cris_cc_mask(dc, CC_MASK_NZ);
1808 l0 = tcg_temp_local_new(TCG_TYPE_TL);
1809 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1810 cris_alu(dc, CC_OP_BOUND,
1811 cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1812 return 2;
1813 }
1814
1815 static unsigned int dec_cmp_r(DisasContext *dc)
1816 {
1817 TCGv t[2];
1818 int size = memsize_zz(dc);
1819 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1820 memsize_char(size), dc->op1, dc->op2));
1821 cris_cc_mask(dc, CC_MASK_NZVC);
1822 cris_alu_alloc_temps(dc, size, t);
1823 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1824
1825 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1826 cris_alu_free_temps(dc, size, t);
1827 return 2;
1828 }
1829
1830 static unsigned int dec_abs_r(DisasContext *dc)
1831 {
1832 TCGv t0;
1833
1834 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1835 dc->op1, dc->op2));
1836 cris_cc_mask(dc, CC_MASK_NZ);
1837
1838 t0 = tcg_temp_new(TCG_TYPE_TL);
1839 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1840 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1841 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1842 tcg_temp_free(t0);
1843
1844 cris_alu(dc, CC_OP_MOVE,
1845 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1846 return 2;
1847 }
1848
1849 static unsigned int dec_add_r(DisasContext *dc)
1850 {
1851 TCGv t[2];
1852 int size = memsize_zz(dc);
1853 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1854 memsize_char(size), dc->op1, dc->op2));
1855 cris_cc_mask(dc, CC_MASK_NZVC);
1856 cris_alu_alloc_temps(dc, size, t);
1857 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1858
1859 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1860 cris_alu_free_temps(dc, size, t);
1861 return 2;
1862 }
1863
1864 static unsigned int dec_addc_r(DisasContext *dc)
1865 {
1866 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1867 dc->op1, dc->op2));
1868 cris_evaluate_flags(dc);
1869 cris_cc_mask(dc, CC_MASK_NZVC);
1870 cris_alu(dc, CC_OP_ADDC,
1871 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1872 return 2;
1873 }
1874
1875 static unsigned int dec_mcp_r(DisasContext *dc)
1876 {
1877 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1878 dc->op2, dc->op1));
1879 cris_evaluate_flags(dc);
1880 cris_cc_mask(dc, CC_MASK_RNZV);
1881 cris_alu(dc, CC_OP_MCP,
1882 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1883 return 2;
1884 }
1885
1886 #if DISAS_CRIS
1887 static char * swapmode_name(int mode, char *modename) {
1888 int i = 0;
1889 if (mode & 8)
1890 modename[i++] = 'n';
1891 if (mode & 4)
1892 modename[i++] = 'w';
1893 if (mode & 2)
1894 modename[i++] = 'b';
1895 if (mode & 1)
1896 modename[i++] = 'r';
1897 modename[i++] = 0;
1898 return modename;
1899 }
1900 #endif
1901
1902 static unsigned int dec_swap_r(DisasContext *dc)
1903 {
1904 TCGv t0;
1905 #if DISAS_CRIS
1906 char modename[4];
1907 #endif
1908 DIS(fprintf (logfile, "swap%s $r%u\n",
1909 swapmode_name(dc->op2, modename), dc->op1));
1910
1911 cris_cc_mask(dc, CC_MASK_NZ);
1912 t0 = tcg_temp_new(TCG_TYPE_TL);
1913 t_gen_mov_TN_reg(t0, dc->op1);
1914 if (dc->op2 & 8)
1915 tcg_gen_not_tl(t0, t0);
1916 if (dc->op2 & 4)
1917 t_gen_swapw(t0, t0);
1918 if (dc->op2 & 2)
1919 t_gen_swapb(t0, t0);
1920 if (dc->op2 & 1)
1921 t_gen_swapr(t0, t0);
1922 cris_alu(dc, CC_OP_MOVE,
1923 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1924 return 2;
1925 }
1926
1927 static unsigned int dec_or_r(DisasContext *dc)
1928 {
1929 TCGv t[2];
1930 int size = memsize_zz(dc);
1931 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1932 memsize_char(size), dc->op1, dc->op2));
1933 cris_cc_mask(dc, CC_MASK_NZ);
1934 cris_alu_alloc_temps(dc, size, t);
1935 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1936 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1937 cris_alu_free_temps(dc, size, t);
1938 return 2;
1939 }
1940
1941 static unsigned int dec_addi_r(DisasContext *dc)
1942 {
1943 TCGv t0;
1944 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1945 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1946 cris_cc_mask(dc, 0);
1947 t0 = tcg_temp_new(TCG_TYPE_TL);
1948 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1949 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1950 return 2;
1951 }
1952
1953 static unsigned int dec_addi_acr(DisasContext *dc)
1954 {
1955 TCGv t0;
1956 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1957 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1958 cris_cc_mask(dc, 0);
1959 t0 = tcg_temp_new(TCG_TYPE_TL);
1960 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1961 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1962
1963 return 2;
1964 }
1965
1966 static unsigned int dec_neg_r(DisasContext *dc)
1967 {
1968 TCGv t[2];
1969 int size = memsize_zz(dc);
1970 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1971 memsize_char(size), dc->op1, dc->op2));
1972 cris_cc_mask(dc, CC_MASK_NZVC);
1973 cris_alu_alloc_temps(dc, size, t);
1974 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1975
1976 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1977 cris_alu_free_temps(dc, size, t);
1978 return 2;
1979 }
1980
1981 static unsigned int dec_btst_r(DisasContext *dc)
1982 {
1983 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1984 dc->op1, dc->op2));
1985 cris_cc_mask(dc, CC_MASK_NZ);
1986 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_T[0], cpu_T[1]);
1987
1988 cris_alu(dc, CC_OP_BTST,
1989 cpu_T[0], cpu_T[0], cpu_T[1], 4);
1990 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1991 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1992 dc->flags_uptodate = 1;
1993 return 2;
1994 }
1995
1996 static unsigned int dec_sub_r(DisasContext *dc)
1997 {
1998 TCGv t[2];
1999 int size = memsize_zz(dc);
2000 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
2001 memsize_char(size), dc->op1, dc->op2));
2002 cris_cc_mask(dc, CC_MASK_NZVC);
2003 cris_alu_alloc_temps(dc, size, t);
2004 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
2005 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
2006 cris_alu_free_temps(dc, size, t);
2007 return 2;
2008 }
2009
2010 /* Zero extension. From size to dword. */
2011 static unsigned int dec_movu_r(DisasContext *dc)
2012 {
2013 TCGv t0;
2014 int size = memsize_z(dc);
2015 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
2016 memsize_char(size),
2017 dc->op1, dc->op2));
2018
2019 cris_cc_mask(dc, CC_MASK_NZ);
2020 t0 = tcg_temp_new(TCG_TYPE_TL);
2021 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
2022 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2023 tcg_temp_free(t0);
2024 return 2;
2025 }
2026
2027 /* Sign extension. From size to dword. */
2028 static unsigned int dec_movs_r(DisasContext *dc)
2029 {
2030 TCGv t0;
2031 int size = memsize_z(dc);
2032 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
2033 memsize_char(size),
2034 dc->op1, dc->op2));
2035
2036 cris_cc_mask(dc, CC_MASK_NZ);
2037 t0 = tcg_temp_new(TCG_TYPE_TL);
2038 /* Size can only be qi or hi. */
2039 t_gen_sext(t0, cpu_R[dc->op1], size);
2040 cris_alu(dc, CC_OP_MOVE,
2041 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
2042 tcg_temp_free(t0);
2043 return 2;
2044 }
2045
2046 /* zero extension. From size to dword. */
2047 static unsigned int dec_addu_r(DisasContext *dc)
2048 {
2049 TCGv t0;
2050 int size = memsize_z(dc);
2051 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
2052 memsize_char(size),
2053 dc->op1, dc->op2));
2054
2055 cris_cc_mask(dc, CC_MASK_NZVC);
2056 t0 = tcg_temp_new(TCG_TYPE_TL);
2057 /* Size can only be qi or hi. */
2058 t_gen_zext(t0, cpu_R[dc->op1], size);
2059 cris_alu(dc, CC_OP_ADD,
2060 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2061 tcg_temp_free(t0);
2062 return 2;
2063 }
2064
2065 /* Sign extension. From size to dword. */
2066 static unsigned int dec_adds_r(DisasContext *dc)
2067 {
2068 TCGv t0;
2069 int size = memsize_z(dc);
2070 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
2071 memsize_char(size),
2072 dc->op1, dc->op2));
2073
2074 cris_cc_mask(dc, CC_MASK_NZVC);
2075 t0 = tcg_temp_new(TCG_TYPE_TL);
2076 /* Size can only be qi or hi. */
2077 t_gen_sext(t0, cpu_R[dc->op1], size);
2078 cris_alu(dc, CC_OP_ADD,
2079 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2080 tcg_temp_free(t0);
2081 return 2;
2082 }
2083
2084 /* Zero extension. From size to dword. */
2085 static unsigned int dec_subu_r(DisasContext *dc)
2086 {
2087 TCGv t0;
2088 int size = memsize_z(dc);
2089 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
2090 memsize_char(size),
2091 dc->op1, dc->op2));
2092
2093 cris_cc_mask(dc, CC_MASK_NZVC);
2094 t0 = tcg_temp_new(TCG_TYPE_TL);
2095 /* Size can only be qi or hi. */
2096 t_gen_zext(t0, cpu_R[dc->op1], size);
2097 cris_alu(dc, CC_OP_SUB,
2098 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2099 tcg_temp_free(t0);
2100 return 2;
2101 }
2102
2103 /* Sign extension. From size to dword. */
2104 static unsigned int dec_subs_r(DisasContext *dc)
2105 {
2106 TCGv t0;
2107 int size = memsize_z(dc);
2108 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
2109 memsize_char(size),
2110 dc->op1, dc->op2));
2111
2112 cris_cc_mask(dc, CC_MASK_NZVC);
2113 t0 = tcg_temp_new(TCG_TYPE_TL);
2114 /* Size can only be qi or hi. */
2115 t_gen_sext(t0, cpu_R[dc->op1], size);
2116 cris_alu(dc, CC_OP_SUB,
2117 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2118 tcg_temp_free(t0);
2119 return 2;
2120 }
2121
2122 static unsigned int dec_setclrf(DisasContext *dc)
2123 {
2124 uint32_t flags;
2125 int set = (~dc->opcode >> 2) & 1;
2126
2127
2128 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2129 | EXTRACT_FIELD(dc->ir, 0, 3);
2130 if (set && flags == 0) {
2131 DIS(fprintf (logfile, "nop\n"));
2132 return 2;
2133 } else if (!set && (flags & 0x20)) {
2134 DIS(fprintf (logfile, "di\n"));
2135 }
2136 else {
2137 DIS(fprintf (logfile, "%sf %x\n",
2138 set ? "set" : "clr",
2139 flags));
2140 }
2141
2142 /* User space is not allowed to touch these. Silently ignore. */
2143 if (dc->tb_flags & U_FLAG) {
2144 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2145 }
2146
2147 if (flags & X_FLAG) {
2148 dc->flagx_known = 1;
2149 if (set)
2150 dc->flags_x = X_FLAG;
2151 else
2152 dc->flags_x = 0;
2153 }
2154
2155 /* Break the TB if the P flag changes. */
2156 if (flags & P_FLAG) {
2157 if ((set && !(dc->tb_flags & P_FLAG))
2158 || (!set && (dc->tb_flags & P_FLAG))) {
2159 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2160 dc->is_jmp = DISAS_UPDATE;
2161 dc->cpustate_changed = 1;
2162 }
2163 }
2164 if (flags & S_FLAG) {
2165 dc->cpustate_changed = 1;
2166 }
2167
2168
2169 /* Simply decode the flags. */
2170 cris_evaluate_flags (dc);
2171 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2172 cris_update_cc_x(dc);
2173 tcg_gen_movi_tl(cc_op, dc->cc_op);
2174
2175 if (set) {
2176 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2177 /* Enter user mode. */
2178 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2179 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2180 dc->cpustate_changed = 1;
2181 }
2182 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2183 }
2184 else
2185 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2186
2187 dc->flags_uptodate = 1;
2188 dc->clear_x = 0;
2189 return 2;
2190 }
2191
2192 static unsigned int dec_move_rs(DisasContext *dc)
2193 {
2194 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
2195 cris_cc_mask(dc, 0);
2196 tcg_gen_helper_0_2(helper_movl_sreg_reg,
2197 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2198 return 2;
2199 }
2200 static unsigned int dec_move_sr(DisasContext *dc)
2201 {
2202 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
2203 cris_cc_mask(dc, 0);
2204 tcg_gen_helper_0_2(helper_movl_reg_sreg,
2205 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2206 return 2;
2207 }
2208
2209 static unsigned int dec_move_rp(DisasContext *dc)
2210 {
2211 TCGv t[2];
2212 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
2213 cris_cc_mask(dc, 0);
2214
2215 t[0] = tcg_temp_new(TCG_TYPE_TL);
2216 if (dc->op2 == PR_CCS) {
2217 cris_evaluate_flags(dc);
2218 t_gen_mov_TN_reg(t[0], dc->op1);
2219 if (dc->tb_flags & U_FLAG) {
2220 t[1] = tcg_temp_new(TCG_TYPE_TL);
2221 /* User space is not allowed to touch all flags. */
2222 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2223 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2224 tcg_gen_or_tl(t[0], t[1], t[0]);
2225 tcg_temp_free(t[1]);
2226 }
2227 }
2228 else
2229 t_gen_mov_TN_reg(t[0], dc->op1);
2230
2231 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2232 if (dc->op2 == PR_CCS) {
2233 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2234 dc->flags_uptodate = 1;
2235 }
2236 tcg_temp_free(t[0]);
2237 return 2;
2238 }
2239 static unsigned int dec_move_pr(DisasContext *dc)
2240 {
2241 TCGv t0;
2242 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
2243 cris_cc_mask(dc, 0);
2244
2245 if (dc->op2 == PR_CCS)
2246 cris_evaluate_flags(dc);
2247
2248 t0 = tcg_temp_new(TCG_TYPE_TL);
2249 t_gen_mov_TN_preg(t0, dc->op2);
2250 cris_alu(dc, CC_OP_MOVE,
2251 cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]);
2252 tcg_temp_free(t0);
2253 return 2;
2254 }
2255
2256 static unsigned int dec_move_mr(DisasContext *dc)
2257 {
2258 int memsize = memsize_zz(dc);
2259 int insn_len;
2260 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2261 memsize_char(memsize),
2262 dc->op1, dc->postinc ? "+]" : "]",
2263 dc->op2));
2264
2265 if (memsize == 4) {
2266 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2267 cris_cc_mask(dc, CC_MASK_NZ);
2268 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2269 cris_update_cc_x(dc);
2270 cris_update_result(dc, cpu_R[dc->op2]);
2271 }
2272 else {
2273 TCGv t0;
2274
2275 t0 = tcg_temp_new(TCG_TYPE_TL);
2276 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2277 cris_cc_mask(dc, CC_MASK_NZ);
2278 cris_alu(dc, CC_OP_MOVE,
2279 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2280 tcg_temp_free(t0);
2281 }
2282 do_postinc(dc, memsize);
2283 return insn_len;
2284 }
2285
2286 static unsigned int dec_movs_m(DisasContext *dc)
2287 {
2288 int memsize = memsize_z(dc);
2289 int insn_len;
2290 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2291 memsize_char(memsize),
2292 dc->op1, dc->postinc ? "+]" : "]",
2293 dc->op2));
2294
2295 /* sign extend. */
2296 insn_len = dec_prep_alu_m(dc, 1, memsize);
2297 cris_cc_mask(dc, CC_MASK_NZ);
2298 cris_alu(dc, CC_OP_MOVE,
2299 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2300 do_postinc(dc, memsize);
2301 return insn_len;
2302 }
2303
2304 static unsigned int dec_addu_m(DisasContext *dc)
2305 {
2306 int memsize = memsize_z(dc);
2307 int insn_len;
2308 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2309 memsize_char(memsize),
2310 dc->op1, dc->postinc ? "+]" : "]",
2311 dc->op2));
2312
2313 /* sign extend. */
2314 insn_len = dec_prep_alu_m(dc, 0, memsize);
2315 cris_cc_mask(dc, CC_MASK_NZVC);
2316 cris_alu(dc, CC_OP_ADD,
2317 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2318 do_postinc(dc, memsize);
2319 return insn_len;
2320 }
2321
2322 static unsigned int dec_adds_m(DisasContext *dc)
2323 {
2324 int memsize = memsize_z(dc);
2325 int insn_len;
2326 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2327 memsize_char(memsize),
2328 dc->op1, dc->postinc ? "+]" : "]",
2329 dc->op2));
2330
2331 /* sign extend. */
2332 insn_len = dec_prep_alu_m(dc, 1, memsize);
2333 cris_cc_mask(dc, CC_MASK_NZVC);
2334 cris_alu(dc, CC_OP_ADD,
2335 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2336 do_postinc(dc, memsize);
2337 return insn_len;
2338 }
2339
2340 static unsigned int dec_subu_m(DisasContext *dc)
2341 {
2342 int memsize = memsize_z(dc);
2343 int insn_len;
2344 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2345 memsize_char(memsize),
2346 dc->op1, dc->postinc ? "+]" : "]",
2347 dc->op2));
2348
2349 /* sign extend. */
2350 insn_len = dec_prep_alu_m(dc, 0, memsize);
2351 cris_cc_mask(dc, CC_MASK_NZVC);
2352 cris_alu(dc, CC_OP_SUB,
2353 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2354 do_postinc(dc, memsize);
2355 return insn_len;
2356 }
2357
2358 static unsigned int dec_subs_m(DisasContext *dc)
2359 {
2360 int memsize = memsize_z(dc);
2361 int insn_len;
2362 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2363 memsize_char(memsize),
2364 dc->op1, dc->postinc ? "+]" : "]",
2365 dc->op2));
2366
2367 /* sign extend. */
2368 insn_len = dec_prep_alu_m(dc, 1, memsize);
2369 cris_cc_mask(dc, CC_MASK_NZVC);
2370 cris_alu(dc, CC_OP_SUB,
2371 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2372 do_postinc(dc, memsize);
2373 return insn_len;
2374 }
2375
2376 static unsigned int dec_movu_m(DisasContext *dc)
2377 {
2378 int memsize = memsize_z(dc);
2379 int insn_len;
2380
2381 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2382 memsize_char(memsize),
2383 dc->op1, dc->postinc ? "+]" : "]",
2384 dc->op2));
2385
2386 insn_len = dec_prep_alu_m(dc, 0, memsize);
2387 cris_cc_mask(dc, CC_MASK_NZ);
2388 cris_alu(dc, CC_OP_MOVE,
2389 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2390 do_postinc(dc, memsize);
2391 return insn_len;
2392 }
2393
2394 static unsigned int dec_cmpu_m(DisasContext *dc)
2395 {
2396 int memsize = memsize_z(dc);
2397 int insn_len;
2398 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2399 memsize_char(memsize),
2400 dc->op1, dc->postinc ? "+]" : "]",
2401 dc->op2));
2402
2403 insn_len = dec_prep_alu_m(dc, 0, memsize);
2404 cris_cc_mask(dc, CC_MASK_NZVC);
2405 cris_alu(dc, CC_OP_CMP,
2406 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2407 do_postinc(dc, memsize);
2408 return insn_len;
2409 }
2410
2411 static unsigned int dec_cmps_m(DisasContext *dc)
2412 {
2413 int memsize = memsize_z(dc);
2414 int insn_len;
2415 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2416 memsize_char(memsize),
2417 dc->op1, dc->postinc ? "+]" : "]",
2418 dc->op2));
2419
2420 insn_len = dec_prep_alu_m(dc, 1, memsize);
2421 cris_cc_mask(dc, CC_MASK_NZVC);
2422 cris_alu(dc, CC_OP_CMP,
2423 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2424 memsize_zz(dc));
2425 do_postinc(dc, memsize);
2426 return insn_len;
2427 }
2428
2429 static unsigned int dec_cmp_m(DisasContext *dc)
2430 {
2431 int memsize = memsize_zz(dc);
2432 int insn_len;
2433 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2434 memsize_char(memsize),
2435 dc->op1, dc->postinc ? "+]" : "]",
2436 dc->op2));
2437
2438 insn_len = dec_prep_alu_m(dc, 0, memsize);
2439 cris_cc_mask(dc, CC_MASK_NZVC);
2440 cris_alu(dc, CC_OP_CMP,
2441 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2442 memsize_zz(dc));
2443 do_postinc(dc, memsize);
2444 return insn_len;
2445 }
2446
2447 static unsigned int dec_test_m(DisasContext *dc)
2448 {
2449 int memsize = memsize_zz(dc);
2450 int insn_len;
2451 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2452 memsize_char(memsize),
2453 dc->op1, dc->postinc ? "+]" : "]",
2454 dc->op2));
2455
2456 cris_evaluate_flags(dc);
2457
2458 insn_len = dec_prep_alu_m(dc, 0, memsize);
2459 cris_cc_mask(dc, CC_MASK_NZ);
2460 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2461
2462 cris_alu(dc, CC_OP_CMP,
2463 cpu_R[dc->op2], cpu_T[1], tcg_const_tl(0),
2464 memsize_zz(dc));
2465 do_postinc(dc, memsize);
2466 return insn_len;
2467 }
2468
2469 static unsigned int dec_and_m(DisasContext *dc)
2470 {
2471 int memsize = memsize_zz(dc);
2472 int insn_len;
2473 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2474 memsize_char(memsize),
2475 dc->op1, dc->postinc ? "+]" : "]",
2476 dc->op2));
2477
2478 insn_len = dec_prep_alu_m(dc, 0, memsize);
2479 cris_cc_mask(dc, CC_MASK_NZ);
2480 cris_alu(dc, CC_OP_AND,
2481 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2482 memsize_zz(dc));
2483 do_postinc(dc, memsize);
2484 return insn_len;
2485 }
2486
2487 static unsigned int dec_add_m(DisasContext *dc)
2488 {
2489 int memsize = memsize_zz(dc);
2490 int insn_len;
2491 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2492 memsize_char(memsize),
2493 dc->op1, dc->postinc ? "+]" : "]",
2494 dc->op2));
2495
2496 insn_len = dec_prep_alu_m(dc, 0, memsize);
2497 cris_cc_mask(dc, CC_MASK_NZVC);
2498 cris_alu(dc, CC_OP_ADD,
2499 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2500 memsize_zz(dc));
2501 do_postinc(dc, memsize);
2502 return insn_len;
2503 }
2504
2505 static unsigned int dec_addo_m(DisasContext *dc)
2506 {
2507 int memsize = memsize_zz(dc);
2508 int insn_len;
2509 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2510 memsize_char(memsize),
2511 dc->op1, dc->postinc ? "+]" : "]",
2512 dc->op2));
2513
2514 insn_len = dec_prep_alu_m(dc, 1, memsize);
2515 cris_cc_mask(dc, 0);
2516 cris_alu(dc, CC_OP_ADD,
2517 cpu_R[R_ACR], cpu_T[0], cpu_T[1], 4);
2518 do_postinc(dc, memsize);
2519 return insn_len;
2520 }
2521
2522 static unsigned int dec_bound_m(DisasContext *dc)
2523 {
2524 int memsize = memsize_zz(dc);
2525 int insn_len;
2526 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2527 memsize_char(memsize),
2528 dc->op1, dc->postinc ? "+]" : "]",
2529 dc->op2));
2530
2531 insn_len = dec_prep_alu_m(dc, 0, memsize);
2532 cris_cc_mask(dc, CC_MASK_NZ);
2533 cris_alu(dc, CC_OP_BOUND,
2534 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2535 do_postinc(dc, memsize);
2536 return insn_len;
2537 }
2538
2539 static unsigned int dec_addc_mr(DisasContext *dc)
2540 {
2541 int insn_len = 2;
2542 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2543 dc->op1, dc->postinc ? "+]" : "]",
2544 dc->op2));
2545
2546 cris_evaluate_flags(dc);
2547 insn_len = dec_prep_alu_m(dc, 0, 4);
2548 cris_cc_mask(dc, CC_MASK_NZVC);
2549 cris_alu(dc, CC_OP_ADDC,
2550 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2551 do_postinc(dc, 4);
2552 return insn_len;
2553 }
2554
2555 static unsigned int dec_sub_m(DisasContext *dc)
2556 {
2557 int memsize = memsize_zz(dc);
2558 int insn_len;
2559 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2560 memsize_char(memsize),
2561 dc->op1, dc->postinc ? "+]" : "]",
2562 dc->op2, dc->ir, dc->zzsize));
2563
2564 insn_len = dec_prep_alu_m(dc, 0, memsize);
2565 cris_cc_mask(dc, CC_MASK_NZVC);
2566 cris_alu(dc, CC_OP_SUB,
2567 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize);
2568 do_postinc(dc, memsize);
2569 return insn_len;
2570 }
2571
2572 static unsigned int dec_or_m(DisasContext *dc)
2573 {
2574 int memsize = memsize_zz(dc);
2575 int insn_len;
2576 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2577 memsize_char(memsize),
2578 dc->op1, dc->postinc ? "+]" : "]",
2579 dc->op2, dc->pc));
2580
2581 insn_len = dec_prep_alu_m(dc, 0, memsize);
2582 cris_cc_mask(dc, CC_MASK_NZ);
2583 cris_alu(dc, CC_OP_OR,
2584 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize_zz(dc));
2585 do_postinc(dc, memsize);
2586 return insn_len;
2587 }
2588
2589 static unsigned int dec_move_mp(DisasContext *dc)
2590 {
2591 int memsize = memsize_zz(dc);
2592 int insn_len = 2;
2593
2594 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2595 memsize_char(memsize),
2596 dc->op1,
2597 dc->postinc ? "+]" : "]",
2598 dc->op2));
2599
2600 insn_len = dec_prep_alu_m(dc, 0, memsize);
2601 cris_cc_mask(dc, 0);
2602 if (dc->op2 == PR_CCS) {
2603 cris_evaluate_flags(dc);
2604 if (dc->tb_flags & U_FLAG) {
2605 /* User space is not allowed to touch all flags. */
2606 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2607 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2608 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2609 }
2610 }
2611
2612 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[1]);
2613
2614 do_postinc(dc, memsize);
2615 return insn_len;
2616 }
2617
2618 static unsigned int dec_move_pm(DisasContext *dc)
2619 {
2620 int memsize;
2621
2622 memsize = preg_sizes[dc->op2];
2623
2624 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2625 memsize_char(memsize),
2626 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2627
2628 /* prepare store. Address in T0, value in T1. */
2629 if (dc->op2 == PR_CCS)
2630 cris_evaluate_flags(dc);
2631 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2632 cris_flush_cc_state(dc);
2633 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2634
2635 cris_cc_mask(dc, 0);
2636 if (dc->postinc)
2637 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2638 return 2;
2639 }
2640
2641 static unsigned int dec_movem_mr(DisasContext *dc)
2642 {
2643 TCGv tmp[16];
2644 int i;
2645 int nr = dc->op2 + 1;
2646
2647 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2648 dc->postinc ? "+]" : "]", dc->op2));
2649
2650 /* There are probably better ways of doing this. */
2651 cris_flush_cc_state(dc);
2652 for (i = 0; i < (nr >> 1); i++) {
2653 tmp[i] = tcg_temp_new(TCG_TYPE_I64);
2654 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 8);
2655 gen_load(dc, tmp[i], cpu_T[0], 8, 0);
2656 }
2657 if (nr & 1) {
2658 tmp[i] = tcg_temp_new(TCG_TYPE_I32);
2659 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 8);
2660 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
2661 }
2662
2663 for (i = 0; i < (nr >> 1); i++) {
2664 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2665 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2666 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2667 tcg_temp_free(tmp[i]);
2668 }
2669 if (nr & 1) {
2670 tcg_gen_mov_tl(cpu_R[dc->op2], tmp[i]);
2671 tcg_temp_free(tmp[i]);
2672 }
2673
2674 /* writeback the updated pointer value. */
2675 if (dc->postinc)
2676 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2677
2678 /* gen_load might want to evaluate the previous insns flags. */
2679 cris_cc_mask(dc, 0);
2680 return 2;
2681 }
2682
2683 static unsigned int dec_movem_rm(DisasContext *dc)
2684 {
2685 TCGv tmp;
2686 int i;
2687
2688 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2689 dc->postinc ? "+]" : "]"));
2690
2691 cris_flush_cc_state(dc);
2692
2693 tmp = tcg_temp_new(TCG_TYPE_TL);
2694 tcg_gen_movi_tl(tmp, 4);
2695 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op1]);
2696 for (i = 0; i <= dc->op2; i++) {
2697 /* Displace addr. */
2698 /* Perform the store. */
2699 gen_store(dc, cpu_T[0], cpu_R[i], 4);
2700 tcg_gen_add_tl(cpu_T[0], cpu_T[0], tmp);
2701 }
2702 if (dc->postinc)
2703 tcg_gen_mov_tl(cpu_R[dc->op1], cpu_T[0]);
2704 cris_cc_mask(dc, 0);
2705 tcg_temp_free(tmp);
2706 return 2;
2707 }
2708
2709 static unsigned int dec_move_rm(DisasContext *dc)
2710 {
2711 int memsize;
2712
2713 memsize = memsize_zz(dc);
2714
2715 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2716 memsize, dc->op2, dc->op1));
2717
2718 /* prepare store. */
2719 cris_flush_cc_state(dc);
2720 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2721
2722 if (dc->postinc)
2723 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2724 cris_cc_mask(dc, 0);
2725 return 2;
2726 }
2727
2728 static unsigned int dec_lapcq(DisasContext *dc)
2729 {
2730 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2731 dc->pc + dc->op1*2, dc->op2));
2732 cris_cc_mask(dc, 0);
2733 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2734 return 2;
2735 }
2736
2737 static unsigned int dec_lapc_im(DisasContext *dc)
2738 {
2739 unsigned int rd;
2740 int32_t imm;
2741 int32_t pc;
2742
2743 rd = dc->op2;
2744
2745 cris_cc_mask(dc, 0);
2746 imm = ldl_code(dc->pc + 2);
2747 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2748
2749 pc = dc->pc;
2750 pc += imm;
2751 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2752 return 6;
2753 }
2754
2755 /* Jump to special reg. */
2756 static unsigned int dec_jump_p(DisasContext *dc)
2757 {
2758 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2759
2760 if (dc->op2 == PR_CCS)
2761 cris_evaluate_flags(dc);
2762 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2763 /* rete will often have low bit set to indicate delayslot. */
2764 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2765 cris_cc_mask(dc, 0);
2766 cris_prepare_jmp(dc, JMP_INDIRECT);
2767 return 2;
2768 }
2769
2770 /* Jump and save. */
2771 static unsigned int dec_jas_r(DisasContext *dc)
2772 {
2773 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2774 cris_cc_mask(dc, 0);
2775 /* Store the return address in Pd. */
2776 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2777 if (dc->op2 > 15)
2778 abort();
2779 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2780
2781 cris_prepare_jmp(dc, JMP_INDIRECT);
2782 return 2;
2783 }
2784
2785 static unsigned int dec_jas_im(DisasContext *dc)
2786 {
2787 uint32_t imm;
2788
2789 imm = ldl_code(dc->pc + 2);
2790
2791 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2792 cris_cc_mask(dc, 0);
2793 /* Store the return address in Pd. */
2794 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2795
2796 dc->jmp_pc = imm;
2797 cris_prepare_jmp(dc, JMP_DIRECT);
2798 return 6;
2799 }
2800
2801 static unsigned int dec_jasc_im(DisasContext *dc)
2802 {
2803 uint32_t imm;
2804
2805 imm = ldl_code(dc->pc + 2);
2806
2807 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2808 cris_cc_mask(dc, 0);
2809 /* Store the return address in Pd. */
2810 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2811
2812 dc->jmp_pc = imm;
2813 cris_prepare_jmp(dc, JMP_DIRECT);
2814 return 6;
2815 }
2816
2817 static unsigned int dec_jasc_r(DisasContext *dc)
2818 {
2819 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2820 cris_cc_mask(dc, 0);
2821 /* Store the return address in Pd. */
2822 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2823 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2824 cris_prepare_jmp(dc, JMP_INDIRECT);
2825 return 2;
2826 }
2827
2828 static unsigned int dec_bcc_im(DisasContext *dc)
2829 {
2830 int32_t offset;
2831 uint32_t cond = dc->op2;
2832
2833 offset = ldsw_code(dc->pc + 2);
2834
2835 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2836 cc_name(cond), offset,
2837 dc->pc, dc->pc + offset));
2838
2839 cris_cc_mask(dc, 0);
2840 /* op2 holds the condition-code. */
2841 cris_prepare_cc_branch (dc, offset, cond);
2842 return 4;
2843 }
2844
2845 static unsigned int dec_bas_im(DisasContext *dc)
2846 {
2847 int32_t simm;
2848
2849
2850 simm = ldl_code(dc->pc + 2);
2851
2852 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2853 cris_cc_mask(dc, 0);
2854 /* Store the return address in Pd. */
2855 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2856
2857 dc->jmp_pc = dc->pc + simm;
2858 cris_prepare_jmp(dc, JMP_DIRECT);
2859 return 6;
2860 }
2861
2862 static unsigned int dec_basc_im(DisasContext *dc)
2863 {
2864 int32_t simm;
2865 simm = ldl_code(dc->pc + 2);
2866
2867 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2868 cris_cc_mask(dc, 0);
2869 /* Store the return address in Pd. */
2870 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2871
2872 dc->jmp_pc = dc->pc + simm;
2873 cris_prepare_jmp(dc, JMP_DIRECT);
2874 return 6;
2875 }
2876
2877 static unsigned int dec_rfe_etc(DisasContext *dc)
2878 {
2879 cris_cc_mask(dc, 0);
2880
2881 if (dc->op2 == 15) /* ignore halt. */
2882 return 2;
2883
2884 switch (dc->op2 & 7) {
2885 case 2:
2886 /* rfe. */
2887 DIS(fprintf(logfile, "rfe\n"));
2888 cris_evaluate_flags(dc);
2889 tcg_gen_helper_0_0(helper_rfe);
2890 dc->is_jmp = DISAS_UPDATE;
2891 break;
2892 case 5:
2893 /* rfn. */
2894 DIS(fprintf(logfile, "rfn\n"));
2895 cris_evaluate_flags(dc);
2896 tcg_gen_helper_0_0(helper_rfn);
2897 dc->is_jmp = DISAS_UPDATE;
2898 break;
2899 case 6:
2900 DIS(fprintf(logfile, "break %d\n", dc->op1));
2901 cris_evaluate_flags (dc);
2902 /* break. */
2903 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2904
2905 /* Breaks start at 16 in the exception vector. */
2906 t_gen_mov_env_TN(trap_vector,
2907 tcg_const_tl(dc->op1 + 16));
2908 t_gen_raise_exception(EXCP_BREAK);
2909 dc->is_jmp = DISAS_UPDATE;
2910 break;
2911 default:
2912 printf ("op2=%x\n", dc->op2);
2913 BUG();
2914 break;
2915
2916 }
2917 return 2;
2918 }
2919
2920 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2921 {
2922 return 2;
2923 }
2924
2925 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2926 {
2927 return 2;
2928 }
2929
2930 static unsigned int dec_null(DisasContext *dc)
2931 {
2932 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2933 dc->pc, dc->opcode, dc->op1, dc->op2);
2934 fflush(NULL);
2935 BUG();
2936 return 2;
2937 }
2938
2939 static struct decoder_info {
2940 struct {
2941 uint32_t bits;
2942 uint32_t mask;
2943 };
2944 unsigned int (*dec)(DisasContext *dc);
2945 } decinfo[] = {
2946 /* Order matters here. */
2947 {DEC_MOVEQ, dec_moveq},
2948 {DEC_BTSTQ, dec_btstq},
2949 {DEC_CMPQ, dec_cmpq},
2950 {DEC_ADDOQ, dec_addoq},
2951 {DEC_ADDQ, dec_addq},
2952 {DEC_SUBQ, dec_subq},
2953 {DEC_ANDQ, dec_andq},
2954 {DEC_ORQ, dec_orq},
2955 {DEC_ASRQ, dec_asrq},
2956 {DEC_LSLQ, dec_lslq},
2957 {DEC_LSRQ, dec_lsrq},
2958 {DEC_BCCQ, dec_bccq},
2959
2960 {DEC_BCC_IM, dec_bcc_im},
2961 {DEC_JAS_IM, dec_jas_im},
2962 {DEC_JAS_R, dec_jas_r},
2963 {DEC_JASC_IM, dec_jasc_im},
2964 {DEC_JASC_R, dec_jasc_r},
2965 {DEC_BAS_IM, dec_bas_im},
2966 {DEC_BASC_IM, dec_basc_im},
2967 {DEC_JUMP_P, dec_jump_p},
2968 {DEC_LAPC_IM, dec_lapc_im},
2969 {DEC_LAPCQ, dec_lapcq},
2970
2971 {DEC_RFE_ETC, dec_rfe_etc},
2972 {DEC_ADDC_MR, dec_addc_mr},
2973
2974 {DEC_MOVE_MP, dec_move_mp},
2975 {DEC_MOVE_PM, dec_move_pm},
2976 {DEC_MOVEM_MR, dec_movem_mr},
2977 {DEC_MOVEM_RM, dec_movem_rm},
2978 {DEC_MOVE_PR, dec_move_pr},
2979 {DEC_SCC_R, dec_scc_r},
2980 {DEC_SETF, dec_setclrf},
2981 {DEC_CLEARF, dec_setclrf},
2982
2983 {DEC_MOVE_SR, dec_move_sr},
2984 {DEC_MOVE_RP, dec_move_rp},
2985 {DEC_SWAP_R, dec_swap_r},
2986 {DEC_ABS_R, dec_abs_r},
2987 {DEC_LZ_R, dec_lz_r},
2988 {DEC_MOVE_RS, dec_move_rs},
2989 {DEC_BTST_R, dec_btst_r},
2990 {DEC_ADDC_R, dec_addc_r},
2991
2992 {DEC_DSTEP_R, dec_dstep_r},
2993 {DEC_XOR_R, dec_xor_r},
2994 {DEC_MCP_R, dec_mcp_r},
2995 {DEC_CMP_R, dec_cmp_r},
2996
2997 {DEC_ADDI_R, dec_addi_r},
2998 {DEC_ADDI_ACR, dec_addi_acr},
2999
3000 {DEC_ADD_R, dec_add_r},
3001 {DEC_SUB_R, dec_sub_r},
3002
3003 {DEC_ADDU_R, dec_addu_r},
3004 {DEC_ADDS_R, dec_adds_r},
3005 {DEC_SUBU_R, dec_subu_r},
3006 {DEC_SUBS_R, dec_subs_r},
3007 {DEC_LSL_R, dec_lsl_r},
3008
3009 {DEC_AND_R, dec_and_r},
3010 {DEC_OR_R, dec_or_r},
3011 {DEC_BOUND_R, dec_bound_r},
3012 {DEC_ASR_R, dec_asr_r},
3013 {DEC_LSR_R, dec_lsr_r},
3014
3015 {DEC_MOVU_R, dec_movu_r},
3016 {DEC_MOVS_R, dec_movs_r},
3017 {DEC_NEG_R, dec_neg_r},
3018 {DEC_MOVE_R, dec_move_r},
3019
3020 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3021 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3022
3023 {DEC_MULS_R, dec_muls_r},
3024 {DEC_MULU_R, dec_mulu_r},
3025
3026 {DEC_ADDU_M, dec_addu_m},
3027 {DEC_ADDS_M, dec_adds_m},
3028 {DEC_SUBU_M, dec_subu_m},
3029 {DEC_SUBS_M, dec_subs_m},
3030
3031 {DEC_CMPU_M, dec_cmpu_m},
3032 {DEC_CMPS_M, dec_cmps_m},
3033 {DEC_MOVU_M, dec_movu_m},
3034 {DEC_MOVS_M, dec_movs_m},
3035
3036 {DEC_CMP_M, dec_cmp_m},
3037 {DEC_ADDO_M, dec_addo_m},
3038 {DEC_BOUND_M, dec_bound_m},
3039 {DEC_ADD_M, dec_add_m},
3040 {DEC_SUB_M, dec_sub_m},
3041 {DEC_AND_M, dec_and_m},
3042 {DEC_OR_M, dec_or_m},
3043 {DEC_MOVE_RM, dec_move_rm},
3044 {DEC_TEST_M, dec_test_m},
3045 {DEC_MOVE_MR, dec_move_mr},
3046
3047 {{0, 0}, dec_null}
3048 };
3049
3050 static inline unsigned int
3051 cris_decoder(DisasContext *dc)
3052 {
3053 unsigned int insn_len = 2;
3054 int i;
3055
3056 if (unlikely(loglevel & CPU_LOG_TB_OP))
3057 tcg_gen_debug_insn_start(dc->pc);
3058
3059 /* Load a halfword onto the instruction register. */
3060 dc->ir = lduw_code(dc->pc);
3061
3062 /* Now decode it. */
3063 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3064 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3065 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3066 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3067 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3068 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3069
3070 /* Large switch for all insns. */
3071 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
3072 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3073 {
3074 insn_len = decinfo[i].dec(dc);
3075 break;
3076 }
3077 }
3078
3079 #if !defined(CONFIG_USER_ONLY)
3080 /* Single-stepping ? */
3081 if (dc->tb_flags & S_FLAG) {
3082 int l1;
3083
3084 l1 = gen_new_label();
3085 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3086 /* We treat SPC as a break with an odd trap vector. */
3087 cris_evaluate_flags (dc);
3088 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3089 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3090 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3091 t_gen_raise_exception(EXCP_BREAK);
3092 gen_set_label(l1);
3093 }
3094 #endif
3095 return insn_len;
3096 }
3097
3098 static void check_breakpoint(CPUState *env, DisasContext *dc)
3099 {
3100 int j;
3101 if (env->nb_breakpoints > 0) {
3102 for(j = 0; j < env->nb_breakpoints; j++) {
3103 if (env->breakpoints[j] == dc->pc) {
3104 cris_evaluate_flags (dc);
3105 tcg_gen_movi_tl(env_pc, dc->pc);
3106 t_gen_raise_exception(EXCP_DEBUG);
3107 dc->is_jmp = DISAS_UPDATE;
3108 }
3109 }
3110 }
3111 }
3112
3113
3114 /*
3115 * Delay slots on QEMU/CRIS.
3116 *
3117 * If an exception hits on a delayslot, the core will let ERP (the Exception
3118 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3119 * to give SW a hint that the exception actually hit on the dslot.
3120 *
3121 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3122 * the core and any jmp to an odd addresses will mask off that lsb. It is
3123 * simply there to let sw know there was an exception on a dslot.
3124 *
3125 * When the software returns from an exception, the branch will re-execute.
3126 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3127 * and the branch and delayslot dont share pages.
3128 *
3129 * The TB contaning the branch insn will set up env->btarget and evaluate
3130 * env->btaken. When the translation loop exits we will note that the branch
3131 * sequence is broken and let env->dslot be the size of the branch insn (those
3132 * vary in length).
3133 *
3134 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3135 * set). It will also expect to have env->dslot setup with the size of the
3136 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3137 * will execute the dslot and take the branch, either to btarget or just one
3138 * insn ahead.
3139 *
3140 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3141 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3142 * branch and set lsb). Then env->dslot gets cleared so that the exception
3143 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3144 * masked off and we will reexecute the branch insn.
3145 *
3146 */
3147
3148 /* generate intermediate code for basic block 'tb'. */
3149 static void
3150 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3151 int search_pc)
3152 {
3153 uint16_t *gen_opc_end;
3154 uint32_t pc_start;
3155 unsigned int insn_len;
3156 int j, lj;
3157 struct DisasContext ctx;
3158 struct DisasContext *dc = &ctx;
3159 uint32_t next_page_start;
3160 target_ulong npc;
3161 int num_insns;
3162 int max_insns;
3163
3164 if (!logfile)
3165 logfile = stderr;
3166
3167 /* Odd PC indicates that branch is rexecuting due to exception in the
3168 * delayslot, like in real hw.
3169 */
3170 pc_start = tb->pc & ~1;
3171 dc->env = env;
3172 dc->tb = tb;
3173
3174 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3175
3176 dc->is_jmp = DISAS_NEXT;
3177 dc->ppc = pc_start;
3178 dc->pc = pc_start;
3179 dc->singlestep_enabled = env->singlestep_enabled;
3180 dc->flags_uptodate = 1;
3181 dc->flagx_known = 1;
3182 dc->flags_x = tb->flags & X_FLAG;
3183 dc->cc_x_uptodate = 0;
3184 dc->cc_mask = 0;
3185 dc->update_cc = 0;
3186
3187 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3188 dc->cc_size_uptodate = -1;
3189
3190 /* Decode TB flags. */
3191 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
3192 dc->delayed_branch = !!(tb->flags & 7);
3193 if (dc->delayed_branch)
3194 dc->jmp = JMP_INDIRECT;
3195 else
3196 dc->jmp = JMP_NOJMP;
3197
3198 dc->cpustate_changed = 0;
3199
3200 if (loglevel & CPU_LOG_TB_IN_ASM) {
3201 fprintf(logfile,
3202 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3203 "pid=%x usp=%x\n"
3204 "%x.%x.%x.%x\n"
3205 "%x.%x.%x.%x\n"
3206 "%x.%x.%x.%x\n"
3207 "%x.%x.%x.%x\n",
3208 search_pc, dc->pc, dc->ppc,
3209 (unsigned long long)tb->flags,
3210 env->btarget, (unsigned)tb->flags & 7,
3211 env->pregs[PR_CCS],
3212 env->pregs[PR_PID], env->pregs[PR_USP],
3213 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3214 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3215 env->regs[8], env->regs[9],
3216 env->regs[10], env->regs[11],
3217 env->regs[12], env->regs[13],
3218 env->regs[14], env->regs[15]);
3219 fprintf(logfile, "--------------\n");
3220 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3221 }
3222
3223 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3224 lj = -1;
3225 num_insns = 0;
3226 max_insns = tb->cflags & CF_COUNT_MASK;
3227 if (max_insns == 0)
3228 max_insns = CF_COUNT_MASK;
3229
3230 gen_icount_start();
3231 do
3232 {
3233 check_breakpoint(env, dc);
3234
3235 if (search_pc) {
3236 j = gen_opc_ptr - gen_opc_buf;
3237 if (lj < j) {
3238 lj++;
3239 while (lj < j)
3240 gen_opc_instr_start[lj++] = 0;
3241 }
3242 if (dc->delayed_branch == 1)
3243 gen_opc_pc[lj] = dc->ppc | 1;
3244 else
3245 gen_opc_pc[lj] = dc->pc;
3246 gen_opc_instr_start[lj] = 1;
3247 gen_opc_icount[lj] = num_insns;
3248 }
3249
3250 /* Pretty disas. */
3251 DIS(fprintf(logfile, "%8.8x:\t", dc->pc));
3252
3253 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3254 gen_io_start();
3255 dc->clear_x = 1;
3256
3257 insn_len = cris_decoder(dc);
3258 dc->ppc = dc->pc;
3259 dc->pc += insn_len;
3260 if (dc->clear_x)
3261 cris_clear_x_flag(dc);
3262
3263 num_insns++;
3264 /* Check for delayed branches here. If we do it before
3265 actually generating any host code, the simulator will just
3266 loop doing nothing for on this program location. */
3267 if (dc->delayed_branch) {
3268 dc->delayed_branch--;
3269 if (dc->delayed_branch == 0)
3270 {
3271 if (tb->flags & 7)
3272 t_gen_mov_env_TN(dslot,
3273 tcg_const_tl(0));
3274 if (dc->jmp == JMP_DIRECT) {
3275 dc->is_jmp = DISAS_NEXT;
3276 } else {
3277 t_gen_cc_jmp(env_btarget,
3278 tcg_const_tl(dc->pc));
3279 dc->is_jmp = DISAS_JUMP;
3280 }
3281 break;
3282 }
3283 }
3284
3285 /* If we are rexecuting a branch due to exceptions on
3286 delay slots dont break. */
3287 if (!(tb->pc & 1) && env->singlestep_enabled)
3288 break;
3289 } while (!dc->is_jmp && !dc->cpustate_changed
3290 && gen_opc_ptr < gen_opc_end
3291 && (dc->pc < next_page_start)
3292 && num_insns < max_insns);
3293
3294 npc = dc->pc;
3295 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3296 npc = dc->jmp_pc;
3297
3298 if (tb->cflags & CF_LAST_IO)
3299 gen_io_end();
3300 /* Force an update if the per-tb cpu state has changed. */
3301 if (dc->is_jmp == DISAS_NEXT
3302 && (dc->cpustate_changed || !dc->flagx_known
3303 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3304 dc->is_jmp = DISAS_UPDATE;
3305 tcg_gen_movi_tl(env_pc, npc);
3306 }
3307 /* Broken branch+delayslot sequence. */
3308 if (dc->delayed_branch == 1) {
3309 /* Set env->dslot to the size of the branch insn. */
3310 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3311 cris_store_direct_jmp(dc);
3312 }
3313
3314 cris_evaluate_flags (dc);
3315
3316 if (unlikely(env->singlestep_enabled)) {
3317 if (dc->is_jmp == DISAS_NEXT)
3318 tcg_gen_movi_tl(env_pc, npc);
3319 t_gen_raise_exception(EXCP_DEBUG);
3320 } else {
3321 switch(dc->is_jmp) {
3322 case DISAS_NEXT:
3323 gen_goto_tb(dc, 1, npc);
3324 break;
3325 default:
3326 case DISAS_JUMP:
3327 case DISAS_UPDATE:
3328 /* indicate that the hash table must be used
3329 to find the next TB */
3330 tcg_gen_exit_tb(0);
3331 break;
3332 case DISAS_SWI:
3333 case DISAS_TB_JUMP:
3334 /* nothing more to generate */
3335 break;
3336 }
3337 }
3338 gen_icount_end(tb, num_insns);
3339 *gen_opc_ptr = INDEX_op_end;
3340 if (search_pc) {
3341 j = gen_opc_ptr - gen_opc_buf;
3342 lj++;
3343 while (lj <= j)
3344 gen_opc_instr_start[lj++] = 0;
3345 } else {
3346 tb->size = dc->pc - pc_start;
3347 tb->icount = num_insns;
3348 }
3349
3350 #ifdef DEBUG_DISAS
3351 #if !DISAS_CRIS
3352 if (loglevel & CPU_LOG_TB_IN_ASM) {
3353 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
3354 fprintf(logfile, "\nisize=%d osize=%zd\n",
3355 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3356 }
3357 #endif
3358 #endif
3359 }
3360
3361 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3362 {
3363 gen_intermediate_code_internal(env, tb, 0);
3364 }
3365
3366 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3367 {
3368 gen_intermediate_code_internal(env, tb, 1);
3369 }
3370
3371 void cpu_dump_state (CPUState *env, FILE *f,
3372 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3373 int flags)
3374 {
3375 int i;
3376 uint32_t srs;
3377
3378 if (!env || !f)
3379 return;
3380
3381 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3382 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3383 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3384 env->cc_op,
3385 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3386
3387
3388 for (i = 0; i < 16; i++) {
3389 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3390 if ((i + 1) % 4 == 0)
3391 cpu_fprintf(f, "\n");
3392 }
3393 cpu_fprintf(f, "\nspecial regs:\n");
3394 for (i = 0; i < 16; i++) {
3395 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3396 if ((i + 1) % 4 == 0)
3397 cpu_fprintf(f, "\n");
3398 }
3399 srs = env->pregs[PR_SRS];
3400 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3401 if (srs < 256) {
3402 for (i = 0; i < 16; i++) {
3403 cpu_fprintf(f, "s%2.2d=%8.8x ",
3404 i, env->sregs[srs][i]);
3405 if ((i + 1) % 4 == 0)
3406 cpu_fprintf(f, "\n");
3407 }
3408 }
3409 cpu_fprintf(f, "\n\n");
3410
3411 }
3412
3413 CPUCRISState *cpu_cris_init (const char *cpu_model)
3414 {
3415 CPUCRISState *env;
3416 static int tcg_initialized = 0;
3417 int i;
3418
3419 env = qemu_mallocz(sizeof(CPUCRISState));
3420 if (!env)
3421 return NULL;
3422
3423 cpu_exec_init(env);
3424 cpu_reset(env);
3425
3426 if (tcg_initialized)
3427 return env;
3428
3429 tcg_initialized = 1;
3430
3431 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3432 #if TARGET_LONG_BITS > HOST_LONG_BITS
3433 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3434 TCG_AREG0, offsetof(CPUState, t0), "T0");
3435 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3436 TCG_AREG0, offsetof(CPUState, t1), "T1");
3437 #else
3438 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3439 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3440 #endif
3441
3442 cc_x = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3443 offsetof(CPUState, cc_x), "cc_x");
3444 cc_src = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3445 offsetof(CPUState, cc_src), "cc_src");
3446 cc_dest = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3447 offsetof(CPUState, cc_dest),
3448 "cc_dest");
3449 cc_result = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3450 offsetof(CPUState, cc_result),
3451 "cc_result");
3452 cc_op = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3453 offsetof(CPUState, cc_op), "cc_op");
3454 cc_size = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3455 offsetof(CPUState, cc_size),
3456 "cc_size");
3457 cc_mask = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3458 offsetof(CPUState, cc_mask),
3459 "cc_mask");
3460
3461 env_pc = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3462 offsetof(CPUState, pc),
3463 "pc");
3464 env_btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3465 offsetof(CPUState, btarget),
3466 "btarget");
3467 env_btaken = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3468 offsetof(CPUState, btaken),
3469 "btaken");
3470 for (i = 0; i < 16; i++) {
3471 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3472 offsetof(CPUState, regs[i]),
3473 regnames[i]);
3474 }
3475 for (i = 0; i < 16; i++) {
3476 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
3477 offsetof(CPUState, pregs[i]),
3478 pregnames[i]);
3479 }
3480
3481 TCG_HELPER(helper_raise_exception);
3482 TCG_HELPER(helper_dump);
3483
3484 TCG_HELPER(helper_tlb_flush_pid);
3485 TCG_HELPER(helper_movl_sreg_reg);
3486 TCG_HELPER(helper_movl_reg_sreg);
3487 TCG_HELPER(helper_rfe);
3488 TCG_HELPER(helper_rfn);
3489
3490 TCG_HELPER(helper_evaluate_flags_muls);
3491 TCG_HELPER(helper_evaluate_flags_mulu);
3492 TCG_HELPER(helper_evaluate_flags_mcp);
3493 TCG_HELPER(helper_evaluate_flags_alu_4);
3494 TCG_HELPER(helper_evaluate_flags_move_4);
3495 TCG_HELPER(helper_evaluate_flags_move_2);
3496 TCG_HELPER(helper_evaluate_flags);
3497 TCG_HELPER(helper_top_evaluate_flags);
3498 return env;
3499 }
3500
3501 void cpu_reset (CPUCRISState *env)
3502 {
3503 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3504 tlb_flush(env, 1);
3505
3506 env->pregs[PR_VR] = 32;
3507 #if defined(CONFIG_USER_ONLY)
3508 /* start in user mode with interrupts enabled. */
3509 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3510 #else
3511 env->pregs[PR_CCS] = 0;
3512 #endif
3513 }
3514
3515 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3516 unsigned long searched_pc, int pc_pos, void *puc)
3517 {
3518 env->pc = gen_opc_pc[pc_pos];
3519 }
jz4740 based target emulation