target-cris/cpu.h

   1 /*
   2  *  CRIS virtual CPU header
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #ifndef CPU_CRIS_H
  22 #define CPU_CRIS_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #include "cpu-defs.h"
  27
  28 #include "softfloat.h"
  29
  30 #define TARGET_HAS_ICE 1
  31
  32 #define ELF_MACHINE     EM_CRIS
  33
  34 #define EXCP_MMU_EXEC    0
  35 #define EXCP_MMU_READ    1
  36 #define EXCP_MMU_WRITE   2
  37 #define EXCP_MMU_FLUSH   3
  38 #define EXCP_MMU_FAULT   4
  39 #define EXCP_BREAK      16 /* trap.  */
  40
  41 /* Register aliases. R0 - R15 */
  42 #define R_FP  8
  43 #define R_SP  14
  44 #define R_ACR 15
  45
  46 /* Support regs, P0 - P15  */
  47 #define PR_BZ  0
  48 #define PR_VR  1
  49 #define PR_PID 2
  50 #define PR_SRS 3
  51 #define PR_WZ  4
  52 #define PR_EXS 5
  53 #define PR_EDA 6
  54 #define PR_MOF 7
  55 #define PR_DZ  8
  56 #define PR_EBP 9
  57 #define PR_ERP 10
  58 #define PR_SRP 11
  59 #define PR_CCS 13
  60 #define PR_USP 14
  61 #define PR_SPC 15
  62
  63 /* CPU flags.  */
  64 #define S_FLAG 0x200
  65 #define R_FLAG 0x100
  66 #define P_FLAG 0x80
  67 #define U_FLAG 0x40
  68 #define P_FLAG 0x80
  69 #define U_FLAG 0x40
  70 #define I_FLAG 0x20
  71 #define X_FLAG 0x10
  72 #define N_FLAG 0x08
  73 #define Z_FLAG 0x04
  74 #define V_FLAG 0x02
  75 #define C_FLAG 0x01
  76 #define ALU_FLAGS 0x1F
  77
  78 /* Condition codes.  */
  79 #define CC_CC   0
  80 #define CC_CS   1
  81 #define CC_NE   2
  82 #define CC_EQ   3
  83 #define CC_VC   4
  84 #define CC_VS   5
  85 #define CC_PL   6
  86 #define CC_MI   7
  87 #define CC_LS   8
  88 #define CC_HI   9
  89 #define CC_GE  10
  90 #define CC_LT  11
  91 #define CC_GT  12
  92 #define CC_LE  13
  93 #define CC_A   14
  94 #define CC_P   15
  95
  96 /* Internal flags for the implementation.  */
  97 #define F_DELAYSLOT 1
  98
  99 #define NB_MMU_MODES 2
 100
 101 typedef struct CPUCRISState {
 102         uint32_t regs[16];
 103         /* P0 - P15 are referred to as special registers in the docs.  */
 104         uint32_t pregs[16];
 105
 106         /* Pseudo register for the PC. Not directly accessable on CRIS.  */
 107         uint32_t pc;
 108
 109         /* Pseudo register for the kernel stack.  */
 110         uint32_t ksp;
 111
 112         /* These are setup up by the guest code just before transfering the
 113            control back to the host.  */
 114         int jmp;
 115         uint32_t btarget;
 116         int btaken;
 117
 118         /* Condition flag tracking.  */
 119         uint32_t cc_op;
 120         uint32_t cc_mask;
 121         uint32_t cc_dest;
 122         uint32_t cc_src;
 123         uint32_t cc_result;
 124
 125         /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 126         int cc_size;
 127
 128         /* Extended arithmetics.  */
 129         int cc_x_live;
 130         int cc_x;
 131
 132         int exception_index;
 133         int interrupt_request;
 134         int interrupt_vector;
 135         int fault_vector;
 136         int trap_vector;
 137
 138         uint32_t debug1;
 139         uint32_t debug2;
 140         uint32_t debug3;
 141
 142         struct
 143         {
 144                 int exec_insns;
 145                 int exec_loads;
 146                 int exec_stores;
 147         } stats;
 148
 149         /* FIXME: add a check in the translator to avoid writing to support
 150            register sets beyond the 4th. The ISA allows up to 256! but in
 151            practice there is no core that implements more than 4.
 152
 153            Support function registers are used to control units close to the
 154            core. Accesses do not pass down the normal hierarchy.
 155         */
 156         uint32_t sregs[4][16];
 157
 158         /*
 159          * We just store the stores to the tlbset here for later evaluation
 160          * when the hw needs access to them.
 161          *
 162          * One for I and another for D.
 163          */
 164         struct
 165         {
 166                 uint32_t hi;
 167                 uint32_t lo;
 168         } tlbsets[2][4][16];
 169
 170         int features;
 171         int user_mode_only;
 172         int halted;
 173
 174         jmp_buf jmp_env;
 175         CPU_COMMON
 176 } CPUCRISState;
 177
 178 CPUCRISState *cpu_cris_init(const char *cpu_model);
 179 int cpu_cris_exec(CPUCRISState *s);
 180 void cpu_cris_close(CPUCRISState *s);
 181 void do_interrupt(CPUCRISState *env);
 182 /* you can call this signal handler from your SIGBUS and SIGSEGV
 183    signal handlers to inform the virtual CPU of exceptions. non zero
 184    is returned if the signal was handled by the virtual CPU.  */
 185 int cpu_cris_signal_handler(int host_signum, void *pinfo,
 186                            void *puc);
 187 void cpu_cris_flush_flags(CPUCRISState *, int);
 188
 189
 190 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 191                           int is_asi);
 192
 193 enum {
 194     CC_OP_DYNAMIC, /* Use env->cc_op  */
 195     CC_OP_FLAGS,
 196     CC_OP_LOGIC,
 197     CC_OP_CMP,
 198     CC_OP_MOVE,
 199     CC_OP_MOVE_PD,
 200     CC_OP_MOVE_SD,
 201     CC_OP_ADD,
 202     CC_OP_ADDC,
 203     CC_OP_MCP,
 204     CC_OP_ADDU,
 205     CC_OP_SUB,
 206     CC_OP_SUBU,
 207     CC_OP_NEG,
 208     CC_OP_BTST,
 209     CC_OP_MULS,
 210     CC_OP_MULU,
 211     CC_OP_DSTEP,
 212     CC_OP_BOUND,
 213
 214     CC_OP_OR,
 215     CC_OP_AND,
 216     CC_OP_XOR,
 217     CC_OP_LSL,
 218     CC_OP_LSR,
 219     CC_OP_ASR,
 220     CC_OP_LZ
 221 };
 222
 223 #define CCF_C 0x01
 224 #define CCF_V 0x02
 225 #define CCF_Z 0x04
 226 #define CCF_N 0x08
 227 #define CCF_X 0x10
 228
 229 #define CRIS_SSP    0
 230 #define CRIS_USP    1
 231
 232 void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector);
 233 void cris_set_macsr(CPUCRISState *env, uint32_t val);
 234 void cris_switch_sp(CPUCRISState *env);
 235
 236 void do_cris_semihosting(CPUCRISState *env, int nr);
 237
 238 enum cris_features {
 239     CRIS_FEATURE_CF_ISA_MUL,
 240 };
 241
 242 static inline int cris_feature(CPUCRISState *env, int feature)
 243 {
 244     return (env->features & (1u << feature)) != 0;
 245 }
 246
 247 void register_cris_insns (CPUCRISState *env);
 248
 249 /* CRIS uses 8k pages.  */
 250 #define TARGET_PAGE_BITS 13
 251 #define MMAP_SHIFT TARGET_PAGE_BITS
 252
 253 #define CPUState CPUCRISState
 254 #define cpu_init cpu_cris_init
 255 #define cpu_exec cpu_cris_exec
 256 #define cpu_gen_code cpu_cris_gen_code
 257 #define cpu_signal_handler cpu_cris_signal_handler
 258
 259 /* MMU modes definitions */
 260 #define MMU_MODE0_SUFFIX _kernel
 261 #define MMU_MODE1_SUFFIX _user
 262 #define MMU_USER_IDX 1
 263 static inline int cpu_mmu_index (CPUState *env)
 264 {
 265         return !!(env->pregs[PR_CCS] & U_FLAG);
 266 }
 267
 268 /* Support function regs.  */
 269 #define SFR_RW_GC_CFG      0][0
 270 #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 271 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 272 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 273 #define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 274 #define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 275 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 276 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 277
 278 #include "cpu-all.h"
 279 #endif