hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "console.h"
  27 #include "net.h"
  28
  29 //#define DEBUG_PCI
  30
  31 struct PCIBus {
  32     int bus_num;
  33     int devfn_min;
  34     pci_set_irq_fn set_irq;
  35     pci_map_irq_fn map_irq;
  36     uint32_t config_reg; /* XXX: suppress */
  37     /* low level pic */
  38     SetIRQFunc *low_set_irq;
  39     qemu_irq *irq_opaque;
  40     PCIDevice *devices[256];
  41     PCIDevice *parent_dev;
  42     PCIBus *next;
  43     /* The bus IRQ state is the logical OR of the connected devices.
  44        Keep a count of the number of devices with raised IRQs.  */
  45     int nirq;
  46     int irq_count[];
  47 };
  48
  49 static void pci_update_mappings(PCIDevice *d);
  50 static void pci_set_irq(void *opaque, int irq_num, int level);
  51
  52 target_phys_addr_t pci_mem_base;
  53 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  54 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  55 static int pci_irq_index;
  56 static PCIBus *first_bus;
  57
  58 static void pcibus_save(QEMUFile *f, void *opaque)
  59 {
  60     PCIBus *bus = (PCIBus *)opaque;
  61     int i;
  62
  63     qemu_put_be32(f, bus->nirq);
  64     for (i = 0; i < bus->nirq; i++)
  65         qemu_put_be32(f, bus->irq_count[i]);
  66 }
  67
  68 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  69 {
  70     PCIBus *bus = (PCIBus *)opaque;
  71     int i, nirq;
  72
  73     if (version_id != 1)
  74         return -EINVAL;
  75
  76     nirq = qemu_get_be32(f);
  77     if (bus->nirq != nirq) {
  78         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  79                 nirq, bus->nirq);
  80         return -EINVAL;
  81     }
  82
  83     for (i = 0; i < nirq; i++)
  84         bus->irq_count[i] = qemu_get_be32(f);
  85
  86     return 0;
  87 }
  88
  89 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  90                          qemu_irq *pic, int devfn_min, int nirq)
  91 {
  92     PCIBus *bus;
  93     static int nbus = 0;
  94
  95     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  96     bus->set_irq = set_irq;
  97     bus->map_irq = map_irq;
  98     bus->irq_opaque = pic;
  99     bus->devfn_min = devfn_min;
 100     bus->nirq = nirq;
 101     first_bus = bus;
 102     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 103     return bus;
 104 }
 105
 106 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 107 {
 108     PCIBus *bus;
 109     bus = qemu_mallocz(sizeof(PCIBus));
 110     bus->map_irq = map_irq;
 111     bus->parent_dev = dev;
 112     bus->next = dev->bus->next;
 113     dev->bus->next = bus;
 114     return bus;
 115 }
 116
 117 int pci_bus_num(PCIBus *s)
 118 {
 119     return s->bus_num;
 120 }
 121
 122 void pci_device_save(PCIDevice *s, QEMUFile *f)
 123 {
 124     int i;
 125
 126     qemu_put_be32(f, 2); /* PCI device version */
 127     qemu_put_buffer(f, s->config, 256);
 128     for (i = 0; i < 4; i++)
 129         qemu_put_be32(f, s->irq_state[i]);
 130 }
 131
 132 int pci_device_load(PCIDevice *s, QEMUFile *f)
 133 {
 134     uint32_t version_id;
 135     int i;
 136
 137     version_id = qemu_get_be32(f);
 138     if (version_id > 2)
 139         return -EINVAL;
 140     qemu_get_buffer(f, s->config, 256);
 141     pci_update_mappings(s);
 142
 143     if (version_id >= 2)
 144         for (i = 0; i < 4; i ++)
 145             s->irq_state[i] = qemu_get_be32(f);
 146
 147     return 0;
 148 }
 149
 150 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 151 {
 152     uint16_t *id;
 153
 154     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 155     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 156     id[1] = cpu_to_le16(pci_default_sub_device_id);
 157     return 0;
 158 }
 159
 160 /* -1 for devfn means auto assign */
 161 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 162                                int instance_size, int devfn,
 163                                PCIConfigReadFunc *config_read,
 164                                PCIConfigWriteFunc *config_write)
 165 {
 166     PCIDevice *pci_dev;
 167
 168     if (pci_irq_index >= PCI_DEVICES_MAX)
 169         return NULL;
 170
 171     if (devfn < 0) {
 172         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 173             if (!bus->devices[devfn])
 174                 goto found;
 175         }
 176         return NULL;
 177     found: ;
 178     }
 179     pci_dev = qemu_mallocz(instance_size);
 180     if (!pci_dev)
 181         return NULL;
 182     pci_dev->bus = bus;
 183     pci_dev->devfn = devfn;
 184     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 185     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 186     pci_set_default_subsystem_id(pci_dev);
 187
 188     if (!config_read)
 189         config_read = pci_default_read_config;
 190     if (!config_write)
 191         config_write = pci_default_write_config;
 192     pci_dev->config_read = config_read;
 193     pci_dev->config_write = config_write;
 194     pci_dev->irq_index = pci_irq_index++;
 195     bus->devices[devfn] = pci_dev;
 196     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 197     return pci_dev;
 198 }
 199
 200 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 201                             uint32_t size, int type,
 202                             PCIMapIORegionFunc *map_func)
 203 {
 204     PCIIORegion *r;
 205     uint32_t addr;
 206
 207     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 208         return;
 209     r = &pci_dev->io_regions[region_num];
 210     r->addr = -1;
 211     r->size = size;
 212     r->type = type;
 213     r->map_func = map_func;
 214     if (region_num == PCI_ROM_SLOT) {
 215         addr = 0x30;
 216     } else {
 217         addr = 0x10 + region_num * 4;
 218     }
 219     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 220 }
 221
 222 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 223 {
 224     return addr + pci_mem_base;
 225 }
 226
 227 static void pci_update_mappings(PCIDevice *d)
 228 {
 229     PCIIORegion *r;
 230     int cmd, i;
 231     uint32_t last_addr, new_addr, config_ofs;
 232
 233     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 234     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 235         r = &d->io_regions[i];
 236         if (i == PCI_ROM_SLOT) {
 237             config_ofs = 0x30;
 238         } else {
 239             config_ofs = 0x10 + i * 4;
 240         }
 241         if (r->size != 0) {
 242             if (r->type & PCI_ADDRESS_SPACE_IO) {
 243                 if (cmd & PCI_COMMAND_IO) {
 244                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 245                                                          config_ofs));
 246                     new_addr = new_addr & ~(r->size - 1);
 247                     last_addr = new_addr + r->size - 1;
 248                     /* NOTE: we have only 64K ioports on PC */
 249                     if (last_addr <= new_addr || new_addr == 0 ||
 250                         last_addr >= 0x10000) {
 251                         new_addr = -1;
 252                     }
 253                 } else {
 254                     new_addr = -1;
 255                 }
 256             } else {
 257                 if (cmd & PCI_COMMAND_MEMORY) {
 258                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 259                                                          config_ofs));
 260                     /* the ROM slot has a specific enable bit */
 261                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 262                         goto no_mem_map;
 263                     new_addr = new_addr & ~(r->size - 1);
 264                     last_addr = new_addr + r->size - 1;
 265                     /* NOTE: we do not support wrapping */
 266                     /* XXX: as we cannot support really dynamic
 267                        mappings, we handle specific values as invalid
 268                        mappings. */
 269                     if (last_addr <= new_addr || new_addr == 0 ||
 270                         last_addr == -1) {
 271                         new_addr = -1;
 272                     }
 273                 } else {
 274                 no_mem_map:
 275                     new_addr = -1;
 276                 }
 277             }
 278             /* now do the real mapping */
 279             if (new_addr != r->addr) {
 280                 if (r->addr != -1) {
 281                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 282                         int class;
 283                         /* NOTE: specific hack for IDE in PC case:
 284                            only one byte must be mapped. */
 285                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 286                         if (class == 0x0101 && r->size == 4) {
 287                             isa_unassign_ioport(r->addr + 2, 1);
 288                         } else {
 289                             isa_unassign_ioport(r->addr, r->size);
 290                         }
 291                     } else {
 292                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 293                                                      r->size,
 294                                                      IO_MEM_UNASSIGNED);
 295                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 296                     }
 297                 }
 298                 r->addr = new_addr;
 299                 if (r->addr != -1) {
 300                     r->map_func(d, i, r->addr, r->size, r->type);
 301                 }
 302             }
 303         }
 304     }
 305 }
 306
 307 uint32_t pci_default_read_config(PCIDevice *d,
 308                                  uint32_t address, int len)
 309 {
 310     uint32_t val;
 311
 312     switch(len) {
 313     default:
 314     case 4:
 315         if (address <= 0xfc) {
 316             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 317             break;
 318         }
 319         /* fall through */
 320     case 2:
 321         if (address <= 0xfe) {
 322             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 323             break;
 324         }
 325         /* fall through */
 326     case 1:
 327         val = d->config[address];
 328         break;
 329     }
 330     return val;
 331 }
 332
 333 void pci_default_write_config(PCIDevice *d,
 334                               uint32_t address, uint32_t val, int len)
 335 {
 336     int can_write, i;
 337     uint32_t end, addr;
 338
 339     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 340                      (address >= 0x30 && address < 0x34))) {
 341         PCIIORegion *r;
 342         int reg;
 343
 344         if ( address >= 0x30 ) {
 345             reg = PCI_ROM_SLOT;
 346         }else{
 347             reg = (address - 0x10) >> 2;
 348         }
 349         r = &d->io_regions[reg];
 350         if (r->size == 0)
 351             goto default_config;
 352         /* compute the stored value */
 353         if (reg == PCI_ROM_SLOT) {
 354             /* keep ROM enable bit */
 355             val &= (~(r->size - 1)) | 1;
 356         } else {
 357             val &= ~(r->size - 1);
 358             val |= r->type;
 359         }
 360         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 361         pci_update_mappings(d);
 362         return;
 363     }
 364  default_config:
 365     /* not efficient, but simple */
 366     addr = address;
 367     for(i = 0; i < len; i++) {
 368         /* default read/write accesses */
 369         switch(d->config[0x0e]) {
 370         case 0x00:
 371         case 0x80:
 372             switch(addr) {
 373             case 0x00:
 374             case 0x01:
 375             case 0x02:
 376             case 0x03:
 377             case 0x08:
 378             case 0x09:
 379             case 0x0a:
 380             case 0x0b:
 381             case 0x0e:
 382             case 0x10 ... 0x27: /* base */
 383             case 0x30 ... 0x33: /* rom */
 384             case 0x3d:
 385                 can_write = 0;
 386                 break;
 387             default:
 388                 can_write = 1;
 389                 break;
 390             }
 391             break;
 392         default:
 393         case 0x01:
 394             switch(addr) {
 395             case 0x00:
 396             case 0x01:
 397             case 0x02:
 398             case 0x03:
 399             case 0x08:
 400             case 0x09:
 401             case 0x0a:
 402             case 0x0b:
 403             case 0x0e:
 404             case 0x38 ... 0x3b: /* rom */
 405             case 0x3d:
 406                 can_write = 0;
 407                 break;
 408             default:
 409                 can_write = 1;
 410                 break;
 411             }
 412             break;
 413         }
 414         if (can_write) {
 415             d->config[addr] = val;
 416         }
 417         if (++addr > 0xff)
 418                 break;
 419         val >>= 8;
 420     }
 421
 422     end = address + len;
 423     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 424         /* if the command register is modified, we must modify the mappings */
 425         pci_update_mappings(d);
 426     }
 427 }
 428
 429 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 430 {
 431     PCIBus *s = opaque;
 432     PCIDevice *pci_dev;
 433     int config_addr, bus_num;
 434
 435 #if defined(DEBUG_PCI) && 0
 436     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 437            addr, val, len);
 438 #endif
 439     bus_num = (addr >> 16) & 0xff;
 440     while (s && s->bus_num != bus_num)
 441         s = s->next;
 442     if (!s)
 443         return;
 444     pci_dev = s->devices[(addr >> 8) & 0xff];
 445     if (!pci_dev)
 446         return;
 447     config_addr = addr & 0xff;
 448 #if defined(DEBUG_PCI)
 449     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 450            pci_dev->name, config_addr, val, len);
 451 #endif
 452     pci_dev->config_write(pci_dev, config_addr, val, len);
 453 }
 454
 455 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 456 {
 457     PCIBus *s = opaque;
 458     PCIDevice *pci_dev;
 459     int config_addr, bus_num;
 460     uint32_t val;
 461
 462     bus_num = (addr >> 16) & 0xff;
 463     while (s && s->bus_num != bus_num)
 464         s= s->next;
 465     if (!s)
 466         goto fail;
 467     pci_dev = s->devices[(addr >> 8) & 0xff];
 468     if (!pci_dev) {
 469     fail:
 470         switch(len) {
 471         case 1:
 472             val = 0xff;
 473             break;
 474         case 2:
 475             val = 0xffff;
 476             break;
 477         default:
 478         case 4:
 479             val = 0xffffffff;
 480             break;
 481         }
 482         goto the_end;
 483     }
 484     config_addr = addr & 0xff;
 485     val = pci_dev->config_read(pci_dev, config_addr, len);
 486 #if defined(DEBUG_PCI)
 487     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 488            pci_dev->name, config_addr, val, len);
 489 #endif
 490  the_end:
 491 #if defined(DEBUG_PCI) && 0
 492     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 493            addr, val, len);
 494 #endif
 495     return val;
 496 }
 497
 498 /***********************************************************/
 499 /* generic PCI irq support */
 500
 501 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 502 static void pci_set_irq(void *opaque, int irq_num, int level)
 503 {
 504     PCIDevice *pci_dev = (PCIDevice *)opaque;
 505     PCIBus *bus;
 506     int change;
 507
 508     change = level - pci_dev->irq_state[irq_num];
 509     if (!change)
 510         return;
 511
 512     pci_dev->irq_state[irq_num] = level;
 513     for (;;) {
 514         bus = pci_dev->bus;
 515         irq_num = bus->map_irq(pci_dev, irq_num);
 516         if (bus->set_irq)
 517             break;
 518         pci_dev = bus->parent_dev;
 519     }
 520     bus->irq_count[irq_num] += change;
 521     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 522 }
 523
 524 /***********************************************************/
 525 /* monitor info on PCI */
 526
 527 typedef struct {
 528     uint16_t class;
 529     const char *desc;
 530 } pci_class_desc;
 531
 532 static const pci_class_desc pci_class_descriptions[] =
 533 {
 534     { 0x0100, "SCSI controller"},
 535     { 0x0101, "IDE controller"},
 536     { 0x0102, "Floppy controller"},
 537     { 0x0103, "IPI controller"},
 538     { 0x0104, "RAID controller"},
 539     { 0x0106, "SATA controller"},
 540     { 0x0107, "SAS controller"},
 541     { 0x0180, "Storage controller"},
 542     { 0x0200, "Ethernet controller"},
 543     { 0x0201, "Token Ring controller"},
 544     { 0x0202, "FDDI controller"},
 545     { 0x0203, "ATM controller"},
 546     { 0x0280, "Network controller"},
 547     { 0x0300, "VGA controller"},
 548     { 0x0301, "XGA controller"},
 549     { 0x0302, "3D controller"},
 550     { 0x0380, "Display controller"},
 551     { 0x0400, "Video controller"},
 552     { 0x0401, "Audio controller"},
 553     { 0x0402, "Phone"},
 554     { 0x0480, "Multimedia controller"},
 555     { 0x0500, "RAM controller"},
 556     { 0x0501, "Flash controller"},
 557     { 0x0580, "Memory controller"},
 558     { 0x0600, "Host bridge"},
 559     { 0x0601, "ISA bridge"},
 560     { 0x0602, "EISA bridge"},
 561     { 0x0603, "MC bridge"},
 562     { 0x0604, "PCI bridge"},
 563     { 0x0605, "PCMCIA bridge"},
 564     { 0x0606, "NUBUS bridge"},
 565     { 0x0607, "CARDBUS bridge"},
 566     { 0x0608, "RACEWAY bridge"},
 567     { 0x0680, "Bridge"},
 568     { 0x0c03, "USB controller"},
 569     { 0, NULL}
 570 };
 571
 572 static void pci_info_device(PCIDevice *d)
 573 {
 574     int i, class;
 575     PCIIORegion *r;
 576     const pci_class_desc *desc;
 577
 578     term_printf("  Bus %2d, device %3d, function %d:\n",
 579            d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 580     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 581     term_printf("    ");
 582     desc = pci_class_descriptions;
 583     while (desc->desc && class != desc->class)
 584         desc++;
 585     if (desc->desc) {
 586         term_printf("%s", desc->desc);
 587     } else {
 588         term_printf("Class %04x", class);
 589     }
 590     term_printf(": PCI device %04x:%04x\n",
 591            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 592            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 593
 594     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 595         term_printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
 596     }
 597     if (class == 0x0604) {
 598         term_printf("      BUS %d.\n", d->config[0x19]);
 599     }
 600     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 601         r = &d->io_regions[i];
 602         if (r->size != 0) {
 603             term_printf("      BAR%d: ", i);
 604             if (r->type & PCI_ADDRESS_SPACE_IO) {
 605                 term_printf("I/O at 0x%04x [0x%04x].\n",
 606                        r->addr, r->addr + r->size - 1);
 607             } else {
 608                 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
 609                        r->addr, r->addr + r->size - 1);
 610             }
 611         }
 612     }
 613     if (class == 0x0604 && d->config[0x19] != 0) {
 614         pci_for_each_device(d->config[0x19], pci_info_device);
 615     }
 616 }
 617
 618 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 619 {
 620     PCIBus *bus = first_bus;
 621     PCIDevice *d;
 622     int devfn;
 623
 624     while (bus && bus->bus_num != bus_num)
 625         bus = bus->next;
 626     if (bus) {
 627         for(devfn = 0; devfn < 256; devfn++) {
 628             d = bus->devices[devfn];
 629             if (d)
 630                 fn(d);
 631         }
 632     }
 633 }
 634
 635 void pci_info(void)
 636 {
 637     pci_for_each_device(0, pci_info_device);
 638 }
 639
 640 /* Initialize a PCI NIC.  */
 641 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn)
 642 {
 643     if (strcmp(nd->model, "ne2k_pci") == 0) {
 644         pci_ne2000_init(bus, nd, devfn);
 645     } else if (strcmp(nd->model, "i82551") == 0) {
 646         pci_i82551_init(bus, nd, devfn);
 647     } else if (strcmp(nd->model, "i82557b") == 0) {
 648         pci_i82557b_init(bus, nd, devfn);
 649     } else if (strcmp(nd->model, "i82559er") == 0) {
 650         pci_i82559er_init(bus, nd, devfn);
 651     } else if (strcmp(nd->model, "rtl8139") == 0) {
 652         pci_rtl8139_init(bus, nd, devfn);
 653     } else if (strcmp(nd->model, "e1000") == 0) {
 654         pci_e1000_init(bus, nd, devfn);
 655     } else if (strcmp(nd->model, "pcnet") == 0) {
 656         pci_pcnet_init(bus, nd, devfn);
 657     } else if (strcmp(nd->model, "?") == 0) {
 658         fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
 659                         " ne2k_pci pcnet rtl8139 e1000\n");
 660         exit (1);
 661     } else {
 662         fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 663         exit (1);
 664     }
 665 }
 666
 667 typedef struct {
 668     PCIDevice dev;
 669     PCIBus *bus;
 670 } PCIBridge;
 671
 672 static void pci_bridge_write_config(PCIDevice *d,
 673                              uint32_t address, uint32_t val, int len)
 674 {
 675     PCIBridge *s = (PCIBridge *)d;
 676
 677     if (address == 0x19 || (address == 0x18 && len > 1)) {
 678         if (address == 0x19)
 679             s->bus->bus_num = val & 0xff;
 680         else
 681             s->bus->bus_num = (val >> 8) & 0xff;
 682 #if defined(DEBUG_PCI)
 683         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 684 #endif
 685     }
 686     pci_default_write_config(d, address, val, len);
 687 }
 688
 689 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 690                         pci_map_irq_fn map_irq, const char *name)
 691 {
 692     PCIBridge *s;
 693     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 694                                          devfn, NULL, pci_bridge_write_config);
 695     s->dev.config[0x00] = id >> 16;
 696     s->dev.config[0x01] = id >> 24;
 697     s->dev.config[0x02] = id; // device_id
 698     s->dev.config[0x03] = id >> 8;
 699     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 700     s->dev.config[0x05] = 0x00;
 701     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 702     s->dev.config[0x07] = 0x00; // status = fast devsel
 703     s->dev.config[0x08] = 0x00; // revision
 704     s->dev.config[0x09] = 0x00; // programming i/f
 705     s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
 706     s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
 707     s->dev.config[0x0D] = 0x10; // latency_timer
 708     s->dev.config[0x0E] = 0x81; // header_type
 709     s->dev.config[0x1E] = 0xa0; // secondary status
 710
 711     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 712     return s->bus;
 713 }