4 /* PCI includes legacy ISA access. */
9 extern target_phys_addr_t pci_mem_base
;
12 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
13 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
14 #define PCI_SUBDEVICE_ID_QEMU 0x1100
16 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
17 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
18 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
20 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
21 uint32_t address
, uint32_t data
, int len
);
22 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
23 uint32_t address
, int len
);
24 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
25 uint32_t addr
, uint32_t size
, int type
);
27 #define PCI_ADDRESS_SPACE_MEM 0x00
28 #define PCI_ADDRESS_SPACE_IO 0x01
29 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
31 typedef struct PCIIORegion
{
32 uint32_t addr
; /* current PCI mapping address. -1 means not mapped */
35 PCIMapIORegionFunc
*map_func
;
38 #define PCI_ROM_SLOT 6
39 #define PCI_NUM_REGIONS 7
41 #define PCI_DEVICES_MAX 64
43 #define PCI_VENDOR_ID 0x00 /* 16 bits */
44 #define PCI_DEVICE_ID 0x02 /* 16 bits */
45 #define PCI_COMMAND 0x04 /* 16 bits */
46 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
47 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
48 #define PCI_REVISION 0x08
49 #define PCI_CLASS_DEVICE 0x0a /* Device class */
50 #define PCI_SUBVENDOR_ID 0x2c /* 16 bits */
51 #define PCI_SUBDEVICE_ID 0x2e /* 16 bits */
52 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
53 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
54 #define PCI_MIN_GNT 0x3e /* 8 bits */
55 #define PCI_MAX_LAT 0x3f /* 8 bits */
57 /* Bits in the PCI Status Register (PCI 2.3 spec) */
58 #define PCI_STATUS_RESERVED1 0x007
59 #define PCI_STATUS_INT_STATUS 0x008
60 #define PCI_STATUS_CAPABILITIES 0x010
61 #define PCI_STATUS_66MHZ 0x020
62 #define PCI_STATUS_RESERVED2 0x040
63 #define PCI_STATUS_FAST_BACK 0x080
64 #define PCI_STATUS_DEVSEL 0x600
66 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
67 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
68 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
70 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
72 /* Bits in the PCI Command Register (PCI 2.3 spec) */
73 #define PCI_COMMAND_RESERVED 0xf800
75 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
78 /* PCI config space */
81 /* the following fields are read only */
85 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
87 /* do not access the following fields */
88 PCIConfigReadFunc
*config_read
;
89 PCIConfigWriteFunc
*config_write
;
90 /* ??? This is a PC-specific hack, and should be removed. */
93 /* IRQ objects for the INTA-INTD pins. */
96 /* Current IRQ levels. Used internally by the generic PCI code. */
100 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
101 int instance_size
, int devfn
,
102 PCIConfigReadFunc
*config_read
,
103 PCIConfigWriteFunc
*config_write
);
105 void pci_register_io_region(PCIDevice
*pci_dev
, int region_num
,
106 uint32_t size
, int type
,
107 PCIMapIORegionFunc
*map_func
);
109 uint32_t pci_default_read_config(PCIDevice
*d
,
110 uint32_t address
, int len
);
111 void pci_default_write_config(PCIDevice
*d
,
112 uint32_t address
, uint32_t val
, int len
);
113 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
114 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
116 typedef void (*pci_set_irq_fn
)(qemu_irq
*pic
, int irq_num
, int level
);
117 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
118 PCIBus
*pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
119 qemu_irq
*pic
, int devfn_min
, int nirq
);
121 void pci_nic_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
122 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
);
123 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
);
124 int pci_bus_num(PCIBus
*s
);
125 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
));
128 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint32_t id
,
129 pci_map_irq_fn map_irq
, const char *name
);
132 #define LSI_MAX_DEVS 7
133 void lsi_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
);
134 void *lsi_scsi_init(PCIBus
*bus
, int devfn
);
137 void pci_vmsvga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
138 unsigned long vga_ram_offset
, int vga_ram_size
);
141 void usb_uhci_piix3_init(PCIBus
*bus
, int devfn
);
142 void usb_uhci_piix4_init(PCIBus
*bus
, int devfn
);
145 void usb_ohci_init_pci(struct PCIBus
*bus
, int num_ports
, int devfn
);
149 void pci_i82551_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
150 void pci_i82557b_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
151 void pci_i82559er_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
155 void pci_ne2000_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
159 void pci_rtl8139_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
162 void pci_e1000_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
165 void pci_pcnet_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
168 PCIBus
*pci_prep_init(qemu_irq
*pic
);
171 PCIBus
*pci_apb_init(target_phys_addr_t special_base
, target_phys_addr_t mem_base
,
175 PCIBus
*sh_pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
176 qemu_irq
*pic
, int devfn_min
, int nirq
);