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Avoid CRIS related warnings by Jan Kiszka.
[qemu/qemu-JZ.git] / hw / sun4m.c
blobe1ff225e381488581721bd43c0fa603b398c606e
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37
38 //#define DEBUG_IRQ
39
40 /*
41 * Sun4m architecture was used in the following machines:
42 *
43 * SPARCserver 6xxMP/xx
44 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
45 * SPARCclassic X (4/10)
46 * SPARCstation LX/ZX (4/30)
47 * SPARCstation Voyager
48 * SPARCstation 10/xx, SPARCserver 10/xx
49 * SPARCstation 5, SPARCserver 5
50 * SPARCstation 20/xx, SPARCserver 20
51 * SPARCstation 4
52 *
53 * Sun4d architecture was used in the following machines:
54 *
55 * SPARCcenter 2000
56 * SPARCserver 1000
57 *
58 * Sun4c architecture was used in the following machines:
59 * SPARCstation 1/1+, SPARCserver 1/1+
60 * SPARCstation SLC
61 * SPARCstation IPC
62 * SPARCstation ELC
63 * SPARCstation IPX
64 *
65 * See for example: http://www.sunhelp.org/faq/sunref1.html
66 */
67
68 #ifdef DEBUG_IRQ
69 #define DPRINTF(fmt, args...) \
70 do { printf("CPUIRQ: " fmt , ##args); } while (0)
71 #else
72 #define DPRINTF(fmt, args...)
73 #endif
74
75 #define KERNEL_LOAD_ADDR 0x00004000
76 #define CMDLINE_ADDR 0x007ff000
77 #define INITRD_LOAD_ADDR 0x00800000
78 #define PROM_SIZE_MAX (512 * 1024)
79 #define PROM_VADDR 0xffd00000
80 #define PROM_FILENAME "openbios-sparc32"
81
82 // Control plane, 8-bit and 24-bit planes
83 #define TCX_SIZE (9 * 1024 * 1024)
84
85 #define MAX_CPUS 16
86 #define MAX_PILS 16
87
88 struct hwdef {
89 target_phys_addr_t iommu_base, slavio_base;
90 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
91 target_phys_addr_t serial_base, fd_base;
92 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
93 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
94 target_phys_addr_t ecc_base;
95 uint32_t ecc_version;
96 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
97 long vram_size, nvram_size;
98 // IRQ numbers are not PIL ones, but master interrupt controller
99 // register bit numbers
100 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
101 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
102 int machine_id; // For NVRAM
103 uint32_t iommu_version;
104 uint32_t intbit_to_level[32];
105 uint64_t max_mem;
106 const char * const default_cpu_model;
107 };
108
109 #define MAX_IOUNITS 5
110
111 struct sun4d_hwdef {
112 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
113 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
114 target_phys_addr_t serial_base;
115 target_phys_addr_t espdma_base, esp_base;
116 target_phys_addr_t ledma_base, le_base;
117 target_phys_addr_t tcx_base;
118 target_phys_addr_t sbi_base;
119 unsigned long vram_size, nvram_size;
120 // IRQ numbers are not PIL ones, but SBI register bit numbers
121 int esp_irq, le_irq, clock_irq, clock1_irq;
122 int ser_irq, ms_kb_irq, me_irq;
123 int machine_id; // For NVRAM
124 uint32_t iounit_version;
125 uint64_t max_mem;
126 const char * const default_cpu_model;
127 };
128
129 int DMA_get_channel_mode (int nchan)
130 {
131 return 0;
132 }
133 int DMA_read_memory (int nchan, void *buf, int pos, int size)
134 {
135 return 0;
136 }
137 int DMA_write_memory (int nchan, void *buf, int pos, int size)
138 {
139 return 0;
140 }
141 void DMA_hold_DREQ (int nchan) {}
142 void DMA_release_DREQ (int nchan) {}
143 void DMA_schedule(int nchan) {}
144 void DMA_run (void) {}
145 void DMA_init (int high_page_enable) {}
146 void DMA_register_channel (int nchan,
147 DMA_transfer_handler transfer_handler,
148 void *opaque)
149 {
150 }
151
152 static int nvram_boot_set(void *opaque, const char *boot_device)
153 {
154 unsigned int i;
155 uint8_t image[sizeof(ohwcfg_v3_t)];
156 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
157 m48t59_t *nvram = (m48t59_t *)opaque;
158
159 for (i = 0; i < sizeof(image); i++)
160 image[i] = m48t59_read(nvram, i) & 0xff;
161
162 strcpy((char *)header->boot_devices, boot_device);
163 header->nboot_devices = strlen(boot_device) & 0xff;
164 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
165
166 for (i = 0; i < sizeof(image); i++)
167 m48t59_write(nvram, i, image[i]);
168
169 return 0;
170 }
171
172 extern int nographic;
173
174 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
175 const char *boot_devices, ram_addr_t RAM_size,
176 uint32_t kernel_size,
177 int width, int height, int depth,
178 int machine_id, const char *arch)
179 {
180 unsigned int i;
181 uint32_t start, end;
182 uint8_t image[0x1ff0];
183 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
184 struct sparc_arch_cfg *sparc_header;
185 struct OpenBIOS_nvpart_v1 *part_header;
186
187 memset(image, '\0', sizeof(image));
188
189 // Try to match PPC NVRAM
190 strcpy((char *)header->struct_ident, "QEMU_BIOS");
191 header->struct_version = cpu_to_be32(3); /* structure v3 */
192
193 header->nvram_size = cpu_to_be16(0x2000);
194 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
195 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
196 strcpy((char *)header->arch, arch);
197 header->nb_cpus = smp_cpus & 0xff;
198 header->RAM0_base = 0;
199 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
200 strcpy((char *)header->boot_devices, boot_devices);
201 header->nboot_devices = strlen(boot_devices) & 0xff;
202 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
203 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
204 if (cmdline) {
205 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
206 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
207 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
208 }
209 // XXX add initrd_image, initrd_size
210 header->width = cpu_to_be16(width);
211 header->height = cpu_to_be16(height);
212 header->depth = cpu_to_be16(depth);
213 if (nographic)
214 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
215
216 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
217
218 // Architecture specific header
219 start = sizeof(ohwcfg_v3_t);
220 sparc_header = (struct sparc_arch_cfg *)&image[start];
221 sparc_header->valid = 0;
222 start += sizeof(struct sparc_arch_cfg);
223
224 // OpenBIOS nvram variables
225 // Variable partition
226 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
227 part_header->signature = OPENBIOS_PART_SYSTEM;
228 strcpy(part_header->name, "system");
229
230 end = start + sizeof(struct OpenBIOS_nvpart_v1);
231 for (i = 0; i < nb_prom_envs; i++)
232 end = OpenBIOS_set_var(image, end, prom_envs[i]);
233
234 // End marker
235 image[end++] = '\0';
236
237 end = start + ((end - start + 15) & ~15);
238 OpenBIOS_finish_partition(part_header, end - start);
239
240 // free partition
241 start = end;
242 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
243 part_header->signature = OPENBIOS_PART_FREE;
244 strcpy(part_header->name, "free");
245
246 end = 0x1fd0;
247 OpenBIOS_finish_partition(part_header, end - start);
248
249 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
250
251 for (i = 0; i < sizeof(image); i++)
252 m48t59_write(nvram, i, image[i]);
253
254 qemu_register_boot_set(nvram_boot_set, nvram);
255 }
256
257 static void *slavio_intctl;
258
259 void pic_info(void)
260 {
261 if (slavio_intctl)
262 slavio_pic_info(slavio_intctl);
263 }
264
265 void irq_info(void)
266 {
267 if (slavio_intctl)
268 slavio_irq_info(slavio_intctl);
269 }
270
271 void cpu_check_irqs(CPUState *env)
272 {
273 if (env->pil_in && (env->interrupt_index == 0 ||
274 (env->interrupt_index & ~15) == TT_EXTINT)) {
275 unsigned int i;
276
277 for (i = 15; i > 0; i--) {
278 if (env->pil_in & (1 << i)) {
279 int old_interrupt = env->interrupt_index;
280
281 env->interrupt_index = TT_EXTINT | i;
282 if (old_interrupt != env->interrupt_index) {
283 DPRINTF("Set CPU IRQ %d\n", i);
284 cpu_interrupt(env, CPU_INTERRUPT_HARD);
285 }
286 break;
287 }
288 }
289 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
290 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
291 env->interrupt_index = 0;
292 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
293 }
294 }
295
296 static void cpu_set_irq(void *opaque, int irq, int level)
297 {
298 CPUState *env = opaque;
299
300 if (level) {
301 DPRINTF("Raise CPU IRQ %d\n", irq);
302 env->halted = 0;
303 env->pil_in |= 1 << irq;
304 cpu_check_irqs(env);
305 } else {
306 DPRINTF("Lower CPU IRQ %d\n", irq);
307 env->pil_in &= ~(1 << irq);
308 cpu_check_irqs(env);
309 }
310 }
311
312 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
313 {
314 }
315
316 static void *slavio_misc;
317
318 void qemu_system_powerdown(void)
319 {
320 slavio_set_power_fail(slavio_misc, 1);
321 }
322
323 static void main_cpu_reset(void *opaque)
324 {
325 CPUState *env = opaque;
326
327 cpu_reset(env);
328 env->halted = 0;
329 }
330
331 static void secondary_cpu_reset(void *opaque)
332 {
333 CPUState *env = opaque;
334
335 cpu_reset(env);
336 env->halted = 1;
337 }
338
339 static unsigned long sun4m_load_kernel(const char *kernel_filename,
340 const char *initrd_filename,
341 ram_addr_t RAM_size)
342 {
343 int linux_boot;
344 unsigned int i;
345 long initrd_size, kernel_size;
346
347 linux_boot = (kernel_filename != NULL);
348
349 kernel_size = 0;
350 if (linux_boot) {
351 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
352 NULL);
353 if (kernel_size < 0)
354 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
355 RAM_size - KERNEL_LOAD_ADDR);
356 if (kernel_size < 0)
357 kernel_size = load_image_targphys(kernel_filename,
358 KERNEL_LOAD_ADDR,
359 RAM_size - KERNEL_LOAD_ADDR);
360 if (kernel_size < 0) {
361 fprintf(stderr, "qemu: could not load kernel '%s'\n",
362 kernel_filename);
363 exit(1);
364 }
365
366 /* load initrd */
367 initrd_size = 0;
368 if (initrd_filename) {
369 initrd_size = load_image_targphys(initrd_filename,
370 INITRD_LOAD_ADDR,
371 RAM_size - INITRD_LOAD_ADDR);
372 if (initrd_size < 0) {
373 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
374 initrd_filename);
375 exit(1);
376 }
377 }
378 if (initrd_size > 0) {
379 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
380 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
381 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
382 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
383 break;
384 }
385 }
386 }
387 }
388 return kernel_size;
389 }
390
391 static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
392 const char *boot_device,
393 DisplayState *ds, const char *kernel_filename,
394 const char *kernel_cmdline,
395 const char *initrd_filename, const char *cpu_model)
396
397 {
398 CPUState *env, *envs[MAX_CPUS];
399 unsigned int i;
400 void *iommu, *espdma, *ledma, *main_esp, *nvram;
401 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
402 *espdma_irq, *ledma_irq;
403 qemu_irq *esp_reset, *le_reset;
404 qemu_irq *fdc_tc;
405 unsigned long prom_offset, kernel_size;
406 int ret;
407 char buf[1024];
408 BlockDriverState *fd[MAX_FD];
409 int drive_index;
410
411 /* init CPUs */
412 if (!cpu_model)
413 cpu_model = hwdef->default_cpu_model;
414
415 for(i = 0; i < smp_cpus; i++) {
416 env = cpu_init(cpu_model);
417 if (!env) {
418 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
419 exit(1);
420 }
421 cpu_sparc_set_id(env, i);
422 envs[i] = env;
423 if (i == 0) {
424 qemu_register_reset(main_cpu_reset, env);
425 } else {
426 qemu_register_reset(secondary_cpu_reset, env);
427 env->halted = 1;
428 }
429 register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
430 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
431 env->prom_addr = hwdef->slavio_base;
432 }
433
434 for (i = smp_cpus; i < MAX_CPUS; i++)
435 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
436
437
438 /* allocate RAM */
439 if ((uint64_t)RAM_size > hwdef->max_mem) {
440 fprintf(stderr,
441 "qemu: Too much memory for this machine: %d, maximum %d\n",
442 (unsigned int)(RAM_size / (1024 * 1024)),
443 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
444 exit(1);
445 }
446 cpu_register_physical_memory(0, RAM_size, 0);
447
448 /* load boot prom */
449 prom_offset = RAM_size + hwdef->vram_size;
450 cpu_register_physical_memory(hwdef->slavio_base,
451 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
452 TARGET_PAGE_MASK,
453 prom_offset | IO_MEM_ROM);
454
455 if (bios_name == NULL)
456 bios_name = PROM_FILENAME;
457 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
458 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
459 if (ret < 0 || ret > PROM_SIZE_MAX)
460 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
461 if (ret < 0 || ret > PROM_SIZE_MAX) {
462 fprintf(stderr, "qemu: could not load prom '%s'\n",
463 buf);
464 exit(1);
465 }
466 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
467
468 /* set up devices */
469 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
470 hwdef->intctl_base + 0x10000ULL,
471 &hwdef->intbit_to_level[0],
472 &slavio_irq, &slavio_cpu_irq,
473 cpu_irqs,
474 hwdef->clock_irq);
475
476 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
477 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
478
479 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
480 prom_offset | IO_MEM_ROM);
481 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
482 sizeof(idreg_data));
483 }
484
485 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
486 slavio_irq[hwdef->me_irq]);
487
488 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
489 iommu, &espdma_irq, &esp_reset);
490
491 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
492 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
493 &le_reset);
494
495 if (graphic_depth != 8 && graphic_depth != 24) {
496 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
497 exit (1);
498 }
499 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
500 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
501
502 if (nd_table[0].model == NULL
503 || strcmp(nd_table[0].model, "lance") == 0) {
504 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
505 } else if (strcmp(nd_table[0].model, "?") == 0) {
506 fprintf(stderr, "qemu: Supported NICs: lance\n");
507 exit (1);
508 } else {
509 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
510 exit (1);
511 }
512
513 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
514 hwdef->nvram_size, 8);
515
516 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
517 slavio_cpu_irq, smp_cpus);
518
519 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
520 nographic);
521 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
522 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
523 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
524 serial_hds[1], serial_hds[0]);
525
526 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
527 hwdef->aux1_base, hwdef->aux2_base,
528 slavio_irq[hwdef->me_irq], envs[0],
529 &fdc_tc);
530
531 if (hwdef->fd_base != (target_phys_addr_t)-1) {
532 /* there is zero or one floppy drive */
533 memset(fd, 0, sizeof(fd));
534 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
535 if (drive_index != -1)
536 fd[0] = drives_table[drive_index].bdrv;
537
538 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
539 fdc_tc);
540 }
541
542 if (drive_get_max_bus(IF_SCSI) > 0) {
543 fprintf(stderr, "qemu: too many SCSI bus\n");
544 exit(1);
545 }
546
547 main_esp = esp_init(hwdef->esp_base, 2,
548 espdma_memory_read, espdma_memory_write,
549 espdma, *espdma_irq, esp_reset);
550
551 for (i = 0; i < ESP_MAX_DEVS; i++) {
552 drive_index = drive_get_index(IF_SCSI, 0, i);
553 if (drive_index == -1)
554 continue;
555 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
556 }
557
558 if (hwdef->cs_base != (target_phys_addr_t)-1)
559 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
560
561 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
562 RAM_size);
563
564 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
565 boot_device, RAM_size, kernel_size, graphic_width,
566 graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
567
568 if (hwdef->ecc_base != (target_phys_addr_t)-1)
569 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
570 hwdef->ecc_version);
571 }
572
573 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
574 const char *boot_device,
575 DisplayState *ds, const char *kernel_filename,
576 const char *kernel_cmdline,
577 const char *initrd_filename, const char *cpu_model)
578 {
579 CPUState *env;
580 unsigned int i;
581 void *iommu, *espdma, *ledma, *main_esp, *nvram;
582 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
583 qemu_irq *esp_reset, *le_reset;
584 qemu_irq *fdc_tc;
585 unsigned long prom_offset, kernel_size;
586 int ret;
587 char buf[1024];
588 BlockDriverState *fd[MAX_FD];
589 int drive_index;
590
591 /* init CPU */
592 if (!cpu_model)
593 cpu_model = hwdef->default_cpu_model;
594
595 env = cpu_init(cpu_model);
596 if (!env) {
597 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
598 exit(1);
599 }
600
601 cpu_sparc_set_id(env, 0);
602
603 qemu_register_reset(main_cpu_reset, env);
604 register_savevm("cpu", 0, 4, cpu_save, cpu_load, env);
605 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
606 env->prom_addr = hwdef->slavio_base;
607
608 /* allocate RAM */
609 if ((uint64_t)RAM_size > hwdef->max_mem) {
610 fprintf(stderr,
611 "qemu: Too much memory for this machine: %d, maximum %d\n",
612 (unsigned int)(RAM_size / (1024 * 1024)),
613 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
614 exit(1);
615 }
616 cpu_register_physical_memory(0, RAM_size, 0);
617
618 /* load boot prom */
619 prom_offset = RAM_size + hwdef->vram_size;
620 cpu_register_physical_memory(hwdef->slavio_base,
621 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
622 TARGET_PAGE_MASK,
623 prom_offset | IO_MEM_ROM);
624
625 if (bios_name == NULL)
626 bios_name = PROM_FILENAME;
627 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
628 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
629 if (ret < 0 || ret > PROM_SIZE_MAX)
630 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
631 if (ret < 0 || ret > PROM_SIZE_MAX) {
632 fprintf(stderr, "qemu: could not load prom '%s'\n",
633 buf);
634 exit(1);
635 }
636 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
637
638 /* set up devices */
639 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
640 &slavio_irq, cpu_irqs);
641
642 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
643 slavio_irq[hwdef->me_irq]);
644
645 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
646 iommu, &espdma_irq, &esp_reset);
647
648 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
649 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
650 &le_reset);
651
652 if (graphic_depth != 8 && graphic_depth != 24) {
653 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
654 exit (1);
655 }
656 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
657 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
658
659 if (nd_table[0].model == NULL
660 || strcmp(nd_table[0].model, "lance") == 0) {
661 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
662 } else if (strcmp(nd_table[0].model, "?") == 0) {
663 fprintf(stderr, "qemu: Supported NICs: lance\n");
664 exit (1);
665 } else {
666 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
667 exit (1);
668 }
669
670 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
671 hwdef->nvram_size, 2);
672
673 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
674 nographic);
675 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
676 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
677 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
678 serial_hds[1], serial_hds[0]);
679
680 slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
681 hwdef->aux1_base, hwdef->aux2_base,
682 slavio_irq[hwdef->me_irq], env, &fdc_tc);
683
684 if (hwdef->fd_base != (target_phys_addr_t)-1) {
685 /* there is zero or one floppy drive */
686 fd[1] = fd[0] = NULL;
687 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
688 if (drive_index != -1)
689 fd[0] = drives_table[drive_index].bdrv;
690
691 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
692 fdc_tc);
693 }
694
695 if (drive_get_max_bus(IF_SCSI) > 0) {
696 fprintf(stderr, "qemu: too many SCSI bus\n");
697 exit(1);
698 }
699
700 main_esp = esp_init(hwdef->esp_base, 2,
701 espdma_memory_read, espdma_memory_write,
702 espdma, *espdma_irq, esp_reset);
703
704 for (i = 0; i < ESP_MAX_DEVS; i++) {
705 drive_index = drive_get_index(IF_SCSI, 0, i);
706 if (drive_index == -1)
707 continue;
708 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
709 }
710
711 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
712 RAM_size);
713
714 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
715 boot_device, RAM_size, kernel_size, graphic_width,
716 graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
717 }
718
719 static const struct hwdef hwdefs[] = {
720 /* SS-5 */
721 {
722 .iommu_base = 0x10000000,
723 .tcx_base = 0x50000000,
724 .cs_base = 0x6c000000,
725 .slavio_base = 0x70000000,
726 .ms_kb_base = 0x71000000,
727 .serial_base = 0x71100000,
728 .nvram_base = 0x71200000,
729 .fd_base = 0x71400000,
730 .counter_base = 0x71d00000,
731 .intctl_base = 0x71e00000,
732 .idreg_base = 0x78000000,
733 .dma_base = 0x78400000,
734 .esp_base = 0x78800000,
735 .le_base = 0x78c00000,
736 .apc_base = 0x6a000000,
737 .aux1_base = 0x71900000,
738 .aux2_base = 0x71910000,
739 .ecc_base = -1,
740 .sun4c_intctl_base = -1,
741 .sun4c_counter_base = -1,
742 .vram_size = 0x00100000,
743 .nvram_size = 0x2000,
744 .esp_irq = 18,
745 .le_irq = 16,
746 .clock_irq = 7,
747 .clock1_irq = 19,
748 .ms_kb_irq = 14,
749 .ser_irq = 15,
750 .fd_irq = 22,
751 .me_irq = 30,
752 .cs_irq = 5,
753 .machine_id = 0x80,
754 .iommu_version = 0x05000000,
755 .intbit_to_level = {
756 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
757 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
758 },
759 .max_mem = 0x10000000,
760 .default_cpu_model = "Fujitsu MB86904",
761 },
762 /* SS-10 */
763 {
764 .iommu_base = 0xfe0000000ULL,
765 .tcx_base = 0xe20000000ULL,
766 .cs_base = -1,
767 .slavio_base = 0xff0000000ULL,
768 .ms_kb_base = 0xff1000000ULL,
769 .serial_base = 0xff1100000ULL,
770 .nvram_base = 0xff1200000ULL,
771 .fd_base = 0xff1700000ULL,
772 .counter_base = 0xff1300000ULL,
773 .intctl_base = 0xff1400000ULL,
774 .idreg_base = 0xef0000000ULL,
775 .dma_base = 0xef0400000ULL,
776 .esp_base = 0xef0800000ULL,
777 .le_base = 0xef0c00000ULL,
778 .apc_base = 0xefa000000ULL, // XXX should not exist
779 .aux1_base = 0xff1800000ULL,
780 .aux2_base = 0xff1a01000ULL,
781 .ecc_base = 0xf00000000ULL,
782 .ecc_version = 0x10000000, // version 0, implementation 1
783 .sun4c_intctl_base = -1,
784 .sun4c_counter_base = -1,
785 .vram_size = 0x00100000,
786 .nvram_size = 0x2000,
787 .esp_irq = 18,
788 .le_irq = 16,
789 .clock_irq = 7,
790 .clock1_irq = 19,
791 .ms_kb_irq = 14,
792 .ser_irq = 15,
793 .fd_irq = 22,
794 .me_irq = 30,
795 .cs_irq = -1,
796 .ecc_irq = 28,
797 .machine_id = 0x72,
798 .iommu_version = 0x03000000,
799 .intbit_to_level = {
800 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
801 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
802 },
803 .max_mem = 0xf00000000ULL,
804 .default_cpu_model = "TI SuperSparc II",
805 },
806 /* SS-600MP */
807 {
808 .iommu_base = 0xfe0000000ULL,
809 .tcx_base = 0xe20000000ULL,
810 .cs_base = -1,
811 .slavio_base = 0xff0000000ULL,
812 .ms_kb_base = 0xff1000000ULL,
813 .serial_base = 0xff1100000ULL,
814 .nvram_base = 0xff1200000ULL,
815 .fd_base = -1,
816 .counter_base = 0xff1300000ULL,
817 .intctl_base = 0xff1400000ULL,
818 .idreg_base = -1,
819 .dma_base = 0xef0081000ULL,
820 .esp_base = 0xef0080000ULL,
821 .le_base = 0xef0060000ULL,
822 .apc_base = 0xefa000000ULL, // XXX should not exist
823 .aux1_base = 0xff1800000ULL,
824 .aux2_base = 0xff1a01000ULL, // XXX should not exist
825 .ecc_base = 0xf00000000ULL,
826 .ecc_version = 0x00000000, // version 0, implementation 0
827 .sun4c_intctl_base = -1,
828 .sun4c_counter_base = -1,
829 .vram_size = 0x00100000,
830 .nvram_size = 0x2000,
831 .esp_irq = 18,
832 .le_irq = 16,
833 .clock_irq = 7,
834 .clock1_irq = 19,
835 .ms_kb_irq = 14,
836 .ser_irq = 15,
837 .fd_irq = 22,
838 .me_irq = 30,
839 .cs_irq = -1,
840 .ecc_irq = 28,
841 .machine_id = 0x71,
842 .iommu_version = 0x01000000,
843 .intbit_to_level = {
844 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
845 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
846 },
847 .max_mem = 0xf00000000ULL,
848 .default_cpu_model = "TI SuperSparc II",
849 },
850 /* SS-20 */
851 {
852 .iommu_base = 0xfe0000000ULL,
853 .tcx_base = 0xe20000000ULL,
854 .cs_base = -1,
855 .slavio_base = 0xff0000000ULL,
856 .ms_kb_base = 0xff1000000ULL,
857 .serial_base = 0xff1100000ULL,
858 .nvram_base = 0xff1200000ULL,
859 .fd_base = 0xff1700000ULL,
860 .counter_base = 0xff1300000ULL,
861 .intctl_base = 0xff1400000ULL,
862 .idreg_base = 0xef0000000ULL,
863 .dma_base = 0xef0400000ULL,
864 .esp_base = 0xef0800000ULL,
865 .le_base = 0xef0c00000ULL,
866 .apc_base = 0xefa000000ULL, // XXX should not exist
867 .aux1_base = 0xff1800000ULL,
868 .aux2_base = 0xff1a01000ULL,
869 .ecc_base = 0xf00000000ULL,
870 .ecc_version = 0x20000000, // version 0, implementation 2
871 .sun4c_intctl_base = -1,
872 .sun4c_counter_base = -1,
873 .vram_size = 0x00100000,
874 .nvram_size = 0x2000,
875 .esp_irq = 18,
876 .le_irq = 16,
877 .clock_irq = 7,
878 .clock1_irq = 19,
879 .ms_kb_irq = 14,
880 .ser_irq = 15,
881 .fd_irq = 22,
882 .me_irq = 30,
883 .cs_irq = -1,
884 .ecc_irq = 28,
885 .machine_id = 0x72,
886 .iommu_version = 0x13000000,
887 .intbit_to_level = {
888 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
889 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
890 },
891 .max_mem = 0xf00000000ULL,
892 .default_cpu_model = "TI SuperSparc II",
893 },
894 /* SS-2 */
895 {
896 .iommu_base = 0xf8000000,
897 .tcx_base = 0xfe000000,
898 .cs_base = -1,
899 .slavio_base = 0xf6000000,
900 .ms_kb_base = 0xf0000000,
901 .serial_base = 0xf1000000,
902 .nvram_base = 0xf2000000,
903 .fd_base = 0xf7200000,
904 .counter_base = -1,
905 .intctl_base = -1,
906 .dma_base = 0xf8400000,
907 .esp_base = 0xf8800000,
908 .le_base = 0xf8c00000,
909 .apc_base = -1,
910 .aux1_base = 0xf7400003,
911 .aux2_base = -1,
912 .sun4c_intctl_base = 0xf5000000,
913 .sun4c_counter_base = 0xf3000000,
914 .vram_size = 0x00100000,
915 .nvram_size = 0x800,
916 .esp_irq = 2,
917 .le_irq = 3,
918 .clock_irq = 5,
919 .clock1_irq = 7,
920 .ms_kb_irq = 1,
921 .ser_irq = 1,
922 .fd_irq = 1,
923 .me_irq = 1,
924 .cs_irq = -1,
925 .machine_id = 0x55,
926 .max_mem = 0x10000000,
927 .default_cpu_model = "Cypress CY7C601",
928 },
929 /* Voyager */
930 {
931 .iommu_base = 0x10000000,
932 .tcx_base = 0x50000000,
933 .cs_base = -1,
934 .slavio_base = 0x70000000,
935 .ms_kb_base = 0x71000000,
936 .serial_base = 0x71100000,
937 .nvram_base = 0x71200000,
938 .fd_base = 0x71400000,
939 .counter_base = 0x71d00000,
940 .intctl_base = 0x71e00000,
941 .idreg_base = 0x78000000,
942 .dma_base = 0x78400000,
943 .esp_base = 0x78800000,
944 .le_base = 0x78c00000,
945 .apc_base = 0x71300000, // pmc
946 .aux1_base = 0x71900000,
947 .aux2_base = 0x71910000,
948 .ecc_base = -1,
949 .sun4c_intctl_base = -1,
950 .sun4c_counter_base = -1,
951 .vram_size = 0x00100000,
952 .nvram_size = 0x2000,
953 .esp_irq = 18,
954 .le_irq = 16,
955 .clock_irq = 7,
956 .clock1_irq = 19,
957 .ms_kb_irq = 14,
958 .ser_irq = 15,
959 .fd_irq = 22,
960 .me_irq = 30,
961 .cs_irq = -1,
962 .machine_id = 0x80,
963 .iommu_version = 0x05000000,
964 .intbit_to_level = {
965 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
966 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
967 },
968 .max_mem = 0x10000000,
969 .default_cpu_model = "Fujitsu MB86904",
970 },
971 /* LX */
972 {
973 .iommu_base = 0x10000000,
974 .tcx_base = 0x50000000,
975 .cs_base = -1,
976 .slavio_base = 0x70000000,
977 .ms_kb_base = 0x71000000,
978 .serial_base = 0x71100000,
979 .nvram_base = 0x71200000,
980 .fd_base = 0x71400000,
981 .counter_base = 0x71d00000,
982 .intctl_base = 0x71e00000,
983 .idreg_base = 0x78000000,
984 .dma_base = 0x78400000,
985 .esp_base = 0x78800000,
986 .le_base = 0x78c00000,
987 .apc_base = -1,
988 .aux1_base = 0x71900000,
989 .aux2_base = 0x71910000,
990 .ecc_base = -1,
991 .sun4c_intctl_base = -1,
992 .sun4c_counter_base = -1,
993 .vram_size = 0x00100000,
994 .nvram_size = 0x2000,
995 .esp_irq = 18,
996 .le_irq = 16,
997 .clock_irq = 7,
998 .clock1_irq = 19,
999 .ms_kb_irq = 14,
1000 .ser_irq = 15,
1001 .fd_irq = 22,
1002 .me_irq = 30,
1003 .cs_irq = -1,
1004 .machine_id = 0x80,
1005 .iommu_version = 0x04000000,
1006 .intbit_to_level = {
1007 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1008 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1009 },
1010 .max_mem = 0x10000000,
1011 .default_cpu_model = "TI MicroSparc I",
1012 },
1013 /* SS-4 */
1014 {
1015 .iommu_base = 0x10000000,
1016 .tcx_base = 0x50000000,
1017 .cs_base = 0x6c000000,
1018 .slavio_base = 0x70000000,
1019 .ms_kb_base = 0x71000000,
1020 .serial_base = 0x71100000,
1021 .nvram_base = 0x71200000,
1022 .fd_base = 0x71400000,
1023 .counter_base = 0x71d00000,
1024 .intctl_base = 0x71e00000,
1025 .idreg_base = 0x78000000,
1026 .dma_base = 0x78400000,
1027 .esp_base = 0x78800000,
1028 .le_base = 0x78c00000,
1029 .apc_base = 0x6a000000,
1030 .aux1_base = 0x71900000,
1031 .aux2_base = 0x71910000,
1032 .ecc_base = -1,
1033 .sun4c_intctl_base = -1,
1034 .sun4c_counter_base = -1,
1035 .vram_size = 0x00100000,
1036 .nvram_size = 0x2000,
1037 .esp_irq = 18,
1038 .le_irq = 16,
1039 .clock_irq = 7,
1040 .clock1_irq = 19,
1041 .ms_kb_irq = 14,
1042 .ser_irq = 15,
1043 .fd_irq = 22,
1044 .me_irq = 30,
1045 .cs_irq = 5,
1046 .machine_id = 0x80,
1047 .iommu_version = 0x05000000,
1048 .intbit_to_level = {
1049 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1050 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1051 },
1052 .max_mem = 0x10000000,
1053 .default_cpu_model = "Fujitsu MB86904",
1054 },
1055 /* SPARCClassic */
1056 {
1057 .iommu_base = 0x10000000,
1058 .tcx_base = 0x50000000,
1059 .cs_base = -1,
1060 .slavio_base = 0x70000000,
1061 .ms_kb_base = 0x71000000,
1062 .serial_base = 0x71100000,
1063 .nvram_base = 0x71200000,
1064 .fd_base = 0x71400000,
1065 .counter_base = 0x71d00000,
1066 .intctl_base = 0x71e00000,
1067 .idreg_base = 0x78000000,
1068 .dma_base = 0x78400000,
1069 .esp_base = 0x78800000,
1070 .le_base = 0x78c00000,
1071 .apc_base = 0x6a000000,
1072 .aux1_base = 0x71900000,
1073 .aux2_base = 0x71910000,
1074 .ecc_base = -1,
1075 .sun4c_intctl_base = -1,
1076 .sun4c_counter_base = -1,
1077 .vram_size = 0x00100000,
1078 .nvram_size = 0x2000,
1079 .esp_irq = 18,
1080 .le_irq = 16,
1081 .clock_irq = 7,
1082 .clock1_irq = 19,
1083 .ms_kb_irq = 14,
1084 .ser_irq = 15,
1085 .fd_irq = 22,
1086 .me_irq = 30,
1087 .cs_irq = -1,
1088 .machine_id = 0x80,
1089 .iommu_version = 0x05000000,
1090 .intbit_to_level = {
1091 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1092 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1093 },
1094 .max_mem = 0x10000000,
1095 .default_cpu_model = "TI MicroSparc I",
1096 },
1097 /* SPARCbook */
1098 {
1099 .iommu_base = 0x10000000,
1100 .tcx_base = 0x50000000, // XXX
1101 .cs_base = -1,
1102 .slavio_base = 0x70000000,
1103 .ms_kb_base = 0x71000000,
1104 .serial_base = 0x71100000,
1105 .nvram_base = 0x71200000,
1106 .fd_base = 0x71400000,
1107 .counter_base = 0x71d00000,
1108 .intctl_base = 0x71e00000,
1109 .idreg_base = 0x78000000,
1110 .dma_base = 0x78400000,
1111 .esp_base = 0x78800000,
1112 .le_base = 0x78c00000,
1113 .apc_base = 0x6a000000,
1114 .aux1_base = 0x71900000,
1115 .aux2_base = 0x71910000,
1116 .ecc_base = -1,
1117 .sun4c_intctl_base = -1,
1118 .sun4c_counter_base = -1,
1119 .vram_size = 0x00100000,
1120 .nvram_size = 0x2000,
1121 .esp_irq = 18,
1122 .le_irq = 16,
1123 .clock_irq = 7,
1124 .clock1_irq = 19,
1125 .ms_kb_irq = 14,
1126 .ser_irq = 15,
1127 .fd_irq = 22,
1128 .me_irq = 30,
1129 .cs_irq = -1,
1130 .machine_id = 0x80,
1131 .iommu_version = 0x05000000,
1132 .intbit_to_level = {
1133 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1134 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1135 },
1136 .max_mem = 0x10000000,
1137 .default_cpu_model = "TI MicroSparc I",
1138 },
1139 };
1140
1141 /* SPARCstation 5 hardware initialisation */
1142 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1143 const char *boot_device, DisplayState *ds,
1144 const char *kernel_filename, const char *kernel_cmdline,
1145 const char *initrd_filename, const char *cpu_model)
1146 {
1147 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1148 kernel_cmdline, initrd_filename, cpu_model);
1149 }
1150
1151 /* SPARCstation 10 hardware initialisation */
1152 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1153 const char *boot_device, DisplayState *ds,
1154 const char *kernel_filename, const char *kernel_cmdline,
1155 const char *initrd_filename, const char *cpu_model)
1156 {
1157 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1158 kernel_cmdline, initrd_filename, cpu_model);
1159 }
1160
1161 /* SPARCserver 600MP hardware initialisation */
1162 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1163 const char *boot_device, DisplayState *ds,
1164 const char *kernel_filename,
1165 const char *kernel_cmdline,
1166 const char *initrd_filename, const char *cpu_model)
1167 {
1168 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1169 kernel_cmdline, initrd_filename, cpu_model);
1170 }
1171
1172 /* SPARCstation 20 hardware initialisation */
1173 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1174 const char *boot_device, DisplayState *ds,
1175 const char *kernel_filename, const char *kernel_cmdline,
1176 const char *initrd_filename, const char *cpu_model)
1177 {
1178 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1179 kernel_cmdline, initrd_filename, cpu_model);
1180 }
1181
1182 /* SPARCstation 2 hardware initialisation */
1183 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1184 const char *boot_device, DisplayState *ds,
1185 const char *kernel_filename, const char *kernel_cmdline,
1186 const char *initrd_filename, const char *cpu_model)
1187 {
1188 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1189 kernel_cmdline, initrd_filename, cpu_model);
1190 }
1191
1192 /* SPARCstation Voyager hardware initialisation */
1193 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1194 const char *boot_device, DisplayState *ds,
1195 const char *kernel_filename, const char *kernel_cmdline,
1196 const char *initrd_filename, const char *cpu_model)
1197 {
1198 sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1199 kernel_cmdline, initrd_filename, cpu_model);
1200 }
1201
1202 /* SPARCstation LX hardware initialisation */
1203 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1204 const char *boot_device, DisplayState *ds,
1205 const char *kernel_filename, const char *kernel_cmdline,
1206 const char *initrd_filename, const char *cpu_model)
1207 {
1208 sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1209 kernel_cmdline, initrd_filename, cpu_model);
1210 }
1211
1212 /* SPARCstation 4 hardware initialisation */
1213 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1214 const char *boot_device, DisplayState *ds,
1215 const char *kernel_filename, const char *kernel_cmdline,
1216 const char *initrd_filename, const char *cpu_model)
1217 {
1218 sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1219 kernel_cmdline, initrd_filename, cpu_model);
1220 }
1221
1222 /* SPARCClassic hardware initialisation */
1223 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1224 const char *boot_device, DisplayState *ds,
1225 const char *kernel_filename, const char *kernel_cmdline,
1226 const char *initrd_filename, const char *cpu_model)
1227 {
1228 sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1229 kernel_cmdline, initrd_filename, cpu_model);
1230 }
1231
1232 /* SPARCbook hardware initialisation */
1233 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1234 const char *boot_device, DisplayState *ds,
1235 const char *kernel_filename, const char *kernel_cmdline,
1236 const char *initrd_filename, const char *cpu_model)
1237 {
1238 sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
1239 kernel_cmdline, initrd_filename, cpu_model);
1240 }
1241
1242 QEMUMachine ss5_machine = {
1243 "SS-5",
1244 "Sun4m platform, SPARCstation 5",
1245 ss5_init,
1246 PROM_SIZE_MAX + TCX_SIZE,
1247 };
1248
1249 QEMUMachine ss10_machine = {
1250 "SS-10",
1251 "Sun4m platform, SPARCstation 10",
1252 ss10_init,
1253 PROM_SIZE_MAX + TCX_SIZE,
1254 };
1255
1256 QEMUMachine ss600mp_machine = {
1257 "SS-600MP",
1258 "Sun4m platform, SPARCserver 600MP",
1259 ss600mp_init,
1260 PROM_SIZE_MAX + TCX_SIZE,
1261 };
1262
1263 QEMUMachine ss20_machine = {
1264 "SS-20",
1265 "Sun4m platform, SPARCstation 20",
1266 ss20_init,
1267 PROM_SIZE_MAX + TCX_SIZE,
1268 };
1269
1270 QEMUMachine ss2_machine = {
1271 "SS-2",
1272 "Sun4c platform, SPARCstation 2",
1273 ss2_init,
1274 PROM_SIZE_MAX + TCX_SIZE,
1275 };
1276
1277 QEMUMachine voyager_machine = {
1278 "Voyager",
1279 "Sun4m platform, SPARCstation Voyager",
1280 vger_init,
1281 PROM_SIZE_MAX + TCX_SIZE,
1282 };
1283
1284 QEMUMachine ss_lx_machine = {
1285 "LX",
1286 "Sun4m platform, SPARCstation LX",
1287 ss_lx_init,
1288 PROM_SIZE_MAX + TCX_SIZE,
1289 };
1290
1291 QEMUMachine ss4_machine = {
1292 "SS-4",
1293 "Sun4m platform, SPARCstation 4",
1294 ss4_init,
1295 PROM_SIZE_MAX + TCX_SIZE,
1296 };
1297
1298 QEMUMachine scls_machine = {
1299 "SPARCClassic",
1300 "Sun4m platform, SPARCClassic",
1301 scls_init,
1302 PROM_SIZE_MAX + TCX_SIZE,
1303 };
1304
1305 QEMUMachine sbook_machine = {
1306 "SPARCbook",
1307 "Sun4m platform, SPARCbook",
1308 sbook_init,
1309 PROM_SIZE_MAX + TCX_SIZE,
1310 };
1311
1312 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1313 /* SS-1000 */
1314 {
1315 .iounit_bases = {
1316 0xfe0200000ULL,
1317 0xfe1200000ULL,
1318 0xfe2200000ULL,
1319 0xfe3200000ULL,
1320 -1,
1321 },
1322 .tcx_base = 0x820000000ULL,
1323 .slavio_base = 0xf00000000ULL,
1324 .ms_kb_base = 0xf00240000ULL,
1325 .serial_base = 0xf00200000ULL,
1326 .nvram_base = 0xf00280000ULL,
1327 .counter_base = 0xf00300000ULL,
1328 .espdma_base = 0x800081000ULL,
1329 .esp_base = 0x800080000ULL,
1330 .ledma_base = 0x800040000ULL,
1331 .le_base = 0x800060000ULL,
1332 .sbi_base = 0xf02800000ULL,
1333 .vram_size = 0x00100000,
1334 .nvram_size = 0x2000,
1335 .esp_irq = 3,
1336 .le_irq = 4,
1337 .clock_irq = 14,
1338 .clock1_irq = 10,
1339 .ms_kb_irq = 12,
1340 .ser_irq = 12,
1341 .machine_id = 0x80,
1342 .iounit_version = 0x03000000,
1343 .max_mem = 0xf00000000ULL,
1344 .default_cpu_model = "TI SuperSparc II",
1345 },
1346 /* SS-2000 */
1347 {
1348 .iounit_bases = {
1349 0xfe0200000ULL,
1350 0xfe1200000ULL,
1351 0xfe2200000ULL,
1352 0xfe3200000ULL,
1353 0xfe4200000ULL,
1354 },
1355 .tcx_base = 0x820000000ULL,
1356 .slavio_base = 0xf00000000ULL,
1357 .ms_kb_base = 0xf00240000ULL,
1358 .serial_base = 0xf00200000ULL,
1359 .nvram_base = 0xf00280000ULL,
1360 .counter_base = 0xf00300000ULL,
1361 .espdma_base = 0x800081000ULL,
1362 .esp_base = 0x800080000ULL,
1363 .ledma_base = 0x800040000ULL,
1364 .le_base = 0x800060000ULL,
1365 .sbi_base = 0xf02800000ULL,
1366 .vram_size = 0x00100000,
1367 .nvram_size = 0x2000,
1368 .esp_irq = 3,
1369 .le_irq = 4,
1370 .clock_irq = 14,
1371 .clock1_irq = 10,
1372 .ms_kb_irq = 12,
1373 .ser_irq = 12,
1374 .machine_id = 0x80,
1375 .iounit_version = 0x03000000,
1376 .max_mem = 0xf00000000ULL,
1377 .default_cpu_model = "TI SuperSparc II",
1378 },
1379 };
1380
1381 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1382 const char *boot_device,
1383 DisplayState *ds, const char *kernel_filename,
1384 const char *kernel_cmdline,
1385 const char *initrd_filename, const char *cpu_model)
1386 {
1387 CPUState *env, *envs[MAX_CPUS];
1388 unsigned int i;
1389 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1390 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1391 *espdma_irq, *ledma_irq;
1392 qemu_irq *esp_reset, *le_reset;
1393 unsigned long prom_offset, kernel_size;
1394 int ret;
1395 char buf[1024];
1396 int drive_index;
1397
1398 /* init CPUs */
1399 if (!cpu_model)
1400 cpu_model = hwdef->default_cpu_model;
1401
1402 for (i = 0; i < smp_cpus; i++) {
1403 env = cpu_init(cpu_model);
1404 if (!env) {
1405 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1406 exit(1);
1407 }
1408 cpu_sparc_set_id(env, i);
1409 envs[i] = env;
1410 if (i == 0) {
1411 qemu_register_reset(main_cpu_reset, env);
1412 } else {
1413 qemu_register_reset(secondary_cpu_reset, env);
1414 env->halted = 1;
1415 }
1416 register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
1417 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1418 env->prom_addr = hwdef->slavio_base;
1419 }
1420
1421 for (i = smp_cpus; i < MAX_CPUS; i++)
1422 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1423
1424 /* allocate RAM */
1425 if ((uint64_t)RAM_size > hwdef->max_mem) {
1426 fprintf(stderr,
1427 "qemu: Too much memory for this machine: %d, maximum %d\n",
1428 (unsigned int)(RAM_size / (1024 * 1024)),
1429 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1430 exit(1);
1431 }
1432 cpu_register_physical_memory(0, RAM_size, 0);
1433
1434 /* load boot prom */
1435 prom_offset = RAM_size + hwdef->vram_size;
1436 cpu_register_physical_memory(hwdef->slavio_base,
1437 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1438 TARGET_PAGE_MASK,
1439 prom_offset | IO_MEM_ROM);
1440
1441 if (bios_name == NULL)
1442 bios_name = PROM_FILENAME;
1443 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1444 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1445 if (ret < 0 || ret > PROM_SIZE_MAX)
1446 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1447 if (ret < 0 || ret > PROM_SIZE_MAX) {
1448 fprintf(stderr, "qemu: could not load prom '%s'\n",
1449 buf);
1450 exit(1);
1451 }
1452
1453 /* set up devices */
1454 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1455
1456 for (i = 0; i < MAX_IOUNITS; i++)
1457 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1458 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1459 hwdef->iounit_version,
1460 sbi_irq[hwdef->me_irq]);
1461
1462 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1463 iounits[0], &espdma_irq, &esp_reset);
1464
1465 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1466 iounits[0], &ledma_irq, &le_reset);
1467
1468 if (graphic_depth != 8 && graphic_depth != 24) {
1469 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1470 exit (1);
1471 }
1472 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1473 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1474
1475 if (nd_table[0].model == NULL
1476 || strcmp(nd_table[0].model, "lance") == 0) {
1477 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1478 } else if (strcmp(nd_table[0].model, "?") == 0) {
1479 fprintf(stderr, "qemu: Supported NICs: lance\n");
1480 exit (1);
1481 } else {
1482 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1483 exit (1);
1484 }
1485
1486 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1487 hwdef->nvram_size, 8);
1488
1489 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1490 sbi_cpu_irq, smp_cpus);
1491
1492 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1493 nographic);
1494 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1495 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1496 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1497 serial_hds[1], serial_hds[0]);
1498
1499 if (drive_get_max_bus(IF_SCSI) > 0) {
1500 fprintf(stderr, "qemu: too many SCSI bus\n");
1501 exit(1);
1502 }
1503
1504 main_esp = esp_init(hwdef->esp_base, 2,
1505 espdma_memory_read, espdma_memory_write,
1506 espdma, *espdma_irq, esp_reset);
1507
1508 for (i = 0; i < ESP_MAX_DEVS; i++) {
1509 drive_index = drive_get_index(IF_SCSI, 0, i);
1510 if (drive_index == -1)
1511 continue;
1512 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1513 }
1514
1515 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1516 RAM_size);
1517
1518 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1519 boot_device, RAM_size, kernel_size, graphic_width,
1520 graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
1521 }
1522
1523 /* SPARCserver 1000 hardware initialisation */
1524 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1525 const char *boot_device, DisplayState *ds,
1526 const char *kernel_filename, const char *kernel_cmdline,
1527 const char *initrd_filename, const char *cpu_model)
1528 {
1529 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1530 kernel_cmdline, initrd_filename, cpu_model);
1531 }
1532
1533 /* SPARCcenter 2000 hardware initialisation */
1534 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1535 const char *boot_device, DisplayState *ds,
1536 const char *kernel_filename, const char *kernel_cmdline,
1537 const char *initrd_filename, const char *cpu_model)
1538 {
1539 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1540 kernel_cmdline, initrd_filename, cpu_model);
1541 }
1542
1543 QEMUMachine ss1000_machine = {
1544 "SS-1000",
1545 "Sun4d platform, SPARCserver 1000",
1546 ss1000_init,
1547 PROM_SIZE_MAX + TCX_SIZE,
1548 };
1549
1550 QEMUMachine ss2000_machine = {
1551 "SS-2000",
1552 "Sun4d platform, SPARCcenter 2000",
1553 ss2000_init,
1554 PROM_SIZE_MAX + TCX_SIZE,
1555 };
jz4740 based target emulation