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Add vsldoi instruction.
[qemu/qemu-JZ.git] / target-ppc / translate.c
blob745da780df06a2551c510ed00fa9568f0e960d4b
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 /*****************************************************************************/
46 /* Code translation helpers */
47
48 /* global register indexes */
49 static TCGv_ptr cpu_env;
50 static char cpu_reg_names[10*3 + 22*4 /* GPR */
51 #if !defined(TARGET_PPC64)
52 + 10*4 + 22*5 /* SPE GPRh */
53 #endif
54 + 10*4 + 22*5 /* FPR */
55 + 2*(10*6 + 22*7) /* AVRh, AVRl */
56 + 8*5 /* CRF */];
57 static TCGv cpu_gpr[32];
58 #if !defined(TARGET_PPC64)
59 static TCGv cpu_gprh[32];
60 #endif
61 static TCGv_i64 cpu_fpr[32];
62 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 static TCGv cpu_xer;
69 static TCGv cpu_reserve;
70 static TCGv_i32 cpu_fpscr;
71 static TCGv_i32 cpu_access_type;
72
73 #include "gen-icount.h"
74
75 void ppc_translate_init(void)
76 {
77 int i;
78 char* p;
79 static int done_init = 0;
80
81 if (done_init)
82 return;
83
84 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
85
86 p = cpu_reg_names;
87
88 for (i = 0; i < 8; i++) {
89 sprintf(p, "crf%d", i);
90 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
91 offsetof(CPUState, crf[i]), p);
92 p += 5;
93 }
94
95 for (i = 0; i < 32; i++) {
96 sprintf(p, "r%d", i);
97 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
98 offsetof(CPUState, gpr[i]), p);
99 p += (i < 10) ? 3 : 4;
100 #if !defined(TARGET_PPC64)
101 sprintf(p, "r%dH", i);
102 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
103 offsetof(CPUState, gprh[i]), p);
104 p += (i < 10) ? 4 : 5;
105 #endif
106
107 sprintf(p, "fp%d", i);
108 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
109 offsetof(CPUState, fpr[i]), p);
110 p += (i < 10) ? 4 : 5;
111
112 sprintf(p, "avr%dH", i);
113 #ifdef WORDS_BIGENDIAN
114 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUState, avr[i].u64[0]), p);
116 #else
117 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
118 offsetof(CPUState, avr[i].u64[1]), p);
119 #endif
120 p += (i < 10) ? 6 : 7;
121
122 sprintf(p, "avr%dL", i);
123 #ifdef WORDS_BIGENDIAN
124 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUState, avr[i].u64[1]), p);
126 #else
127 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, avr[i].u64[0]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 }
132
133 cpu_nip = tcg_global_mem_new(TCG_AREG0,
134 offsetof(CPUState, nip), "nip");
135
136 cpu_msr = tcg_global_mem_new(TCG_AREG0,
137 offsetof(CPUState, msr), "msr");
138
139 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
140 offsetof(CPUState, ctr), "ctr");
141
142 cpu_lr = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUState, lr), "lr");
144
145 cpu_xer = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUState, xer), "xer");
147
148 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, reserve), "reserve");
150
151 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
152 offsetof(CPUState, fpscr), "fpscr");
153
154 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
155 offsetof(CPUState, access_type), "access_type");
156
157 /* register helpers */
158 #define GEN_HELPER 2
159 #include "helper.h"
160
161 done_init = 1;
162 }
163
164 /* internal defines */
165 typedef struct DisasContext {
166 struct TranslationBlock *tb;
167 target_ulong nip;
168 uint32_t opcode;
169 uint32_t exception;
170 /* Routine used to access memory */
171 int mem_idx;
172 int access_type;
173 /* Translation flags */
174 int le_mode;
175 #if defined(TARGET_PPC64)
176 int sf_mode;
177 #endif
178 int fpu_enabled;
179 int altivec_enabled;
180 int spe_enabled;
181 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
182 int singlestep_enabled;
183 } DisasContext;
184
185 struct opc_handler_t {
186 /* invalid bits */
187 uint32_t inval;
188 /* instruction type */
189 uint64_t type;
190 /* handler */
191 void (*handler)(DisasContext *ctx);
192 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
193 const char *oname;
194 #endif
195 #if defined(DO_PPC_STATISTICS)
196 uint64_t count;
197 #endif
198 };
199
200 static always_inline void gen_reset_fpstatus (void)
201 {
202 #ifdef CONFIG_SOFTFLOAT
203 gen_helper_reset_fpstatus();
204 #endif
205 }
206
207 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
208 {
209 TCGv_i32 t0 = tcg_temp_new_i32();
210
211 if (set_fprf != 0) {
212 /* This case might be optimized later */
213 tcg_gen_movi_i32(t0, 1);
214 gen_helper_compute_fprf(t0, arg, t0);
215 if (unlikely(set_rc)) {
216 tcg_gen_mov_i32(cpu_crf[1], t0);
217 }
218 gen_helper_float_check_status();
219 } else if (unlikely(set_rc)) {
220 /* We always need to compute fpcc */
221 tcg_gen_movi_i32(t0, 0);
222 gen_helper_compute_fprf(t0, arg, t0);
223 tcg_gen_mov_i32(cpu_crf[1], t0);
224 }
225
226 tcg_temp_free_i32(t0);
227 }
228
229 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
230 {
231 if (ctx->access_type != access_type) {
232 tcg_gen_movi_i32(cpu_access_type, access_type);
233 ctx->access_type = access_type;
234 }
235 }
236
237 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
238 {
239 #if defined(TARGET_PPC64)
240 if (ctx->sf_mode)
241 tcg_gen_movi_tl(cpu_nip, nip);
242 else
243 #endif
244 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
245 }
246
247 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
248 {
249 TCGv_i32 t0, t1;
250 if (ctx->exception == POWERPC_EXCP_NONE) {
251 gen_update_nip(ctx, ctx->nip);
252 }
253 t0 = tcg_const_i32(excp);
254 t1 = tcg_const_i32(error);
255 gen_helper_raise_exception_err(t0, t1);
256 tcg_temp_free_i32(t0);
257 tcg_temp_free_i32(t1);
258 ctx->exception = (excp);
259 }
260
261 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
262 {
263 TCGv_i32 t0;
264 if (ctx->exception == POWERPC_EXCP_NONE) {
265 gen_update_nip(ctx, ctx->nip);
266 }
267 t0 = tcg_const_i32(excp);
268 gen_helper_raise_exception(t0);
269 tcg_temp_free_i32(t0);
270 ctx->exception = (excp);
271 }
272
273 static always_inline void gen_debug_exception (DisasContext *ctx)
274 {
275 TCGv_i32 t0;
276 gen_update_nip(ctx, ctx->nip);
277 t0 = tcg_const_i32(EXCP_DEBUG);
278 gen_helper_raise_exception(t0);
279 tcg_temp_free_i32(t0);
280 }
281
282 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
283 {
284 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
285 }
286
287 /* Stop translation */
288 static always_inline void gen_stop_exception (DisasContext *ctx)
289 {
290 gen_update_nip(ctx, ctx->nip);
291 ctx->exception = POWERPC_EXCP_STOP;
292 }
293
294 /* No need to update nip here, as execution flow will change */
295 static always_inline void gen_sync_exception (DisasContext *ctx)
296 {
297 ctx->exception = POWERPC_EXCP_SYNC;
298 }
299
300 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
301 static void gen_##name (DisasContext *ctx); \
302 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
303 static void gen_##name (DisasContext *ctx)
304
305 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
306 static void gen_##name (DisasContext *ctx); \
307 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
308 static void gen_##name (DisasContext *ctx)
309
310 typedef struct opcode_t {
311 unsigned char opc1, opc2, opc3;
312 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
313 unsigned char pad[5];
314 #else
315 unsigned char pad[1];
316 #endif
317 opc_handler_t handler;
318 const char *oname;
319 } opcode_t;
320
321 /*****************************************************************************/
322 /*** Instruction decoding ***/
323 #define EXTRACT_HELPER(name, shift, nb) \
324 static always_inline uint32_t name (uint32_t opcode) \
325 { \
326 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
327 }
328
329 #define EXTRACT_SHELPER(name, shift, nb) \
330 static always_inline int32_t name (uint32_t opcode) \
331 { \
332 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
333 }
334
335 /* Opcode part 1 */
336 EXTRACT_HELPER(opc1, 26, 6);
337 /* Opcode part 2 */
338 EXTRACT_HELPER(opc2, 1, 5);
339 /* Opcode part 3 */
340 EXTRACT_HELPER(opc3, 6, 5);
341 /* Update Cr0 flags */
342 EXTRACT_HELPER(Rc, 0, 1);
343 /* Destination */
344 EXTRACT_HELPER(rD, 21, 5);
345 /* Source */
346 EXTRACT_HELPER(rS, 21, 5);
347 /* First operand */
348 EXTRACT_HELPER(rA, 16, 5);
349 /* Second operand */
350 EXTRACT_HELPER(rB, 11, 5);
351 /* Third operand */
352 EXTRACT_HELPER(rC, 6, 5);
353 /*** Get CRn ***/
354 EXTRACT_HELPER(crfD, 23, 3);
355 EXTRACT_HELPER(crfS, 18, 3);
356 EXTRACT_HELPER(crbD, 21, 5);
357 EXTRACT_HELPER(crbA, 16, 5);
358 EXTRACT_HELPER(crbB, 11, 5);
359 /* SPR / TBL */
360 EXTRACT_HELPER(_SPR, 11, 10);
361 static always_inline uint32_t SPR (uint32_t opcode)
362 {
363 uint32_t sprn = _SPR(opcode);
364
365 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
366 }
367 /*** Get constants ***/
368 EXTRACT_HELPER(IMM, 12, 8);
369 /* 16 bits signed immediate value */
370 EXTRACT_SHELPER(SIMM, 0, 16);
371 /* 16 bits unsigned immediate value */
372 EXTRACT_HELPER(UIMM, 0, 16);
373 /* Bit count */
374 EXTRACT_HELPER(NB, 11, 5);
375 /* Shift count */
376 EXTRACT_HELPER(SH, 11, 5);
377 /* Vector shift count */
378 EXTRACT_HELPER(VSH, 6, 4);
379 /* Mask start */
380 EXTRACT_HELPER(MB, 6, 5);
381 /* Mask end */
382 EXTRACT_HELPER(ME, 1, 5);
383 /* Trap operand */
384 EXTRACT_HELPER(TO, 21, 5);
385
386 EXTRACT_HELPER(CRM, 12, 8);
387 EXTRACT_HELPER(FM, 17, 8);
388 EXTRACT_HELPER(SR, 16, 4);
389 EXTRACT_HELPER(FPIMM, 12, 4);
390
391 /*** Jump target decoding ***/
392 /* Displacement */
393 EXTRACT_SHELPER(d, 0, 16);
394 /* Immediate address */
395 static always_inline target_ulong LI (uint32_t opcode)
396 {
397 return (opcode >> 0) & 0x03FFFFFC;
398 }
399
400 static always_inline uint32_t BD (uint32_t opcode)
401 {
402 return (opcode >> 0) & 0xFFFC;
403 }
404
405 EXTRACT_HELPER(BO, 21, 5);
406 EXTRACT_HELPER(BI, 16, 5);
407 /* Absolute/relative address */
408 EXTRACT_HELPER(AA, 1, 1);
409 /* Link */
410 EXTRACT_HELPER(LK, 0, 1);
411
412 /* Create a mask between <start> and <end> bits */
413 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
414 {
415 target_ulong ret;
416
417 #if defined(TARGET_PPC64)
418 if (likely(start == 0)) {
419 ret = UINT64_MAX << (63 - end);
420 } else if (likely(end == 63)) {
421 ret = UINT64_MAX >> start;
422 }
423 #else
424 if (likely(start == 0)) {
425 ret = UINT32_MAX << (31 - end);
426 } else if (likely(end == 31)) {
427 ret = UINT32_MAX >> start;
428 }
429 #endif
430 else {
431 ret = (((target_ulong)(-1ULL)) >> (start)) ^
432 (((target_ulong)(-1ULL) >> (end)) >> 1);
433 if (unlikely(start > end))
434 return ~ret;
435 }
436
437 return ret;
438 }
439
440 /*****************************************************************************/
441 /* PowerPC Instructions types definitions */
442 enum {
443 PPC_NONE = 0x0000000000000000ULL,
444 /* PowerPC base instructions set */
445 PPC_INSNS_BASE = 0x0000000000000001ULL,
446 /* integer operations instructions */
447 #define PPC_INTEGER PPC_INSNS_BASE
448 /* flow control instructions */
449 #define PPC_FLOW PPC_INSNS_BASE
450 /* virtual memory instructions */
451 #define PPC_MEM PPC_INSNS_BASE
452 /* ld/st with reservation instructions */
453 #define PPC_RES PPC_INSNS_BASE
454 /* spr/msr access instructions */
455 #define PPC_MISC PPC_INSNS_BASE
456 /* Deprecated instruction sets */
457 /* Original POWER instruction set */
458 PPC_POWER = 0x0000000000000002ULL,
459 /* POWER2 instruction set extension */
460 PPC_POWER2 = 0x0000000000000004ULL,
461 /* Power RTC support */
462 PPC_POWER_RTC = 0x0000000000000008ULL,
463 /* Power-to-PowerPC bridge (601) */
464 PPC_POWER_BR = 0x0000000000000010ULL,
465 /* 64 bits PowerPC instruction set */
466 PPC_64B = 0x0000000000000020ULL,
467 /* New 64 bits extensions (PowerPC 2.0x) */
468 PPC_64BX = 0x0000000000000040ULL,
469 /* 64 bits hypervisor extensions */
470 PPC_64H = 0x0000000000000080ULL,
471 /* New wait instruction (PowerPC 2.0x) */
472 PPC_WAIT = 0x0000000000000100ULL,
473 /* Time base mftb instruction */
474 PPC_MFTB = 0x0000000000000200ULL,
475
476 /* Fixed-point unit extensions */
477 /* PowerPC 602 specific */
478 PPC_602_SPEC = 0x0000000000000400ULL,
479 /* isel instruction */
480 PPC_ISEL = 0x0000000000000800ULL,
481 /* popcntb instruction */
482 PPC_POPCNTB = 0x0000000000001000ULL,
483 /* string load / store */
484 PPC_STRING = 0x0000000000002000ULL,
485
486 /* Floating-point unit extensions */
487 /* Optional floating point instructions */
488 PPC_FLOAT = 0x0000000000010000ULL,
489 /* New floating-point extensions (PowerPC 2.0x) */
490 PPC_FLOAT_EXT = 0x0000000000020000ULL,
491 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
492 PPC_FLOAT_FRES = 0x0000000000080000ULL,
493 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
494 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
495 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
496 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
497
498 /* Vector/SIMD extensions */
499 /* Altivec support */
500 PPC_ALTIVEC = 0x0000000001000000ULL,
501 /* PowerPC 2.03 SPE extension */
502 PPC_SPE = 0x0000000002000000ULL,
503 /* PowerPC 2.03 SPE floating-point extension */
504 PPC_SPEFPU = 0x0000000004000000ULL,
505
506 /* Optional memory control instructions */
507 PPC_MEM_TLBIA = 0x0000000010000000ULL,
508 PPC_MEM_TLBIE = 0x0000000020000000ULL,
509 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
510 /* sync instruction */
511 PPC_MEM_SYNC = 0x0000000080000000ULL,
512 /* eieio instruction */
513 PPC_MEM_EIEIO = 0x0000000100000000ULL,
514
515 /* Cache control instructions */
516 PPC_CACHE = 0x0000000200000000ULL,
517 /* icbi instruction */
518 PPC_CACHE_ICBI = 0x0000000400000000ULL,
519 /* dcbz instruction with fixed cache line size */
520 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
521 /* dcbz instruction with tunable cache line size */
522 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
523 /* dcba instruction */
524 PPC_CACHE_DCBA = 0x0000002000000000ULL,
525 /* Freescale cache locking instructions */
526 PPC_CACHE_LOCK = 0x0000004000000000ULL,
527
528 /* MMU related extensions */
529 /* external control instructions */
530 PPC_EXTERN = 0x0000010000000000ULL,
531 /* segment register access instructions */
532 PPC_SEGMENT = 0x0000020000000000ULL,
533 /* PowerPC 6xx TLB management instructions */
534 PPC_6xx_TLB = 0x0000040000000000ULL,
535 /* PowerPC 74xx TLB management instructions */
536 PPC_74xx_TLB = 0x0000080000000000ULL,
537 /* PowerPC 40x TLB management instructions */
538 PPC_40x_TLB = 0x0000100000000000ULL,
539 /* segment register access instructions for PowerPC 64 "bridge" */
540 PPC_SEGMENT_64B = 0x0000200000000000ULL,
541 /* SLB management */
542 PPC_SLBI = 0x0000400000000000ULL,
543
544 /* Embedded PowerPC dedicated instructions */
545 PPC_WRTEE = 0x0001000000000000ULL,
546 /* PowerPC 40x exception model */
547 PPC_40x_EXCP = 0x0002000000000000ULL,
548 /* PowerPC 405 Mac instructions */
549 PPC_405_MAC = 0x0004000000000000ULL,
550 /* PowerPC 440 specific instructions */
551 PPC_440_SPEC = 0x0008000000000000ULL,
552 /* BookE (embedded) PowerPC specification */
553 PPC_BOOKE = 0x0010000000000000ULL,
554 /* mfapidi instruction */
555 PPC_MFAPIDI = 0x0020000000000000ULL,
556 /* tlbiva instruction */
557 PPC_TLBIVA = 0x0040000000000000ULL,
558 /* tlbivax instruction */
559 PPC_TLBIVAX = 0x0080000000000000ULL,
560 /* PowerPC 4xx dedicated instructions */
561 PPC_4xx_COMMON = 0x0100000000000000ULL,
562 /* PowerPC 40x ibct instructions */
563 PPC_40x_ICBT = 0x0200000000000000ULL,
564 /* rfmci is not implemented in all BookE PowerPC */
565 PPC_RFMCI = 0x0400000000000000ULL,
566 /* rfdi instruction */
567 PPC_RFDI = 0x0800000000000000ULL,
568 /* DCR accesses */
569 PPC_DCR = 0x1000000000000000ULL,
570 /* DCR extended accesse */
571 PPC_DCRX = 0x2000000000000000ULL,
572 /* user-mode DCR access, implemented in PowerPC 460 */
573 PPC_DCRUX = 0x4000000000000000ULL,
574 };
575
576 /*****************************************************************************/
577 /* PowerPC instructions table */
578 #if HOST_LONG_BITS == 64
579 #define OPC_ALIGN 8
580 #else
581 #define OPC_ALIGN 4
582 #endif
583 #if defined(__APPLE__)
584 #define OPCODES_SECTION \
585 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
586 #else
587 #define OPCODES_SECTION \
588 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
589 #endif
590
591 #if defined(DO_PPC_STATISTICS)
592 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
593 OPCODES_SECTION opcode_t opc_##name = { \
594 .opc1 = op1, \
595 .opc2 = op2, \
596 .opc3 = op3, \
597 .pad = { 0, }, \
598 .handler = { \
599 .inval = invl, \
600 .type = _typ, \
601 .handler = &gen_##name, \
602 .oname = stringify(name), \
603 }, \
604 .oname = stringify(name), \
605 }
606 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
607 OPCODES_SECTION opcode_t opc_##name = { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval = invl, \
614 .type = _typ, \
615 .handler = &gen_##name, \
616 .oname = onam, \
617 }, \
618 .oname = onam, \
619 }
620 #else
621 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
622 OPCODES_SECTION opcode_t opc_##name = { \
623 .opc1 = op1, \
624 .opc2 = op2, \
625 .opc3 = op3, \
626 .pad = { 0, }, \
627 .handler = { \
628 .inval = invl, \
629 .type = _typ, \
630 .handler = &gen_##name, \
631 }, \
632 .oname = stringify(name), \
633 }
634 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
635 OPCODES_SECTION opcode_t opc_##name = { \
636 .opc1 = op1, \
637 .opc2 = op2, \
638 .opc3 = op3, \
639 .pad = { 0, }, \
640 .handler = { \
641 .inval = invl, \
642 .type = _typ, \
643 .handler = &gen_##name, \
644 }, \
645 .oname = onam, \
646 }
647 #endif
648
649 #define GEN_OPCODE_MARK(name) \
650 OPCODES_SECTION opcode_t opc_##name = { \
651 .opc1 = 0xFF, \
652 .opc2 = 0xFF, \
653 .opc3 = 0xFF, \
654 .pad = { 0, }, \
655 .handler = { \
656 .inval = 0x00000000, \
657 .type = 0x00, \
658 .handler = NULL, \
659 }, \
660 .oname = stringify(name), \
661 }
662
663 /* SPR load/store helpers */
664 static always_inline void gen_load_spr(TCGv t, int reg)
665 {
666 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
667 }
668
669 static always_inline void gen_store_spr(int reg, TCGv t)
670 {
671 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
672 }
673
674 /* Start opcode list */
675 GEN_OPCODE_MARK(start);
676
677 /* Invalid instruction */
678 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
679 {
680 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
681 }
682
683 static opc_handler_t invalid_handler = {
684 .inval = 0xFFFFFFFF,
685 .type = PPC_NONE,
686 .handler = gen_invalid,
687 };
688
689 /*** Integer comparison ***/
690
691 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
692 {
693 int l1, l2, l3;
694
695 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
696 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
697 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
698
699 l1 = gen_new_label();
700 l2 = gen_new_label();
701 l3 = gen_new_label();
702 if (s) {
703 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
704 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
705 } else {
706 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
707 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
708 }
709 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
710 tcg_gen_br(l3);
711 gen_set_label(l1);
712 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
713 tcg_gen_br(l3);
714 gen_set_label(l2);
715 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
716 gen_set_label(l3);
717 }
718
719 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
720 {
721 TCGv t0 = tcg_const_local_tl(arg1);
722 gen_op_cmp(arg0, t0, s, crf);
723 tcg_temp_free(t0);
724 }
725
726 #if defined(TARGET_PPC64)
727 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
728 {
729 TCGv t0, t1;
730 t0 = tcg_temp_local_new();
731 t1 = tcg_temp_local_new();
732 if (s) {
733 tcg_gen_ext32s_tl(t0, arg0);
734 tcg_gen_ext32s_tl(t1, arg1);
735 } else {
736 tcg_gen_ext32u_tl(t0, arg0);
737 tcg_gen_ext32u_tl(t1, arg1);
738 }
739 gen_op_cmp(t0, t1, s, crf);
740 tcg_temp_free(t1);
741 tcg_temp_free(t0);
742 }
743
744 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
745 {
746 TCGv t0 = tcg_const_local_tl(arg1);
747 gen_op_cmp32(arg0, t0, s, crf);
748 tcg_temp_free(t0);
749 }
750 #endif
751
752 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
753 {
754 #if defined(TARGET_PPC64)
755 if (!(ctx->sf_mode))
756 gen_op_cmpi32(reg, 0, 1, 0);
757 else
758 #endif
759 gen_op_cmpi(reg, 0, 1, 0);
760 }
761
762 /* cmp */
763 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
764 {
765 #if defined(TARGET_PPC64)
766 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
767 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
768 1, crfD(ctx->opcode));
769 else
770 #endif
771 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
772 1, crfD(ctx->opcode));
773 }
774
775 /* cmpi */
776 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
777 {
778 #if defined(TARGET_PPC64)
779 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
780 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
781 1, crfD(ctx->opcode));
782 else
783 #endif
784 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
785 1, crfD(ctx->opcode));
786 }
787
788 /* cmpl */
789 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
790 {
791 #if defined(TARGET_PPC64)
792 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
793 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
794 0, crfD(ctx->opcode));
795 else
796 #endif
797 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
798 0, crfD(ctx->opcode));
799 }
800
801 /* cmpli */
802 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
803 {
804 #if defined(TARGET_PPC64)
805 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
806 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
807 0, crfD(ctx->opcode));
808 else
809 #endif
810 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
811 0, crfD(ctx->opcode));
812 }
813
814 /* isel (PowerPC 2.03 specification) */
815 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
816 {
817 int l1, l2;
818 uint32_t bi = rC(ctx->opcode);
819 uint32_t mask;
820 TCGv_i32 t0;
821
822 l1 = gen_new_label();
823 l2 = gen_new_label();
824
825 mask = 1 << (3 - (bi & 0x03));
826 t0 = tcg_temp_new_i32();
827 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
828 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
829 if (rA(ctx->opcode) == 0)
830 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
831 else
832 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
833 tcg_gen_br(l2);
834 gen_set_label(l1);
835 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
836 gen_set_label(l2);
837 tcg_temp_free_i32(t0);
838 }
839
840 /*** Integer arithmetic ***/
841
842 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
843 {
844 int l1;
845 TCGv t0;
846
847 l1 = gen_new_label();
848 /* Start with XER OV disabled, the most likely case */
849 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
850 t0 = tcg_temp_local_new();
851 tcg_gen_xor_tl(t0, arg0, arg1);
852 #if defined(TARGET_PPC64)
853 if (!ctx->sf_mode)
854 tcg_gen_ext32s_tl(t0, t0);
855 #endif
856 if (sub)
857 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
858 else
859 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
860 tcg_gen_xor_tl(t0, arg1, arg2);
861 #if defined(TARGET_PPC64)
862 if (!ctx->sf_mode)
863 tcg_gen_ext32s_tl(t0, t0);
864 #endif
865 if (sub)
866 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
867 else
868 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
869 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
870 gen_set_label(l1);
871 tcg_temp_free(t0);
872 }
873
874 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
875 {
876 int l1 = gen_new_label();
877
878 #if defined(TARGET_PPC64)
879 if (!(ctx->sf_mode)) {
880 TCGv t0, t1;
881 t0 = tcg_temp_new();
882 t1 = tcg_temp_new();
883
884 tcg_gen_ext32u_tl(t0, arg1);
885 tcg_gen_ext32u_tl(t1, arg2);
886 if (sub) {
887 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
888 } else {
889 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
890 }
891 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
892 gen_set_label(l1);
893 tcg_temp_free(t0);
894 tcg_temp_free(t1);
895 } else
896 #endif
897 {
898 if (sub) {
899 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
900 } else {
901 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
902 }
903 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
904 gen_set_label(l1);
905 }
906 }
907
908 /* Common add function */
909 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
910 int add_ca, int compute_ca, int compute_ov)
911 {
912 TCGv t0, t1;
913
914 if ((!compute_ca && !compute_ov) ||
915 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
916 t0 = ret;
917 } else {
918 t0 = tcg_temp_local_new();
919 }
920
921 if (add_ca) {
922 t1 = tcg_temp_local_new();
923 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
924 tcg_gen_shri_tl(t1, t1, XER_CA);
925 }
926
927 if (compute_ca && compute_ov) {
928 /* Start with XER CA and OV disabled, the most likely case */
929 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
930 } else if (compute_ca) {
931 /* Start with XER CA disabled, the most likely case */
932 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
933 } else if (compute_ov) {
934 /* Start with XER OV disabled, the most likely case */
935 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
936 }
937
938 tcg_gen_add_tl(t0, arg1, arg2);
939
940 if (compute_ca) {
941 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
942 }
943 if (add_ca) {
944 tcg_gen_add_tl(t0, t0, t1);
945 gen_op_arith_compute_ca(ctx, t0, t1, 0);
946 tcg_temp_free(t1);
947 }
948 if (compute_ov) {
949 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
950 }
951
952 if (unlikely(Rc(ctx->opcode) != 0))
953 gen_set_Rc0(ctx, t0);
954
955 if (!TCGV_EQUAL(t0, ret)) {
956 tcg_gen_mov_tl(ret, t0);
957 tcg_temp_free(t0);
958 }
959 }
960 /* Add functions with two operands */
961 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
962 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
963 { \
964 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
965 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
966 add_ca, compute_ca, compute_ov); \
967 }
968 /* Add functions with one operand and one immediate */
969 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
970 add_ca, compute_ca, compute_ov) \
971 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
972 { \
973 TCGv t0 = tcg_const_local_tl(const_val); \
974 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
975 cpu_gpr[rA(ctx->opcode)], t0, \
976 add_ca, compute_ca, compute_ov); \
977 tcg_temp_free(t0); \
978 }
979
980 /* add add. addo addo. */
981 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
982 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
983 /* addc addc. addco addco. */
984 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
985 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
986 /* adde adde. addeo addeo. */
987 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
988 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
989 /* addme addme. addmeo addmeo. */
990 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
991 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
992 /* addze addze. addzeo addzeo.*/
993 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
994 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
995 /* addi */
996 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
997 {
998 target_long simm = SIMM(ctx->opcode);
999
1000 if (rA(ctx->opcode) == 0) {
1001 /* li case */
1002 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1003 } else {
1004 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1005 }
1006 }
1007 /* addic addic.*/
1008 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1009 int compute_Rc0)
1010 {
1011 target_long simm = SIMM(ctx->opcode);
1012
1013 /* Start with XER CA and OV disabled, the most likely case */
1014 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1015
1016 if (likely(simm != 0)) {
1017 TCGv t0 = tcg_temp_local_new();
1018 tcg_gen_addi_tl(t0, arg1, simm);
1019 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1020 tcg_gen_mov_tl(ret, t0);
1021 tcg_temp_free(t0);
1022 } else {
1023 tcg_gen_mov_tl(ret, arg1);
1024 }
1025 if (compute_Rc0) {
1026 gen_set_Rc0(ctx, ret);
1027 }
1028 }
1029 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1030 {
1031 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1032 }
1033 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1034 {
1035 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1036 }
1037 /* addis */
1038 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1039 {
1040 target_long simm = SIMM(ctx->opcode);
1041
1042 if (rA(ctx->opcode) == 0) {
1043 /* lis case */
1044 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1045 } else {
1046 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1047 }
1048 }
1049
1050 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1051 int sign, int compute_ov)
1052 {
1053 int l1 = gen_new_label();
1054 int l2 = gen_new_label();
1055 TCGv_i32 t0 = tcg_temp_local_new_i32();
1056 TCGv_i32 t1 = tcg_temp_local_new_i32();
1057
1058 tcg_gen_trunc_tl_i32(t0, arg1);
1059 tcg_gen_trunc_tl_i32(t1, arg2);
1060 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1061 if (sign) {
1062 int l3 = gen_new_label();
1063 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1064 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1065 gen_set_label(l3);
1066 tcg_gen_div_i32(t0, t0, t1);
1067 } else {
1068 tcg_gen_divu_i32(t0, t0, t1);
1069 }
1070 if (compute_ov) {
1071 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1072 }
1073 tcg_gen_br(l2);
1074 gen_set_label(l1);
1075 if (sign) {
1076 tcg_gen_sari_i32(t0, t0, 31);
1077 } else {
1078 tcg_gen_movi_i32(t0, 0);
1079 }
1080 if (compute_ov) {
1081 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1082 }
1083 gen_set_label(l2);
1084 tcg_gen_extu_i32_tl(ret, t0);
1085 tcg_temp_free_i32(t0);
1086 tcg_temp_free_i32(t1);
1087 if (unlikely(Rc(ctx->opcode) != 0))
1088 gen_set_Rc0(ctx, ret);
1089 }
1090 /* Div functions */
1091 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1092 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1093 { \
1094 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1095 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1096 sign, compute_ov); \
1097 }
1098 /* divwu divwu. divwuo divwuo. */
1099 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1100 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1101 /* divw divw. divwo divwo. */
1102 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1103 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1104 #if defined(TARGET_PPC64)
1105 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1106 int sign, int compute_ov)
1107 {
1108 int l1 = gen_new_label();
1109 int l2 = gen_new_label();
1110
1111 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1112 if (sign) {
1113 int l3 = gen_new_label();
1114 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1115 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1116 gen_set_label(l3);
1117 tcg_gen_div_i64(ret, arg1, arg2);
1118 } else {
1119 tcg_gen_divu_i64(ret, arg1, arg2);
1120 }
1121 if (compute_ov) {
1122 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1123 }
1124 tcg_gen_br(l2);
1125 gen_set_label(l1);
1126 if (sign) {
1127 tcg_gen_sari_i64(ret, arg1, 63);
1128 } else {
1129 tcg_gen_movi_i64(ret, 0);
1130 }
1131 if (compute_ov) {
1132 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1133 }
1134 gen_set_label(l2);
1135 if (unlikely(Rc(ctx->opcode) != 0))
1136 gen_set_Rc0(ctx, ret);
1137 }
1138 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1139 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1140 { \
1141 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1142 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1143 sign, compute_ov); \
1144 }
1145 /* divwu divwu. divwuo divwuo. */
1146 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1147 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1148 /* divw divw. divwo divwo. */
1149 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1150 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1151 #endif
1152
1153 /* mulhw mulhw. */
1154 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1155 {
1156 TCGv_i64 t0, t1;
1157
1158 t0 = tcg_temp_new_i64();
1159 t1 = tcg_temp_new_i64();
1160 #if defined(TARGET_PPC64)
1161 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1162 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1163 tcg_gen_mul_i64(t0, t0, t1);
1164 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1165 #else
1166 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1167 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1168 tcg_gen_mul_i64(t0, t0, t1);
1169 tcg_gen_shri_i64(t0, t0, 32);
1170 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1171 #endif
1172 tcg_temp_free_i64(t0);
1173 tcg_temp_free_i64(t1);
1174 if (unlikely(Rc(ctx->opcode) != 0))
1175 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1176 }
1177 /* mulhwu mulhwu. */
1178 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1179 {
1180 TCGv_i64 t0, t1;
1181
1182 t0 = tcg_temp_new_i64();
1183 t1 = tcg_temp_new_i64();
1184 #if defined(TARGET_PPC64)
1185 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1186 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1187 tcg_gen_mul_i64(t0, t0, t1);
1188 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1189 #else
1190 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1191 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1192 tcg_gen_mul_i64(t0, t0, t1);
1193 tcg_gen_shri_i64(t0, t0, 32);
1194 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1195 #endif
1196 tcg_temp_free_i64(t0);
1197 tcg_temp_free_i64(t1);
1198 if (unlikely(Rc(ctx->opcode) != 0))
1199 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1200 }
1201 /* mullw mullw. */
1202 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1203 {
1204 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1205 cpu_gpr[rB(ctx->opcode)]);
1206 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1207 if (unlikely(Rc(ctx->opcode) != 0))
1208 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1209 }
1210 /* mullwo mullwo. */
1211 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1212 {
1213 int l1;
1214 TCGv_i64 t0, t1;
1215
1216 t0 = tcg_temp_new_i64();
1217 t1 = tcg_temp_new_i64();
1218 l1 = gen_new_label();
1219 /* Start with XER OV disabled, the most likely case */
1220 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1221 #if defined(TARGET_PPC64)
1222 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1223 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1224 #else
1225 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1226 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1227 #endif
1228 tcg_gen_mul_i64(t0, t0, t1);
1229 #if defined(TARGET_PPC64)
1230 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1231 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1232 #else
1233 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1234 tcg_gen_ext32s_i64(t1, t0);
1235 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1236 #endif
1237 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1238 gen_set_label(l1);
1239 tcg_temp_free_i64(t0);
1240 tcg_temp_free_i64(t1);
1241 if (unlikely(Rc(ctx->opcode) != 0))
1242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1243 }
1244 /* mulli */
1245 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1246 {
1247 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1248 SIMM(ctx->opcode));
1249 }
1250 #if defined(TARGET_PPC64)
1251 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1252 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1253 { \
1254 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1255 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1256 if (unlikely(Rc(ctx->opcode) != 0)) \
1257 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1258 }
1259 /* mulhd mulhd. */
1260 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1261 /* mulhdu mulhdu. */
1262 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1263 /* mulld mulld. */
1264 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1265 {
1266 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1267 cpu_gpr[rB(ctx->opcode)]);
1268 if (unlikely(Rc(ctx->opcode) != 0))
1269 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1270 }
1271 /* mulldo mulldo. */
1272 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1273 #endif
1274
1275 /* neg neg. nego nego. */
1276 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1277 {
1278 int l1 = gen_new_label();
1279 int l2 = gen_new_label();
1280 TCGv t0 = tcg_temp_local_new();
1281 #if defined(TARGET_PPC64)
1282 if (ctx->sf_mode) {
1283 tcg_gen_mov_tl(t0, arg1);
1284 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1285 } else
1286 #endif
1287 {
1288 tcg_gen_ext32s_tl(t0, arg1);
1289 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1290 }
1291 tcg_gen_neg_tl(ret, arg1);
1292 if (ov_check) {
1293 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1294 }
1295 tcg_gen_br(l2);
1296 gen_set_label(l1);
1297 tcg_gen_mov_tl(ret, t0);
1298 if (ov_check) {
1299 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1300 }
1301 gen_set_label(l2);
1302 tcg_temp_free(t0);
1303 if (unlikely(Rc(ctx->opcode) != 0))
1304 gen_set_Rc0(ctx, ret);
1305 }
1306 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1307 {
1308 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1309 }
1310 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1311 {
1312 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1313 }
1314
1315 /* Common subf function */
1316 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1317 int add_ca, int compute_ca, int compute_ov)
1318 {
1319 TCGv t0, t1;
1320
1321 if ((!compute_ca && !compute_ov) ||
1322 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1323 t0 = ret;
1324 } else {
1325 t0 = tcg_temp_local_new();
1326 }
1327
1328 if (add_ca) {
1329 t1 = tcg_temp_local_new();
1330 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1331 tcg_gen_shri_tl(t1, t1, XER_CA);
1332 }
1333
1334 if (compute_ca && compute_ov) {
1335 /* Start with XER CA and OV disabled, the most likely case */
1336 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1337 } else if (compute_ca) {
1338 /* Start with XER CA disabled, the most likely case */
1339 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1340 } else if (compute_ov) {
1341 /* Start with XER OV disabled, the most likely case */
1342 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1343 }
1344
1345 if (add_ca) {
1346 tcg_gen_not_tl(t0, arg1);
1347 tcg_gen_add_tl(t0, t0, arg2);
1348 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1349 tcg_gen_add_tl(t0, t0, t1);
1350 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1351 tcg_temp_free(t1);
1352 } else {
1353 tcg_gen_sub_tl(t0, arg2, arg1);
1354 if (compute_ca) {
1355 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1356 }
1357 }
1358 if (compute_ov) {
1359 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1360 }
1361
1362 if (unlikely(Rc(ctx->opcode) != 0))
1363 gen_set_Rc0(ctx, t0);
1364
1365 if (!TCGV_EQUAL(t0, ret)) {
1366 tcg_gen_mov_tl(ret, t0);
1367 tcg_temp_free(t0);
1368 }
1369 }
1370 /* Sub functions with Two operands functions */
1371 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1372 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1373 { \
1374 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1375 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1376 add_ca, compute_ca, compute_ov); \
1377 }
1378 /* Sub functions with one operand and one immediate */
1379 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1380 add_ca, compute_ca, compute_ov) \
1381 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1382 { \
1383 TCGv t0 = tcg_const_local_tl(const_val); \
1384 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1385 cpu_gpr[rA(ctx->opcode)], t0, \
1386 add_ca, compute_ca, compute_ov); \
1387 tcg_temp_free(t0); \
1388 }
1389 /* subf subf. subfo subfo. */
1390 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1391 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1392 /* subfc subfc. subfco subfco. */
1393 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1394 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1395 /* subfe subfe. subfeo subfo. */
1396 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1397 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1398 /* subfme subfme. subfmeo subfmeo. */
1399 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1400 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1401 /* subfze subfze. subfzeo subfzeo.*/
1402 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1403 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1404 /* subfic */
1405 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1406 {
1407 /* Start with XER CA and OV disabled, the most likely case */
1408 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1409 TCGv t0 = tcg_temp_local_new();
1410 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1411 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1412 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1413 tcg_temp_free(t1);
1414 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1415 tcg_temp_free(t0);
1416 }
1417
1418 /*** Integer logical ***/
1419 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1420 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1421 { \
1422 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1423 cpu_gpr[rB(ctx->opcode)]); \
1424 if (unlikely(Rc(ctx->opcode) != 0)) \
1425 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1426 }
1427
1428 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1429 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1430 { \
1431 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1432 if (unlikely(Rc(ctx->opcode) != 0)) \
1433 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1434 }
1435
1436 /* and & and. */
1437 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1438 /* andc & andc. */
1439 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1440 /* andi. */
1441 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1442 {
1443 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1444 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1445 }
1446 /* andis. */
1447 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1448 {
1449 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1451 }
1452 /* cntlzw */
1453 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1454 {
1455 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1456 if (unlikely(Rc(ctx->opcode) != 0))
1457 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1458 }
1459 /* eqv & eqv. */
1460 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1461 /* extsb & extsb. */
1462 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1463 /* extsh & extsh. */
1464 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1465 /* nand & nand. */
1466 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1467 /* nor & nor. */
1468 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1469 /* or & or. */
1470 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1471 {
1472 int rs, ra, rb;
1473
1474 rs = rS(ctx->opcode);
1475 ra = rA(ctx->opcode);
1476 rb = rB(ctx->opcode);
1477 /* Optimisation for mr. ri case */
1478 if (rs != ra || rs != rb) {
1479 if (rs != rb)
1480 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1481 else
1482 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1483 if (unlikely(Rc(ctx->opcode) != 0))
1484 gen_set_Rc0(ctx, cpu_gpr[ra]);
1485 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1486 gen_set_Rc0(ctx, cpu_gpr[rs]);
1487 #if defined(TARGET_PPC64)
1488 } else {
1489 int prio = 0;
1490
1491 switch (rs) {
1492 case 1:
1493 /* Set process priority to low */
1494 prio = 2;
1495 break;
1496 case 6:
1497 /* Set process priority to medium-low */
1498 prio = 3;
1499 break;
1500 case 2:
1501 /* Set process priority to normal */
1502 prio = 4;
1503 break;
1504 #if !defined(CONFIG_USER_ONLY)
1505 case 31:
1506 if (ctx->mem_idx > 0) {
1507 /* Set process priority to very low */
1508 prio = 1;
1509 }
1510 break;
1511 case 5:
1512 if (ctx->mem_idx > 0) {
1513 /* Set process priority to medium-hight */
1514 prio = 5;
1515 }
1516 break;
1517 case 3:
1518 if (ctx->mem_idx > 0) {
1519 /* Set process priority to high */
1520 prio = 6;
1521 }
1522 break;
1523 case 7:
1524 if (ctx->mem_idx > 1) {
1525 /* Set process priority to very high */
1526 prio = 7;
1527 }
1528 break;
1529 #endif
1530 default:
1531 /* nop */
1532 break;
1533 }
1534 if (prio) {
1535 TCGv t0 = tcg_temp_new();
1536 gen_load_spr(t0, SPR_PPR);
1537 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1538 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1539 gen_store_spr(SPR_PPR, t0);
1540 tcg_temp_free(t0);
1541 }
1542 #endif
1543 }
1544 }
1545 /* orc & orc. */
1546 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1547 /* xor & xor. */
1548 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1549 {
1550 /* Optimisation for "set to zero" case */
1551 if (rS(ctx->opcode) != rB(ctx->opcode))
1552 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1553 else
1554 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1555 if (unlikely(Rc(ctx->opcode) != 0))
1556 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1557 }
1558 /* ori */
1559 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1560 {
1561 target_ulong uimm = UIMM(ctx->opcode);
1562
1563 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1564 /* NOP */
1565 /* XXX: should handle special NOPs for POWER series */
1566 return;
1567 }
1568 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1569 }
1570 /* oris */
1571 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1572 {
1573 target_ulong uimm = UIMM(ctx->opcode);
1574
1575 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1576 /* NOP */
1577 return;
1578 }
1579 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1580 }
1581 /* xori */
1582 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1583 {
1584 target_ulong uimm = UIMM(ctx->opcode);
1585
1586 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1587 /* NOP */
1588 return;
1589 }
1590 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1591 }
1592 /* xoris */
1593 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1594 {
1595 target_ulong uimm = UIMM(ctx->opcode);
1596
1597 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1598 /* NOP */
1599 return;
1600 }
1601 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1602 }
1603 /* popcntb : PowerPC 2.03 specification */
1604 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1605 {
1606 #if defined(TARGET_PPC64)
1607 if (ctx->sf_mode)
1608 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1609 else
1610 #endif
1611 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1612 }
1613
1614 #if defined(TARGET_PPC64)
1615 /* extsw & extsw. */
1616 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1617 /* cntlzd */
1618 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1619 {
1620 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1621 if (unlikely(Rc(ctx->opcode) != 0))
1622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1623 }
1624 #endif
1625
1626 /*** Integer rotate ***/
1627 /* rlwimi & rlwimi. */
1628 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1629 {
1630 uint32_t mb, me, sh;
1631
1632 mb = MB(ctx->opcode);
1633 me = ME(ctx->opcode);
1634 sh = SH(ctx->opcode);
1635 if (likely(sh == 0 && mb == 0 && me == 31)) {
1636 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1637 } else {
1638 target_ulong mask;
1639 TCGv t1;
1640 TCGv t0 = tcg_temp_new();
1641 #if defined(TARGET_PPC64)
1642 TCGv_i32 t2 = tcg_temp_new_i32();
1643 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1644 tcg_gen_rotli_i32(t2, t2, sh);
1645 tcg_gen_extu_i32_i64(t0, t2);
1646 tcg_temp_free_i32(t2);
1647 #else
1648 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1649 #endif
1650 #if defined(TARGET_PPC64)
1651 mb += 32;
1652 me += 32;
1653 #endif
1654 mask = MASK(mb, me);
1655 t1 = tcg_temp_new();
1656 tcg_gen_andi_tl(t0, t0, mask);
1657 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1658 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1659 tcg_temp_free(t0);
1660 tcg_temp_free(t1);
1661 }
1662 if (unlikely(Rc(ctx->opcode) != 0))
1663 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1664 }
1665 /* rlwinm & rlwinm. */
1666 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1667 {
1668 uint32_t mb, me, sh;
1669
1670 sh = SH(ctx->opcode);
1671 mb = MB(ctx->opcode);
1672 me = ME(ctx->opcode);
1673
1674 if (likely(mb == 0 && me == (31 - sh))) {
1675 if (likely(sh == 0)) {
1676 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1677 } else {
1678 TCGv t0 = tcg_temp_new();
1679 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1680 tcg_gen_shli_tl(t0, t0, sh);
1681 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1682 tcg_temp_free(t0);
1683 }
1684 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1685 TCGv t0 = tcg_temp_new();
1686 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1687 tcg_gen_shri_tl(t0, t0, mb);
1688 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1689 tcg_temp_free(t0);
1690 } else {
1691 TCGv t0 = tcg_temp_new();
1692 #if defined(TARGET_PPC64)
1693 TCGv_i32 t1 = tcg_temp_new_i32();
1694 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1695 tcg_gen_rotli_i32(t1, t1, sh);
1696 tcg_gen_extu_i32_i64(t0, t1);
1697 tcg_temp_free_i32(t1);
1698 #else
1699 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1700 #endif
1701 #if defined(TARGET_PPC64)
1702 mb += 32;
1703 me += 32;
1704 #endif
1705 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1706 tcg_temp_free(t0);
1707 }
1708 if (unlikely(Rc(ctx->opcode) != 0))
1709 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1710 }
1711 /* rlwnm & rlwnm. */
1712 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1713 {
1714 uint32_t mb, me;
1715 TCGv t0;
1716 #if defined(TARGET_PPC64)
1717 TCGv_i32 t1, t2;
1718 #endif
1719
1720 mb = MB(ctx->opcode);
1721 me = ME(ctx->opcode);
1722 t0 = tcg_temp_new();
1723 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1724 #if defined(TARGET_PPC64)
1725 t1 = tcg_temp_new_i32();
1726 t2 = tcg_temp_new_i32();
1727 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1728 tcg_gen_trunc_i64_i32(t2, t0);
1729 tcg_gen_rotl_i32(t1, t1, t2);
1730 tcg_gen_extu_i32_i64(t0, t1);
1731 tcg_temp_free_i32(t1);
1732 tcg_temp_free_i32(t2);
1733 #else
1734 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1735 #endif
1736 if (unlikely(mb != 0 || me != 31)) {
1737 #if defined(TARGET_PPC64)
1738 mb += 32;
1739 me += 32;
1740 #endif
1741 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1742 } else {
1743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1744 }
1745 tcg_temp_free(t0);
1746 if (unlikely(Rc(ctx->opcode) != 0))
1747 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1748 }
1749
1750 #if defined(TARGET_PPC64)
1751 #define GEN_PPC64_R2(name, opc1, opc2) \
1752 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1753 { \
1754 gen_##name(ctx, 0); \
1755 } \
1756 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1757 PPC_64B) \
1758 { \
1759 gen_##name(ctx, 1); \
1760 }
1761 #define GEN_PPC64_R4(name, opc1, opc2) \
1762 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1763 { \
1764 gen_##name(ctx, 0, 0); \
1765 } \
1766 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1767 PPC_64B) \
1768 { \
1769 gen_##name(ctx, 0, 1); \
1770 } \
1771 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1772 PPC_64B) \
1773 { \
1774 gen_##name(ctx, 1, 0); \
1775 } \
1776 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1777 PPC_64B) \
1778 { \
1779 gen_##name(ctx, 1, 1); \
1780 }
1781
1782 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1783 uint32_t me, uint32_t sh)
1784 {
1785 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1786 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1787 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1788 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1789 } else {
1790 TCGv t0 = tcg_temp_new();
1791 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1792 if (likely(mb == 0 && me == 63)) {
1793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1794 } else {
1795 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1796 }
1797 tcg_temp_free(t0);
1798 }
1799 if (unlikely(Rc(ctx->opcode) != 0))
1800 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1801 }
1802 /* rldicl - rldicl. */
1803 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1804 {
1805 uint32_t sh, mb;
1806
1807 sh = SH(ctx->opcode) | (shn << 5);
1808 mb = MB(ctx->opcode) | (mbn << 5);
1809 gen_rldinm(ctx, mb, 63, sh);
1810 }
1811 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1812 /* rldicr - rldicr. */
1813 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1814 {
1815 uint32_t sh, me;
1816
1817 sh = SH(ctx->opcode) | (shn << 5);
1818 me = MB(ctx->opcode) | (men << 5);
1819 gen_rldinm(ctx, 0, me, sh);
1820 }
1821 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1822 /* rldic - rldic. */
1823 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1824 {
1825 uint32_t sh, mb;
1826
1827 sh = SH(ctx->opcode) | (shn << 5);
1828 mb = MB(ctx->opcode) | (mbn << 5);
1829 gen_rldinm(ctx, mb, 63 - sh, sh);
1830 }
1831 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1832
1833 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1834 uint32_t me)
1835 {
1836 TCGv t0;
1837
1838 mb = MB(ctx->opcode);
1839 me = ME(ctx->opcode);
1840 t0 = tcg_temp_new();
1841 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1842 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1843 if (unlikely(mb != 0 || me != 63)) {
1844 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1845 } else {
1846 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1847 }
1848 tcg_temp_free(t0);
1849 if (unlikely(Rc(ctx->opcode) != 0))
1850 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1851 }
1852
1853 /* rldcl - rldcl. */
1854 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1855 {
1856 uint32_t mb;
1857
1858 mb = MB(ctx->opcode) | (mbn << 5);
1859 gen_rldnm(ctx, mb, 63);
1860 }
1861 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1862 /* rldcr - rldcr. */
1863 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1864 {
1865 uint32_t me;
1866
1867 me = MB(ctx->opcode) | (men << 5);
1868 gen_rldnm(ctx, 0, me);
1869 }
1870 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1871 /* rldimi - rldimi. */
1872 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1873 {
1874 uint32_t sh, mb, me;
1875
1876 sh = SH(ctx->opcode) | (shn << 5);
1877 mb = MB(ctx->opcode) | (mbn << 5);
1878 me = 63 - sh;
1879 if (unlikely(sh == 0 && mb == 0)) {
1880 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1881 } else {
1882 TCGv t0, t1;
1883 target_ulong mask;
1884
1885 t0 = tcg_temp_new();
1886 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1887 t1 = tcg_temp_new();
1888 mask = MASK(mb, me);
1889 tcg_gen_andi_tl(t0, t0, mask);
1890 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1891 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1892 tcg_temp_free(t0);
1893 tcg_temp_free(t1);
1894 }
1895 if (unlikely(Rc(ctx->opcode) != 0))
1896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1897 }
1898 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1899 #endif
1900
1901 /*** Integer shift ***/
1902 /* slw & slw. */
1903 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1904 {
1905 TCGv t0;
1906 int l1, l2;
1907 l1 = gen_new_label();
1908 l2 = gen_new_label();
1909
1910 t0 = tcg_temp_local_new();
1911 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1912 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1913 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1914 tcg_gen_br(l2);
1915 gen_set_label(l1);
1916 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1917 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1918 gen_set_label(l2);
1919 tcg_temp_free(t0);
1920 if (unlikely(Rc(ctx->opcode) != 0))
1921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1922 }
1923 /* sraw & sraw. */
1924 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1925 {
1926 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1927 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1928 if (unlikely(Rc(ctx->opcode) != 0))
1929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1930 }
1931 /* srawi & srawi. */
1932 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1933 {
1934 int sh = SH(ctx->opcode);
1935 if (sh != 0) {
1936 int l1, l2;
1937 TCGv t0;
1938 l1 = gen_new_label();
1939 l2 = gen_new_label();
1940 t0 = tcg_temp_local_new();
1941 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1942 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1943 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1944 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1945 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1946 tcg_gen_br(l2);
1947 gen_set_label(l1);
1948 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1949 gen_set_label(l2);
1950 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1951 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1952 tcg_temp_free(t0);
1953 } else {
1954 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1955 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1956 }
1957 if (unlikely(Rc(ctx->opcode) != 0))
1958 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1959 }
1960 /* srw & srw. */
1961 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1962 {
1963 TCGv t0, t1;
1964 int l1, l2;
1965 l1 = gen_new_label();
1966 l2 = gen_new_label();
1967
1968 t0 = tcg_temp_local_new();
1969 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1970 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1971 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1972 tcg_gen_br(l2);
1973 gen_set_label(l1);
1974 t1 = tcg_temp_new();
1975 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1976 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1977 tcg_temp_free(t1);
1978 gen_set_label(l2);
1979 tcg_temp_free(t0);
1980 if (unlikely(Rc(ctx->opcode) != 0))
1981 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1982 }
1983 #if defined(TARGET_PPC64)
1984 /* sld & sld. */
1985 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
1986 {
1987 TCGv t0;
1988 int l1, l2;
1989 l1 = gen_new_label();
1990 l2 = gen_new_label();
1991
1992 t0 = tcg_temp_local_new();
1993 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1994 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
1995 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1996 tcg_gen_br(l2);
1997 gen_set_label(l1);
1998 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1999 gen_set_label(l2);
2000 tcg_temp_free(t0);
2001 if (unlikely(Rc(ctx->opcode) != 0))
2002 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2003 }
2004 /* srad & srad. */
2005 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2006 {
2007 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2008 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2009 if (unlikely(Rc(ctx->opcode) != 0))
2010 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2011 }
2012 /* sradi & sradi. */
2013 static always_inline void gen_sradi (DisasContext *ctx, int n)
2014 {
2015 int sh = SH(ctx->opcode) + (n << 5);
2016 if (sh != 0) {
2017 int l1, l2;
2018 TCGv t0;
2019 l1 = gen_new_label();
2020 l2 = gen_new_label();
2021 t0 = tcg_temp_local_new();
2022 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2023 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2024 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2025 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2026 tcg_gen_br(l2);
2027 gen_set_label(l1);
2028 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2029 gen_set_label(l2);
2030 tcg_temp_free(t0);
2031 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2032 } else {
2033 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2034 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2035 }
2036 if (unlikely(Rc(ctx->opcode) != 0))
2037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2038 }
2039 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2040 {
2041 gen_sradi(ctx, 0);
2042 }
2043 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2044 {
2045 gen_sradi(ctx, 1);
2046 }
2047 /* srd & srd. */
2048 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2049 {
2050 TCGv t0;
2051 int l1, l2;
2052 l1 = gen_new_label();
2053 l2 = gen_new_label();
2054
2055 t0 = tcg_temp_local_new();
2056 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2057 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2058 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2059 tcg_gen_br(l2);
2060 gen_set_label(l1);
2061 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2062 gen_set_label(l2);
2063 tcg_temp_free(t0);
2064 if (unlikely(Rc(ctx->opcode) != 0))
2065 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2066 }
2067 #endif
2068
2069 /*** Floating-Point arithmetic ***/
2070 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2071 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2072 { \
2073 if (unlikely(!ctx->fpu_enabled)) { \
2074 gen_exception(ctx, POWERPC_EXCP_FPU); \
2075 return; \
2076 } \
2077 /* NIP cannot be restored if the memory exception comes from an helper */ \
2078 gen_update_nip(ctx, ctx->nip - 4); \
2079 gen_reset_fpstatus(); \
2080 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2081 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2082 if (isfloat) { \
2083 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2084 } \
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2086 Rc(ctx->opcode) != 0); \
2087 }
2088
2089 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2090 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2091 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2092
2093 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2094 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2095 { \
2096 if (unlikely(!ctx->fpu_enabled)) { \
2097 gen_exception(ctx, POWERPC_EXCP_FPU); \
2098 return; \
2099 } \
2100 /* NIP cannot be restored if the memory exception comes from an helper */ \
2101 gen_update_nip(ctx, ctx->nip - 4); \
2102 gen_reset_fpstatus(); \
2103 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2104 cpu_fpr[rB(ctx->opcode)]); \
2105 if (isfloat) { \
2106 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2107 } \
2108 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2109 set_fprf, Rc(ctx->opcode) != 0); \
2110 }
2111 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2112 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2113 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2114
2115 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2116 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2117 { \
2118 if (unlikely(!ctx->fpu_enabled)) { \
2119 gen_exception(ctx, POWERPC_EXCP_FPU); \
2120 return; \
2121 } \
2122 /* NIP cannot be restored if the memory exception comes from an helper */ \
2123 gen_update_nip(ctx, ctx->nip - 4); \
2124 gen_reset_fpstatus(); \
2125 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2126 cpu_fpr[rC(ctx->opcode)]); \
2127 if (isfloat) { \
2128 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2129 } \
2130 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2131 set_fprf, Rc(ctx->opcode) != 0); \
2132 }
2133 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2134 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2135 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2136
2137 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2138 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2139 { \
2140 if (unlikely(!ctx->fpu_enabled)) { \
2141 gen_exception(ctx, POWERPC_EXCP_FPU); \
2142 return; \
2143 } \
2144 /* NIP cannot be restored if the memory exception comes from an helper */ \
2145 gen_update_nip(ctx, ctx->nip - 4); \
2146 gen_reset_fpstatus(); \
2147 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2148 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2149 set_fprf, Rc(ctx->opcode) != 0); \
2150 }
2151
2152 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2153 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2154 { \
2155 if (unlikely(!ctx->fpu_enabled)) { \
2156 gen_exception(ctx, POWERPC_EXCP_FPU); \
2157 return; \
2158 } \
2159 /* NIP cannot be restored if the memory exception comes from an helper */ \
2160 gen_update_nip(ctx, ctx->nip - 4); \
2161 gen_reset_fpstatus(); \
2162 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2163 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2164 set_fprf, Rc(ctx->opcode) != 0); \
2165 }
2166
2167 /* fadd - fadds */
2168 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2169 /* fdiv - fdivs */
2170 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2171 /* fmul - fmuls */
2172 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2173
2174 /* fre */
2175 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2176
2177 /* fres */
2178 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2179
2180 /* frsqrte */
2181 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2182
2183 /* frsqrtes */
2184 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2185 {
2186 if (unlikely(!ctx->fpu_enabled)) {
2187 gen_exception(ctx, POWERPC_EXCP_FPU);
2188 return;
2189 }
2190 /* NIP cannot be restored if the memory exception comes from an helper */
2191 gen_update_nip(ctx, ctx->nip - 4);
2192 gen_reset_fpstatus();
2193 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2194 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2195 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2196 }
2197
2198 /* fsel */
2199 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2200 /* fsub - fsubs */
2201 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2202 /* Optional: */
2203 /* fsqrt */
2204 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2205 {
2206 if (unlikely(!ctx->fpu_enabled)) {
2207 gen_exception(ctx, POWERPC_EXCP_FPU);
2208 return;
2209 }
2210 /* NIP cannot be restored if the memory exception comes from an helper */
2211 gen_update_nip(ctx, ctx->nip - 4);
2212 gen_reset_fpstatus();
2213 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2214 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2215 }
2216
2217 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2218 {
2219 if (unlikely(!ctx->fpu_enabled)) {
2220 gen_exception(ctx, POWERPC_EXCP_FPU);
2221 return;
2222 }
2223 /* NIP cannot be restored if the memory exception comes from an helper */
2224 gen_update_nip(ctx, ctx->nip - 4);
2225 gen_reset_fpstatus();
2226 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2227 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2228 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2229 }
2230
2231 /*** Floating-Point multiply-and-add ***/
2232 /* fmadd - fmadds */
2233 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2234 /* fmsub - fmsubs */
2235 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2236 /* fnmadd - fnmadds */
2237 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2238 /* fnmsub - fnmsubs */
2239 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2240
2241 /*** Floating-Point round & convert ***/
2242 /* fctiw */
2243 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2244 /* fctiwz */
2245 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2246 /* frsp */
2247 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2248 #if defined(TARGET_PPC64)
2249 /* fcfid */
2250 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2251 /* fctid */
2252 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2253 /* fctidz */
2254 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2255 #endif
2256
2257 /* frin */
2258 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2259 /* friz */
2260 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2261 /* frip */
2262 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2263 /* frim */
2264 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2265
2266 /*** Floating-Point compare ***/
2267 /* fcmpo */
2268 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2269 {
2270 TCGv_i32 crf;
2271 if (unlikely(!ctx->fpu_enabled)) {
2272 gen_exception(ctx, POWERPC_EXCP_FPU);
2273 return;
2274 }
2275 /* NIP cannot be restored if the memory exception comes from an helper */
2276 gen_update_nip(ctx, ctx->nip - 4);
2277 gen_reset_fpstatus();
2278 crf = tcg_const_i32(crfD(ctx->opcode));
2279 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2280 tcg_temp_free_i32(crf);
2281 gen_helper_float_check_status();
2282 }
2283
2284 /* fcmpu */
2285 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2286 {
2287 TCGv_i32 crf;
2288 if (unlikely(!ctx->fpu_enabled)) {
2289 gen_exception(ctx, POWERPC_EXCP_FPU);
2290 return;
2291 }
2292 /* NIP cannot be restored if the memory exception comes from an helper */
2293 gen_update_nip(ctx, ctx->nip - 4);
2294 gen_reset_fpstatus();
2295 crf = tcg_const_i32(crfD(ctx->opcode));
2296 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2297 tcg_temp_free_i32(crf);
2298 gen_helper_float_check_status();
2299 }
2300
2301 /*** Floating-point move ***/
2302 /* fabs */
2303 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2304 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2305
2306 /* fmr - fmr. */
2307 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2308 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2309 {
2310 if (unlikely(!ctx->fpu_enabled)) {
2311 gen_exception(ctx, POWERPC_EXCP_FPU);
2312 return;
2313 }
2314 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2315 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2316 }
2317
2318 /* fnabs */
2319 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2320 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2321 /* fneg */
2322 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2323 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2324
2325 /*** Floating-Point status & ctrl register ***/
2326 /* mcrfs */
2327 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2328 {
2329 int bfa;
2330
2331 if (unlikely(!ctx->fpu_enabled)) {
2332 gen_exception(ctx, POWERPC_EXCP_FPU);
2333 return;
2334 }
2335 bfa = 4 * (7 - crfS(ctx->opcode));
2336 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2337 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2338 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2339 }
2340
2341 /* mffs */
2342 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2343 {
2344 if (unlikely(!ctx->fpu_enabled)) {
2345 gen_exception(ctx, POWERPC_EXCP_FPU);
2346 return;
2347 }
2348 gen_reset_fpstatus();
2349 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2350 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2351 }
2352
2353 /* mtfsb0 */
2354 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2355 {
2356 uint8_t crb;
2357
2358 if (unlikely(!ctx->fpu_enabled)) {
2359 gen_exception(ctx, POWERPC_EXCP_FPU);
2360 return;
2361 }
2362 crb = 31 - crbD(ctx->opcode);
2363 gen_reset_fpstatus();
2364 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2365 TCGv_i32 t0;
2366 /* NIP cannot be restored if the memory exception comes from an helper */
2367 gen_update_nip(ctx, ctx->nip - 4);
2368 t0 = tcg_const_i32(crb);
2369 gen_helper_fpscr_clrbit(t0);
2370 tcg_temp_free_i32(t0);
2371 }
2372 if (unlikely(Rc(ctx->opcode) != 0)) {
2373 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2374 }
2375 }
2376
2377 /* mtfsb1 */
2378 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2379 {
2380 uint8_t crb;
2381
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 crb = 31 - crbD(ctx->opcode);
2387 gen_reset_fpstatus();
2388 /* XXX: we pretend we can only do IEEE floating-point computations */
2389 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2390 TCGv_i32 t0;
2391 /* NIP cannot be restored if the memory exception comes from an helper */
2392 gen_update_nip(ctx, ctx->nip - 4);
2393 t0 = tcg_const_i32(crb);
2394 gen_helper_fpscr_setbit(t0);
2395 tcg_temp_free_i32(t0);
2396 }
2397 if (unlikely(Rc(ctx->opcode) != 0)) {
2398 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2399 }
2400 /* We can raise a differed exception */
2401 gen_helper_float_check_status();
2402 }
2403
2404 /* mtfsf */
2405 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2406 {
2407 TCGv_i32 t0;
2408
2409 if (unlikely(!ctx->fpu_enabled)) {
2410 gen_exception(ctx, POWERPC_EXCP_FPU);
2411 return;
2412 }
2413 /* NIP cannot be restored if the memory exception comes from an helper */
2414 gen_update_nip(ctx, ctx->nip - 4);
2415 gen_reset_fpstatus();
2416 t0 = tcg_const_i32(FM(ctx->opcode));
2417 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2418 tcg_temp_free_i32(t0);
2419 if (unlikely(Rc(ctx->opcode) != 0)) {
2420 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2421 }
2422 /* We can raise a differed exception */
2423 gen_helper_float_check_status();
2424 }
2425
2426 /* mtfsfi */
2427 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2428 {
2429 int bf, sh;
2430 TCGv_i64 t0;
2431 TCGv_i32 t1;
2432
2433 if (unlikely(!ctx->fpu_enabled)) {
2434 gen_exception(ctx, POWERPC_EXCP_FPU);
2435 return;
2436 }
2437 bf = crbD(ctx->opcode) >> 2;
2438 sh = 7 - bf;
2439 /* NIP cannot be restored if the memory exception comes from an helper */
2440 gen_update_nip(ctx, ctx->nip - 4);
2441 gen_reset_fpstatus();
2442 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2443 t1 = tcg_const_i32(1 << sh);
2444 gen_helper_store_fpscr(t0, t1);
2445 tcg_temp_free_i64(t0);
2446 tcg_temp_free_i32(t1);
2447 if (unlikely(Rc(ctx->opcode) != 0)) {
2448 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2449 }
2450 /* We can raise a differed exception */
2451 gen_helper_float_check_status();
2452 }
2453
2454 /*** Addressing modes ***/
2455 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2456 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2457 {
2458 target_long simm = SIMM(ctx->opcode);
2459
2460 simm &= ~maskl;
2461 if (rA(ctx->opcode) == 0) {
2462 #if defined(TARGET_PPC64)
2463 if (!ctx->sf_mode) {
2464 tcg_gen_movi_tl(EA, (uint32_t)simm);
2465 } else
2466 #endif
2467 tcg_gen_movi_tl(EA, simm);
2468 } else if (likely(simm != 0)) {
2469 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2470 #if defined(TARGET_PPC64)
2471 if (!ctx->sf_mode) {
2472 tcg_gen_ext32u_tl(EA, EA);
2473 }
2474 #endif
2475 } else {
2476 #if defined(TARGET_PPC64)
2477 if (!ctx->sf_mode) {
2478 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2479 } else
2480 #endif
2481 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2482 }
2483 }
2484
2485 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2486 {
2487 if (rA(ctx->opcode) == 0) {
2488 #if defined(TARGET_PPC64)
2489 if (!ctx->sf_mode) {
2490 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2491 } else
2492 #endif
2493 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2494 } else {
2495 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2496 #if defined(TARGET_PPC64)
2497 if (!ctx->sf_mode) {
2498 tcg_gen_ext32u_tl(EA, EA);
2499 }
2500 #endif
2501 }
2502 }
2503
2504 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2505 {
2506 if (rA(ctx->opcode) == 0) {
2507 tcg_gen_movi_tl(EA, 0);
2508 } else {
2509 #if defined(TARGET_PPC64)
2510 if (!ctx->sf_mode) {
2511 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2512 } else
2513 #endif
2514 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2515 }
2516 }
2517
2518 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2519 {
2520 tcg_gen_addi_tl(ret, arg1, val);
2521 #if defined(TARGET_PPC64)
2522 if (!ctx->sf_mode) {
2523 tcg_gen_ext32u_tl(ret, ret);
2524 }
2525 #endif
2526 }
2527
2528 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2529 {
2530 int l1 = gen_new_label();
2531 TCGv t0 = tcg_temp_new();
2532 TCGv_i32 t1, t2;
2533 /* NIP cannot be restored if the memory exception comes from an helper */
2534 gen_update_nip(ctx, ctx->nip - 4);
2535 tcg_gen_andi_tl(t0, EA, mask);
2536 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2537 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2538 t2 = tcg_const_i32(0);
2539 gen_helper_raise_exception_err(t1, t2);
2540 tcg_temp_free_i32(t1);
2541 tcg_temp_free_i32(t2);
2542 gen_set_label(l1);
2543 tcg_temp_free(t0);
2544 }
2545
2546 /*** Integer load ***/
2547 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2548 {
2549 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2550 }
2551
2552 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2553 {
2554 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2555 }
2556
2557 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2558 {
2559 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2560 if (unlikely(ctx->le_mode)) {
2561 #if defined(TARGET_PPC64)
2562 TCGv_i32 t0 = tcg_temp_new_i32();
2563 tcg_gen_trunc_tl_i32(t0, arg1);
2564 tcg_gen_bswap16_i32(t0, t0);
2565 tcg_gen_extu_i32_tl(arg1, t0);
2566 tcg_temp_free_i32(t0);
2567 #else
2568 tcg_gen_bswap16_i32(arg1, arg1);
2569 #endif
2570 }
2571 }
2572
2573 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2574 {
2575 if (unlikely(ctx->le_mode)) {
2576 #if defined(TARGET_PPC64)
2577 TCGv_i32 t0;
2578 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2579 t0 = tcg_temp_new_i32();
2580 tcg_gen_trunc_tl_i32(t0, arg1);
2581 tcg_gen_bswap16_i32(t0, t0);
2582 tcg_gen_extu_i32_tl(arg1, t0);
2583 tcg_gen_ext16s_tl(arg1, arg1);
2584 tcg_temp_free_i32(t0);
2585 #else
2586 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2587 tcg_gen_bswap16_i32(arg1, arg1);
2588 tcg_gen_ext16s_i32(arg1, arg1);
2589 #endif
2590 } else {
2591 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2592 }
2593 }
2594
2595 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2596 {
2597 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2598 if (unlikely(ctx->le_mode)) {
2599 #if defined(TARGET_PPC64)
2600 TCGv_i32 t0 = tcg_temp_new_i32();
2601 tcg_gen_trunc_tl_i32(t0, arg1);
2602 tcg_gen_bswap_i32(t0, t0);
2603 tcg_gen_extu_i32_tl(arg1, t0);
2604 tcg_temp_free_i32(t0);
2605 #else
2606 tcg_gen_bswap_i32(arg1, arg1);
2607 #endif
2608 }
2609 }
2610
2611 #if defined(TARGET_PPC64)
2612 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2613 {
2614 if (unlikely(ctx->mem_idx)) {
2615 TCGv_i32 t0;
2616 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2617 t0 = tcg_temp_new_i32();
2618 tcg_gen_trunc_tl_i32(t0, arg1);
2619 tcg_gen_bswap_i32(t0, t0);
2620 tcg_gen_ext_i32_tl(arg1, t0);
2621 tcg_temp_free_i32(t0);
2622 } else
2623 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2624 }
2625 #endif
2626
2627 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2628 {
2629 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2630 if (unlikely(ctx->le_mode)) {
2631 tcg_gen_bswap_i64(arg1, arg1);
2632 }
2633 }
2634
2635 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2636 {
2637 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2638 }
2639
2640 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2641 {
2642 if (unlikely(ctx->le_mode)) {
2643 #if defined(TARGET_PPC64)
2644 TCGv_i32 t0;
2645 TCGv t1;
2646 t0 = tcg_temp_new_i32();
2647 tcg_gen_trunc_tl_i32(t0, arg1);
2648 tcg_gen_ext16u_i32(t0, t0);
2649 tcg_gen_bswap16_i32(t0, t0);
2650 t1 = tcg_temp_new();
2651 tcg_gen_extu_i32_tl(t1, t0);
2652 tcg_temp_free_i32(t0);
2653 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2654 tcg_temp_free(t1);
2655 #else
2656 TCGv t0 = tcg_temp_new();
2657 tcg_gen_ext16u_tl(t0, arg1);
2658 tcg_gen_bswap16_i32(t0, t0);
2659 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2660 tcg_temp_free(t0);
2661 #endif
2662 } else {
2663 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2664 }
2665 }
2666
2667 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2668 {
2669 if (unlikely(ctx->le_mode)) {
2670 #if defined(TARGET_PPC64)
2671 TCGv_i32 t0;
2672 TCGv t1;
2673 t0 = tcg_temp_new_i32();
2674 tcg_gen_trunc_tl_i32(t0, arg1);
2675 tcg_gen_bswap_i32(t0, t0);
2676 t1 = tcg_temp_new();
2677 tcg_gen_extu_i32_tl(t1, t0);
2678 tcg_temp_free_i32(t0);
2679 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2680 tcg_temp_free(t1);
2681 #else
2682 TCGv t0 = tcg_temp_new_i32();
2683 tcg_gen_bswap_i32(t0, arg1);
2684 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2685 tcg_temp_free(t0);
2686 #endif
2687 } else {
2688 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2689 }
2690 }
2691
2692 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2693 {
2694 if (unlikely(ctx->le_mode)) {
2695 TCGv_i64 t0 = tcg_temp_new_i64();
2696 tcg_gen_bswap_i64(t0, arg1);
2697 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2698 tcg_temp_free_i64(t0);
2699 } else
2700 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2701 }
2702
2703 #define GEN_LD(name, ldop, opc, type) \
2704 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2705 { \
2706 TCGv EA; \
2707 gen_set_access_type(ctx, ACCESS_INT); \
2708 EA = tcg_temp_new(); \
2709 gen_addr_imm_index(ctx, EA, 0); \
2710 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2711 tcg_temp_free(EA); \
2712 }
2713
2714 #define GEN_LDU(name, ldop, opc, type) \
2715 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2716 { \
2717 TCGv EA; \
2718 if (unlikely(rA(ctx->opcode) == 0 || \
2719 rA(ctx->opcode) == rD(ctx->opcode))) { \
2720 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2721 return; \
2722 } \
2723 gen_set_access_type(ctx, ACCESS_INT); \
2724 EA = tcg_temp_new(); \
2725 if (type == PPC_64B) \
2726 gen_addr_imm_index(ctx, EA, 0x03); \
2727 else \
2728 gen_addr_imm_index(ctx, EA, 0); \
2729 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2730 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2731 tcg_temp_free(EA); \
2732 }
2733
2734 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2735 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2736 { \
2737 TCGv EA; \
2738 if (unlikely(rA(ctx->opcode) == 0 || \
2739 rA(ctx->opcode) == rD(ctx->opcode))) { \
2740 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2741 return; \
2742 } \
2743 gen_set_access_type(ctx, ACCESS_INT); \
2744 EA = tcg_temp_new(); \
2745 gen_addr_reg_index(ctx, EA); \
2746 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2747 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2748 tcg_temp_free(EA); \
2749 }
2750
2751 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2752 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2753 { \
2754 TCGv EA; \
2755 gen_set_access_type(ctx, ACCESS_INT); \
2756 EA = tcg_temp_new(); \
2757 gen_addr_reg_index(ctx, EA); \
2758 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2759 tcg_temp_free(EA); \
2760 }
2761
2762 #define GEN_LDS(name, ldop, op, type) \
2763 GEN_LD(name, ldop, op | 0x20, type); \
2764 GEN_LDU(name, ldop, op | 0x21, type); \
2765 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2766 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2767
2768 /* lbz lbzu lbzux lbzx */
2769 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2770 /* lha lhau lhaux lhax */
2771 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2772 /* lhz lhzu lhzux lhzx */
2773 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2774 /* lwz lwzu lwzux lwzx */
2775 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2776 #if defined(TARGET_PPC64)
2777 /* lwaux */
2778 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2779 /* lwax */
2780 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2781 /* ldux */
2782 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2783 /* ldx */
2784 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2785 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2786 {
2787 TCGv EA;
2788 if (Rc(ctx->opcode)) {
2789 if (unlikely(rA(ctx->opcode) == 0 ||
2790 rA(ctx->opcode) == rD(ctx->opcode))) {
2791 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2792 return;
2793 }
2794 }
2795 gen_set_access_type(ctx, ACCESS_INT);
2796 EA = tcg_temp_new();
2797 gen_addr_imm_index(ctx, EA, 0x03);
2798 if (ctx->opcode & 0x02) {
2799 /* lwa (lwau is undefined) */
2800 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2801 } else {
2802 /* ld - ldu */
2803 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2804 }
2805 if (Rc(ctx->opcode))
2806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2807 tcg_temp_free(EA);
2808 }
2809 /* lq */
2810 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2811 {
2812 #if defined(CONFIG_USER_ONLY)
2813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2814 #else
2815 int ra, rd;
2816 TCGv EA;
2817
2818 /* Restore CPU state */
2819 if (unlikely(ctx->mem_idx == 0)) {
2820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2821 return;
2822 }
2823 ra = rA(ctx->opcode);
2824 rd = rD(ctx->opcode);
2825 if (unlikely((rd & 1) || rd == ra)) {
2826 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2827 return;
2828 }
2829 if (unlikely(ctx->le_mode)) {
2830 /* Little-endian mode is not handled */
2831 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2832 return;
2833 }
2834 gen_set_access_type(ctx, ACCESS_INT);
2835 EA = tcg_temp_new();
2836 gen_addr_imm_index(ctx, EA, 0x0F);
2837 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2838 gen_addr_add(ctx, EA, EA, 8);
2839 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2840 tcg_temp_free(EA);
2841 #endif
2842 }
2843 #endif
2844
2845 /*** Integer store ***/
2846 #define GEN_ST(name, stop, opc, type) \
2847 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2848 { \
2849 TCGv EA; \
2850 gen_set_access_type(ctx, ACCESS_INT); \
2851 EA = tcg_temp_new(); \
2852 gen_addr_imm_index(ctx, EA, 0); \
2853 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2854 tcg_temp_free(EA); \
2855 }
2856
2857 #define GEN_STU(name, stop, opc, type) \
2858 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2859 { \
2860 TCGv EA; \
2861 if (unlikely(rA(ctx->opcode) == 0)) { \
2862 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2863 return; \
2864 } \
2865 gen_set_access_type(ctx, ACCESS_INT); \
2866 EA = tcg_temp_new(); \
2867 if (type == PPC_64B) \
2868 gen_addr_imm_index(ctx, EA, 0x03); \
2869 else \
2870 gen_addr_imm_index(ctx, EA, 0); \
2871 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2872 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2873 tcg_temp_free(EA); \
2874 }
2875
2876 #define GEN_STUX(name, stop, opc2, opc3, type) \
2877 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2878 { \
2879 TCGv EA; \
2880 if (unlikely(rA(ctx->opcode) == 0)) { \
2881 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2882 return; \
2883 } \
2884 gen_set_access_type(ctx, ACCESS_INT); \
2885 EA = tcg_temp_new(); \
2886 gen_addr_reg_index(ctx, EA); \
2887 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2888 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2889 tcg_temp_free(EA); \
2890 }
2891
2892 #define GEN_STX(name, stop, opc2, opc3, type) \
2893 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2894 { \
2895 TCGv EA; \
2896 gen_set_access_type(ctx, ACCESS_INT); \
2897 EA = tcg_temp_new(); \
2898 gen_addr_reg_index(ctx, EA); \
2899 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2900 tcg_temp_free(EA); \
2901 }
2902
2903 #define GEN_STS(name, stop, op, type) \
2904 GEN_ST(name, stop, op | 0x20, type); \
2905 GEN_STU(name, stop, op | 0x21, type); \
2906 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2907 GEN_STX(name, stop, 0x17, op | 0x00, type)
2908
2909 /* stb stbu stbux stbx */
2910 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2911 /* sth sthu sthux sthx */
2912 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2913 /* stw stwu stwux stwx */
2914 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2915 #if defined(TARGET_PPC64)
2916 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2917 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2918 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2919 {
2920 int rs;
2921 TCGv EA;
2922
2923 rs = rS(ctx->opcode);
2924 if ((ctx->opcode & 0x3) == 0x2) {
2925 #if defined(CONFIG_USER_ONLY)
2926 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2927 #else
2928 /* stq */
2929 if (unlikely(ctx->mem_idx == 0)) {
2930 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2931 return;
2932 }
2933 if (unlikely(rs & 1)) {
2934 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2935 return;
2936 }
2937 if (unlikely(ctx->le_mode)) {
2938 /* Little-endian mode is not handled */
2939 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2940 return;
2941 }
2942 gen_set_access_type(ctx, ACCESS_INT);
2943 EA = tcg_temp_new();
2944 gen_addr_imm_index(ctx, EA, 0x03);
2945 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2946 gen_addr_add(ctx, EA, EA, 8);
2947 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2948 tcg_temp_free(EA);
2949 #endif
2950 } else {
2951 /* std / stdu */
2952 if (Rc(ctx->opcode)) {
2953 if (unlikely(rA(ctx->opcode) == 0)) {
2954 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2955 return;
2956 }
2957 }
2958 gen_set_access_type(ctx, ACCESS_INT);
2959 EA = tcg_temp_new();
2960 gen_addr_imm_index(ctx, EA, 0x03);
2961 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2962 if (Rc(ctx->opcode))
2963 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2964 tcg_temp_free(EA);
2965 }
2966 }
2967 #endif
2968 /*** Integer load and store with byte reverse ***/
2969 /* lhbrx */
2970 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2971 {
2972 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2973 if (likely(!ctx->le_mode)) {
2974 #if defined(TARGET_PPC64)
2975 TCGv_i32 t0 = tcg_temp_new_i32();
2976 tcg_gen_trunc_tl_i32(t0, arg1);
2977 tcg_gen_bswap16_i32(t0, t0);
2978 tcg_gen_extu_i32_tl(arg1, t0);
2979 tcg_temp_free_i32(t0);
2980 #else
2981 tcg_gen_bswap16_i32(arg1, arg1);
2982 #endif
2983 }
2984 }
2985 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2986
2987 /* lwbrx */
2988 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2989 {
2990 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2991 if (likely(!ctx->le_mode)) {
2992 #if defined(TARGET_PPC64)
2993 TCGv_i32 t0 = tcg_temp_new_i32();
2994 tcg_gen_trunc_tl_i32(t0, arg1);
2995 tcg_gen_bswap_i32(t0, t0);
2996 tcg_gen_extu_i32_tl(arg1, t0);
2997 tcg_temp_free_i32(t0);
2998 #else
2999 tcg_gen_bswap_i32(arg1, arg1);
3000 #endif
3001 }
3002 }
3003 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3004
3005 /* sthbrx */
3006 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3007 {
3008 if (likely(!ctx->le_mode)) {
3009 #if defined(TARGET_PPC64)
3010 TCGv_i32 t0;
3011 TCGv t1;
3012 t0 = tcg_temp_new_i32();
3013 tcg_gen_trunc_tl_i32(t0, arg1);
3014 tcg_gen_ext16u_i32(t0, t0);
3015 tcg_gen_bswap16_i32(t0, t0);
3016 t1 = tcg_temp_new();
3017 tcg_gen_extu_i32_tl(t1, t0);
3018 tcg_temp_free_i32(t0);
3019 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3020 tcg_temp_free(t1);
3021 #else
3022 TCGv t0 = tcg_temp_new();
3023 tcg_gen_ext16u_tl(t0, arg1);
3024 tcg_gen_bswap16_i32(t0, t0);
3025 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3026 tcg_temp_free(t0);
3027 #endif
3028 } else {
3029 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3030 }
3031 }
3032 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3033
3034 /* stwbrx */
3035 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3036 {
3037 if (likely(!ctx->le_mode)) {
3038 #if defined(TARGET_PPC64)
3039 TCGv_i32 t0;
3040 TCGv t1;
3041 t0 = tcg_temp_new_i32();
3042 tcg_gen_trunc_tl_i32(t0, arg1);
3043 tcg_gen_bswap_i32(t0, t0);
3044 t1 = tcg_temp_new();
3045 tcg_gen_extu_i32_tl(t1, t0);
3046 tcg_temp_free_i32(t0);
3047 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3048 tcg_temp_free(t1);
3049 #else
3050 TCGv t0 = tcg_temp_new_i32();
3051 tcg_gen_bswap_i32(t0, arg1);
3052 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3053 tcg_temp_free(t0);
3054 #endif
3055 } else {
3056 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3057 }
3058 }
3059 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3060
3061 /*** Integer load and store multiple ***/
3062 /* lmw */
3063 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3064 {
3065 TCGv t0;
3066 TCGv_i32 t1;
3067 gen_set_access_type(ctx, ACCESS_INT);
3068 /* NIP cannot be restored if the memory exception comes from an helper */
3069 gen_update_nip(ctx, ctx->nip - 4);
3070 t0 = tcg_temp_new();
3071 t1 = tcg_const_i32(rD(ctx->opcode));
3072 gen_addr_imm_index(ctx, t0, 0);
3073 gen_helper_lmw(t0, t1);
3074 tcg_temp_free(t0);
3075 tcg_temp_free_i32(t1);
3076 }
3077
3078 /* stmw */
3079 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3080 {
3081 TCGv t0;
3082 TCGv_i32 t1;
3083 gen_set_access_type(ctx, ACCESS_INT);
3084 /* NIP cannot be restored if the memory exception comes from an helper */
3085 gen_update_nip(ctx, ctx->nip - 4);
3086 t0 = tcg_temp_new();
3087 t1 = tcg_const_i32(rS(ctx->opcode));
3088 gen_addr_imm_index(ctx, t0, 0);
3089 gen_helper_stmw(t0, t1);
3090 tcg_temp_free(t0);
3091 tcg_temp_free_i32(t1);
3092 }
3093
3094 /*** Integer load and store strings ***/
3095 /* lswi */
3096 /* PowerPC32 specification says we must generate an exception if
3097 * rA is in the range of registers to be loaded.
3098 * In an other hand, IBM says this is valid, but rA won't be loaded.
3099 * For now, I'll follow the spec...
3100 */
3101 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3102 {
3103 TCGv t0;
3104 TCGv_i32 t1, t2;
3105 int nb = NB(ctx->opcode);
3106 int start = rD(ctx->opcode);
3107 int ra = rA(ctx->opcode);
3108 int nr;
3109
3110 if (nb == 0)
3111 nb = 32;
3112 nr = nb / 4;
3113 if (unlikely(((start + nr) > 32 &&
3114 start <= ra && (start + nr - 32) > ra) ||
3115 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3116 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3117 return;
3118 }
3119 gen_set_access_type(ctx, ACCESS_INT);
3120 /* NIP cannot be restored if the memory exception comes from an helper */
3121 gen_update_nip(ctx, ctx->nip - 4);
3122 t0 = tcg_temp_new();
3123 gen_addr_register(ctx, t0);
3124 t1 = tcg_const_i32(nb);
3125 t2 = tcg_const_i32(start);
3126 gen_helper_lsw(t0, t1, t2);
3127 tcg_temp_free(t0);
3128 tcg_temp_free_i32(t1);
3129 tcg_temp_free_i32(t2);
3130 }
3131
3132 /* lswx */
3133 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3134 {
3135 TCGv t0;
3136 TCGv_i32 t1, t2, t3;
3137 gen_set_access_type(ctx, ACCESS_INT);
3138 /* NIP cannot be restored if the memory exception comes from an helper */
3139 gen_update_nip(ctx, ctx->nip - 4);
3140 t0 = tcg_temp_new();
3141 gen_addr_reg_index(ctx, t0);
3142 t1 = tcg_const_i32(rD(ctx->opcode));
3143 t2 = tcg_const_i32(rA(ctx->opcode));
3144 t3 = tcg_const_i32(rB(ctx->opcode));
3145 gen_helper_lswx(t0, t1, t2, t3);
3146 tcg_temp_free(t0);
3147 tcg_temp_free_i32(t1);
3148 tcg_temp_free_i32(t2);
3149 tcg_temp_free_i32(t3);
3150 }
3151
3152 /* stswi */
3153 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3154 {
3155 TCGv t0;
3156 TCGv_i32 t1, t2;
3157 int nb = NB(ctx->opcode);
3158 gen_set_access_type(ctx, ACCESS_INT);
3159 /* NIP cannot be restored if the memory exception comes from an helper */
3160 gen_update_nip(ctx, ctx->nip - 4);
3161 t0 = tcg_temp_new();
3162 gen_addr_register(ctx, t0);
3163 if (nb == 0)
3164 nb = 32;
3165 t1 = tcg_const_i32(nb);
3166 t2 = tcg_const_i32(rS(ctx->opcode));
3167 gen_helper_stsw(t0, t1, t2);
3168 tcg_temp_free(t0);
3169 tcg_temp_free_i32(t1);
3170 tcg_temp_free_i32(t2);
3171 }
3172
3173 /* stswx */
3174 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3175 {
3176 TCGv t0;
3177 TCGv_i32 t1, t2;
3178 gen_set_access_type(ctx, ACCESS_INT);
3179 /* NIP cannot be restored if the memory exception comes from an helper */
3180 gen_update_nip(ctx, ctx->nip - 4);
3181 t0 = tcg_temp_new();
3182 gen_addr_reg_index(ctx, t0);
3183 t1 = tcg_temp_new_i32();
3184 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3185 tcg_gen_andi_i32(t1, t1, 0x7F);
3186 t2 = tcg_const_i32(rS(ctx->opcode));
3187 gen_helper_stsw(t0, t1, t2);
3188 tcg_temp_free(t0);
3189 tcg_temp_free_i32(t1);
3190 tcg_temp_free_i32(t2);
3191 }
3192
3193 /*** Memory synchronisation ***/
3194 /* eieio */
3195 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3196 {
3197 }
3198
3199 /* isync */
3200 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3201 {
3202 gen_stop_exception(ctx);
3203 }
3204
3205 /* lwarx */
3206 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3207 {
3208 TCGv t0;
3209 gen_set_access_type(ctx, ACCESS_RES);
3210 t0 = tcg_temp_local_new();
3211 gen_addr_reg_index(ctx, t0);
3212 gen_check_align(ctx, t0, 0x03);
3213 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3214 tcg_gen_mov_tl(cpu_reserve, t0);
3215 tcg_temp_free(t0);
3216 }
3217
3218 /* stwcx. */
3219 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3220 {
3221 int l1;
3222 TCGv t0;
3223 gen_set_access_type(ctx, ACCESS_RES);
3224 t0 = tcg_temp_local_new();
3225 gen_addr_reg_index(ctx, t0);
3226 gen_check_align(ctx, t0, 0x03);
3227 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3228 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3229 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3230 l1 = gen_new_label();
3231 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3232 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3233 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3234 gen_set_label(l1);
3235 tcg_gen_movi_tl(cpu_reserve, -1);
3236 tcg_temp_free(t0);
3237 }
3238
3239 #if defined(TARGET_PPC64)
3240 /* ldarx */
3241 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3242 {
3243 TCGv t0;
3244 gen_set_access_type(ctx, ACCESS_RES);
3245 t0 = tcg_temp_local_new();
3246 gen_addr_reg_index(ctx, t0);
3247 gen_check_align(ctx, t0, 0x07);
3248 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3249 tcg_gen_mov_tl(cpu_reserve, t0);
3250 tcg_temp_free(t0);
3251 }
3252
3253 /* stdcx. */
3254 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3255 {
3256 int l1;
3257 TCGv t0;
3258 gen_set_access_type(ctx, ACCESS_RES);
3259 t0 = tcg_temp_local_new();
3260 gen_addr_reg_index(ctx, t0);
3261 gen_check_align(ctx, t0, 0x07);
3262 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3263 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3264 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3265 l1 = gen_new_label();
3266 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3267 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3268 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3269 gen_set_label(l1);
3270 tcg_gen_movi_tl(cpu_reserve, -1);
3271 tcg_temp_free(t0);
3272 }
3273 #endif /* defined(TARGET_PPC64) */
3274
3275 /* sync */
3276 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3277 {
3278 }
3279
3280 /* wait */
3281 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3282 {
3283 TCGv_i32 t0 = tcg_temp_new_i32();
3284 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3285 tcg_temp_free_i32(t0);
3286 /* Stop translation, as the CPU is supposed to sleep from now */
3287 gen_exception_err(ctx, EXCP_HLT, 1);
3288 }
3289
3290 /*** Floating-point load ***/
3291 #define GEN_LDF(name, ldop, opc, type) \
3292 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3293 { \
3294 TCGv EA; \
3295 if (unlikely(!ctx->fpu_enabled)) { \
3296 gen_exception(ctx, POWERPC_EXCP_FPU); \
3297 return; \
3298 } \
3299 gen_set_access_type(ctx, ACCESS_FLOAT); \
3300 EA = tcg_temp_new(); \
3301 gen_addr_imm_index(ctx, EA, 0); \
3302 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3303 tcg_temp_free(EA); \
3304 }
3305
3306 #define GEN_LDUF(name, ldop, opc, type) \
3307 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3308 { \
3309 TCGv EA; \
3310 if (unlikely(!ctx->fpu_enabled)) { \
3311 gen_exception(ctx, POWERPC_EXCP_FPU); \
3312 return; \
3313 } \
3314 if (unlikely(rA(ctx->opcode) == 0)) { \
3315 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3316 return; \
3317 } \
3318 gen_set_access_type(ctx, ACCESS_FLOAT); \
3319 EA = tcg_temp_new(); \
3320 gen_addr_imm_index(ctx, EA, 0); \
3321 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3322 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3323 tcg_temp_free(EA); \
3324 }
3325
3326 #define GEN_LDUXF(name, ldop, opc, type) \
3327 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3328 { \
3329 TCGv EA; \
3330 if (unlikely(!ctx->fpu_enabled)) { \
3331 gen_exception(ctx, POWERPC_EXCP_FPU); \
3332 return; \
3333 } \
3334 if (unlikely(rA(ctx->opcode) == 0)) { \
3335 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3336 return; \
3337 } \
3338 gen_set_access_type(ctx, ACCESS_FLOAT); \
3339 EA = tcg_temp_new(); \
3340 gen_addr_reg_index(ctx, EA); \
3341 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3342 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3343 tcg_temp_free(EA); \
3344 }
3345
3346 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3347 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3348 { \
3349 TCGv EA; \
3350 if (unlikely(!ctx->fpu_enabled)) { \
3351 gen_exception(ctx, POWERPC_EXCP_FPU); \
3352 return; \
3353 } \
3354 gen_set_access_type(ctx, ACCESS_FLOAT); \
3355 EA = tcg_temp_new(); \
3356 gen_addr_reg_index(ctx, EA); \
3357 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3358 tcg_temp_free(EA); \
3359 }
3360
3361 #define GEN_LDFS(name, ldop, op, type) \
3362 GEN_LDF(name, ldop, op | 0x20, type); \
3363 GEN_LDUF(name, ldop, op | 0x21, type); \
3364 GEN_LDUXF(name, ldop, op | 0x01, type); \
3365 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3366
3367 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3368 {
3369 TCGv t0 = tcg_temp_new();
3370 TCGv_i32 t1 = tcg_temp_new_i32();
3371 gen_qemu_ld32u(ctx, t0, arg2);
3372 tcg_gen_trunc_tl_i32(t1, t0);
3373 tcg_temp_free(t0);
3374 gen_helper_float32_to_float64(arg1, t1);
3375 tcg_temp_free_i32(t1);
3376 }
3377
3378 /* lfd lfdu lfdux lfdx */
3379 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3380 /* lfs lfsu lfsux lfsx */
3381 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3382
3383 /*** Floating-point store ***/
3384 #define GEN_STF(name, stop, opc, type) \
3385 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3386 { \
3387 TCGv EA; \
3388 if (unlikely(!ctx->fpu_enabled)) { \
3389 gen_exception(ctx, POWERPC_EXCP_FPU); \
3390 return; \
3391 } \
3392 gen_set_access_type(ctx, ACCESS_FLOAT); \
3393 EA = tcg_temp_new(); \
3394 gen_addr_imm_index(ctx, EA, 0); \
3395 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3396 tcg_temp_free(EA); \
3397 }
3398
3399 #define GEN_STUF(name, stop, opc, type) \
3400 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3401 { \
3402 TCGv EA; \
3403 if (unlikely(!ctx->fpu_enabled)) { \
3404 gen_exception(ctx, POWERPC_EXCP_FPU); \
3405 return; \
3406 } \
3407 if (unlikely(rA(ctx->opcode) == 0)) { \
3408 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3409 return; \
3410 } \
3411 gen_set_access_type(ctx, ACCESS_FLOAT); \
3412 EA = tcg_temp_new(); \
3413 gen_addr_imm_index(ctx, EA, 0); \
3414 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3415 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3416 tcg_temp_free(EA); \
3417 }
3418
3419 #define GEN_STUXF(name, stop, opc, type) \
3420 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3421 { \
3422 TCGv EA; \
3423 if (unlikely(!ctx->fpu_enabled)) { \
3424 gen_exception(ctx, POWERPC_EXCP_FPU); \
3425 return; \
3426 } \
3427 if (unlikely(rA(ctx->opcode) == 0)) { \
3428 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3429 return; \
3430 } \
3431 gen_set_access_type(ctx, ACCESS_FLOAT); \
3432 EA = tcg_temp_new(); \
3433 gen_addr_reg_index(ctx, EA); \
3434 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3435 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3436 tcg_temp_free(EA); \
3437 }
3438
3439 #define GEN_STXF(name, stop, opc2, opc3, type) \
3440 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3441 { \
3442 TCGv EA; \
3443 if (unlikely(!ctx->fpu_enabled)) { \
3444 gen_exception(ctx, POWERPC_EXCP_FPU); \
3445 return; \
3446 } \
3447 gen_set_access_type(ctx, ACCESS_FLOAT); \
3448 EA = tcg_temp_new(); \
3449 gen_addr_reg_index(ctx, EA); \
3450 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3451 tcg_temp_free(EA); \
3452 }
3453
3454 #define GEN_STFS(name, stop, op, type) \
3455 GEN_STF(name, stop, op | 0x20, type); \
3456 GEN_STUF(name, stop, op | 0x21, type); \
3457 GEN_STUXF(name, stop, op | 0x01, type); \
3458 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3459
3460 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3461 {
3462 TCGv_i32 t0 = tcg_temp_new_i32();
3463 TCGv t1 = tcg_temp_new();
3464 gen_helper_float64_to_float32(t0, arg1);
3465 tcg_gen_extu_i32_tl(t1, t0);
3466 tcg_temp_free_i32(t0);
3467 gen_qemu_st32(ctx, t1, arg2);
3468 tcg_temp_free(t1);
3469 }
3470
3471 /* stfd stfdu stfdux stfdx */
3472 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3473 /* stfs stfsu stfsux stfsx */
3474 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3475
3476 /* Optional: */
3477 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3478 {
3479 TCGv t0 = tcg_temp_new();
3480 tcg_gen_trunc_i64_tl(t0, arg1),
3481 gen_qemu_st32(ctx, t0, arg2);
3482 tcg_temp_free(t0);
3483 }
3484 /* stfiwx */
3485 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3486
3487 /*** Branch ***/
3488 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3489 target_ulong dest)
3490 {
3491 TranslationBlock *tb;
3492 tb = ctx->tb;
3493 #if defined(TARGET_PPC64)
3494 if (!ctx->sf_mode)
3495 dest = (uint32_t) dest;
3496 #endif
3497 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3498 likely(!ctx->singlestep_enabled)) {
3499 tcg_gen_goto_tb(n);
3500 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3501 tcg_gen_exit_tb((long)tb + n);
3502 } else {
3503 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3504 if (unlikely(ctx->singlestep_enabled)) {
3505 if ((ctx->singlestep_enabled &
3506 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3507 ctx->exception == POWERPC_EXCP_BRANCH) {
3508 target_ulong tmp = ctx->nip;
3509 ctx->nip = dest;
3510 gen_exception(ctx, POWERPC_EXCP_TRACE);
3511 ctx->nip = tmp;
3512 }
3513 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3514 gen_debug_exception(ctx);
3515 }
3516 }
3517 tcg_gen_exit_tb(0);
3518 }
3519 }
3520
3521 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3522 {
3523 #if defined(TARGET_PPC64)
3524 if (ctx->sf_mode == 0)
3525 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3526 else
3527 #endif
3528 tcg_gen_movi_tl(cpu_lr, nip);
3529 }
3530
3531 /* b ba bl bla */
3532 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3533 {
3534 target_ulong li, target;
3535
3536 ctx->exception = POWERPC_EXCP_BRANCH;
3537 /* sign extend LI */
3538 #if defined(TARGET_PPC64)
3539 if (ctx->sf_mode)
3540 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3541 else
3542 #endif
3543 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3544 if (likely(AA(ctx->opcode) == 0))
3545 target = ctx->nip + li - 4;
3546 else
3547 target = li;
3548 if (LK(ctx->opcode))
3549 gen_setlr(ctx, ctx->nip);
3550 gen_goto_tb(ctx, 0, target);
3551 }
3552
3553 #define BCOND_IM 0
3554 #define BCOND_LR 1
3555 #define BCOND_CTR 2
3556
3557 static always_inline void gen_bcond (DisasContext *ctx, int type)
3558 {
3559 uint32_t bo = BO(ctx->opcode);
3560 int l1 = gen_new_label();
3561 TCGv target;
3562
3563 ctx->exception = POWERPC_EXCP_BRANCH;
3564 if (type == BCOND_LR || type == BCOND_CTR) {
3565 target = tcg_temp_local_new();
3566 if (type == BCOND_CTR)
3567 tcg_gen_mov_tl(target, cpu_ctr);
3568 else
3569 tcg_gen_mov_tl(target, cpu_lr);
3570 }
3571 if (LK(ctx->opcode))
3572 gen_setlr(ctx, ctx->nip);
3573 l1 = gen_new_label();
3574 if ((bo & 0x4) == 0) {
3575 /* Decrement and test CTR */
3576 TCGv temp = tcg_temp_new();
3577 if (unlikely(type == BCOND_CTR)) {
3578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3579 return;
3580 }
3581 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3582 #if defined(TARGET_PPC64)
3583 if (!ctx->sf_mode)
3584 tcg_gen_ext32u_tl(temp, cpu_ctr);
3585 else
3586 #endif
3587 tcg_gen_mov_tl(temp, cpu_ctr);
3588 if (bo & 0x2) {
3589 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3590 } else {
3591 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3592 }
3593 tcg_temp_free(temp);
3594 }
3595 if ((bo & 0x10) == 0) {
3596 /* Test CR */
3597 uint32_t bi = BI(ctx->opcode);
3598 uint32_t mask = 1 << (3 - (bi & 0x03));
3599 TCGv_i32 temp = tcg_temp_new_i32();
3600
3601 if (bo & 0x8) {
3602 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3603 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3604 } else {
3605 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3606 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3607 }
3608 tcg_temp_free_i32(temp);
3609 }
3610 if (type == BCOND_IM) {
3611 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3612 if (likely(AA(ctx->opcode) == 0)) {
3613 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3614 } else {
3615 gen_goto_tb(ctx, 0, li);
3616 }
3617 gen_set_label(l1);
3618 gen_goto_tb(ctx, 1, ctx->nip);
3619 } else {
3620 #if defined(TARGET_PPC64)
3621 if (!(ctx->sf_mode))
3622 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3623 else
3624 #endif
3625 tcg_gen_andi_tl(cpu_nip, target, ~3);
3626 tcg_gen_exit_tb(0);
3627 gen_set_label(l1);
3628 #if defined(TARGET_PPC64)
3629 if (!(ctx->sf_mode))
3630 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3631 else
3632 #endif
3633 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3634 tcg_gen_exit_tb(0);
3635 }
3636 }
3637
3638 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3639 {
3640 gen_bcond(ctx, BCOND_IM);
3641 }
3642
3643 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3644 {
3645 gen_bcond(ctx, BCOND_CTR);
3646 }
3647
3648 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3649 {
3650 gen_bcond(ctx, BCOND_LR);
3651 }
3652
3653 /*** Condition register logical ***/
3654 #define GEN_CRLOGIC(name, tcg_op, opc) \
3655 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3656 { \
3657 uint8_t bitmask; \
3658 int sh; \
3659 TCGv_i32 t0, t1; \
3660 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3661 t0 = tcg_temp_new_i32(); \
3662 if (sh > 0) \
3663 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3664 else if (sh < 0) \
3665 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3666 else \
3667 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3668 t1 = tcg_temp_new_i32(); \
3669 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3670 if (sh > 0) \
3671 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3672 else if (sh < 0) \
3673 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3674 else \
3675 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3676 tcg_op(t0, t0, t1); \
3677 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3678 tcg_gen_andi_i32(t0, t0, bitmask); \
3679 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3680 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3681 tcg_temp_free_i32(t0); \
3682 tcg_temp_free_i32(t1); \
3683 }
3684
3685 /* crand */
3686 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3687 /* crandc */
3688 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3689 /* creqv */
3690 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3691 /* crnand */
3692 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3693 /* crnor */
3694 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3695 /* cror */
3696 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3697 /* crorc */
3698 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3699 /* crxor */
3700 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3701 /* mcrf */
3702 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3703 {
3704 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3705 }
3706
3707 /*** System linkage ***/
3708 /* rfi (mem_idx only) */
3709 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3710 {
3711 #if defined(CONFIG_USER_ONLY)
3712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3713 #else
3714 /* Restore CPU state */
3715 if (unlikely(!ctx->mem_idx)) {
3716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3717 return;
3718 }
3719 gen_helper_rfi();
3720 gen_sync_exception(ctx);
3721 #endif
3722 }
3723
3724 #if defined(TARGET_PPC64)
3725 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3726 {
3727 #if defined(CONFIG_USER_ONLY)
3728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3729 #else
3730 /* Restore CPU state */
3731 if (unlikely(!ctx->mem_idx)) {
3732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3733 return;
3734 }
3735 gen_helper_rfid();
3736 gen_sync_exception(ctx);
3737 #endif
3738 }
3739
3740 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3741 {
3742 #if defined(CONFIG_USER_ONLY)
3743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3744 #else
3745 /* Restore CPU state */
3746 if (unlikely(ctx->mem_idx <= 1)) {
3747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3748 return;
3749 }
3750 gen_helper_hrfid();
3751 gen_sync_exception(ctx);
3752 #endif
3753 }
3754 #endif
3755
3756 /* sc */
3757 #if defined(CONFIG_USER_ONLY)
3758 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3759 #else
3760 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3761 #endif
3762 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3763 {
3764 uint32_t lev;
3765
3766 lev = (ctx->opcode >> 5) & 0x7F;
3767 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3768 }
3769
3770 /*** Trap ***/
3771 /* tw */
3772 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3773 {
3774 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3775 /* Update the nip since this might generate a trap exception */
3776 gen_update_nip(ctx, ctx->nip);
3777 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3778 tcg_temp_free_i32(t0);
3779 }
3780
3781 /* twi */
3782 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3783 {
3784 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3785 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3786 /* Update the nip since this might generate a trap exception */
3787 gen_update_nip(ctx, ctx->nip);
3788 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3789 tcg_temp_free(t0);
3790 tcg_temp_free_i32(t1);
3791 }
3792
3793 #if defined(TARGET_PPC64)
3794 /* td */
3795 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3796 {
3797 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3798 /* Update the nip since this might generate a trap exception */
3799 gen_update_nip(ctx, ctx->nip);
3800 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3801 tcg_temp_free_i32(t0);
3802 }
3803
3804 /* tdi */
3805 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3806 {
3807 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3808 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3809 /* Update the nip since this might generate a trap exception */
3810 gen_update_nip(ctx, ctx->nip);
3811 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3812 tcg_temp_free(t0);
3813 tcg_temp_free_i32(t1);
3814 }
3815 #endif
3816
3817 /*** Processor control ***/
3818 /* mcrxr */
3819 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3820 {
3821 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3822 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3823 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3824 }
3825
3826 /* mfcr */
3827 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3828 {
3829 uint32_t crm, crn;
3830
3831 if (likely(ctx->opcode & 0x00100000)) {
3832 crm = CRM(ctx->opcode);
3833 if (likely((crm ^ (crm - 1)) == 0)) {
3834 crn = ffs(crm);
3835 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3836 }
3837 } else {
3838 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3839 }
3840 }
3841
3842 /* mfmsr */
3843 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3844 {
3845 #if defined(CONFIG_USER_ONLY)
3846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3847 #else
3848 if (unlikely(!ctx->mem_idx)) {
3849 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3850 return;
3851 }
3852 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3853 #endif
3854 }
3855
3856 #if 1
3857 #define SPR_NOACCESS ((void *)(-1UL))
3858 #else
3859 static void spr_noaccess (void *opaque, int sprn)
3860 {
3861 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3862 printf("ERROR: try to access SPR %d !\n", sprn);
3863 }
3864 #define SPR_NOACCESS (&spr_noaccess)
3865 #endif
3866
3867 /* mfspr */
3868 static always_inline void gen_op_mfspr (DisasContext *ctx)
3869 {
3870 void (*read_cb)(void *opaque, int gprn, int sprn);
3871 uint32_t sprn = SPR(ctx->opcode);
3872
3873 #if !defined(CONFIG_USER_ONLY)
3874 if (ctx->mem_idx == 2)
3875 read_cb = ctx->spr_cb[sprn].hea_read;
3876 else if (ctx->mem_idx)
3877 read_cb = ctx->spr_cb[sprn].oea_read;
3878 else
3879 #endif
3880 read_cb = ctx->spr_cb[sprn].uea_read;
3881 if (likely(read_cb != NULL)) {
3882 if (likely(read_cb != SPR_NOACCESS)) {
3883 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3884 } else {
3885 /* Privilege exception */
3886 /* This is a hack to avoid warnings when running Linux:
3887 * this OS breaks the PowerPC virtualisation model,
3888 * allowing userland application to read the PVR
3889 */
3890 if (sprn != SPR_PVR) {
3891 if (loglevel != 0) {
3892 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3893 ADDRX "\n", sprn, sprn, ctx->nip);
3894 }
3895 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3896 sprn, sprn, ctx->nip);
3897 }
3898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3899 }
3900 } else {
3901 /* Not defined */
3902 if (loglevel != 0) {
3903 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3904 ADDRX "\n", sprn, sprn, ctx->nip);
3905 }
3906 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3907 sprn, sprn, ctx->nip);
3908 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3909 }
3910 }
3911
3912 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3913 {
3914 gen_op_mfspr(ctx);
3915 }
3916
3917 /* mftb */
3918 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3919 {
3920 gen_op_mfspr(ctx);
3921 }
3922
3923 /* mtcrf */
3924 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3925 {
3926 uint32_t crm, crn;
3927
3928 crm = CRM(ctx->opcode);
3929 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3930 TCGv_i32 temp = tcg_temp_new_i32();
3931 crn = ffs(crm);
3932 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3933 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3934 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3935 tcg_temp_free_i32(temp);
3936 } else {
3937 TCGv_i32 temp = tcg_const_i32(crm);
3938 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3939 tcg_temp_free_i32(temp);
3940 }
3941 }
3942
3943 /* mtmsr */
3944 #if defined(TARGET_PPC64)
3945 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3946 {
3947 #if defined(CONFIG_USER_ONLY)
3948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3949 #else
3950 if (unlikely(!ctx->mem_idx)) {
3951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3952 return;
3953 }
3954 if (ctx->opcode & 0x00010000) {
3955 /* Special form that does not need any synchronisation */
3956 TCGv t0 = tcg_temp_new();
3957 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3958 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3959 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3960 tcg_temp_free(t0);
3961 } else {
3962 /* XXX: we need to update nip before the store
3963 * if we enter power saving mode, we will exit the loop
3964 * directly from ppc_store_msr
3965 */
3966 gen_update_nip(ctx, ctx->nip);
3967 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3968 /* Must stop the translation as machine state (may have) changed */
3969 /* Note that mtmsr is not always defined as context-synchronizing */
3970 gen_stop_exception(ctx);
3971 }
3972 #endif
3973 }
3974 #endif
3975
3976 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3977 {
3978 #if defined(CONFIG_USER_ONLY)
3979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3980 #else
3981 if (unlikely(!ctx->mem_idx)) {
3982 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3983 return;
3984 }
3985 if (ctx->opcode & 0x00010000) {
3986 /* Special form that does not need any synchronisation */
3987 TCGv t0 = tcg_temp_new();
3988 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3989 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3990 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3991 tcg_temp_free(t0);
3992 } else {
3993 /* XXX: we need to update nip before the store
3994 * if we enter power saving mode, we will exit the loop
3995 * directly from ppc_store_msr
3996 */
3997 gen_update_nip(ctx, ctx->nip);
3998 #if defined(TARGET_PPC64)
3999 if (!ctx->sf_mode) {
4000 TCGv t0 = tcg_temp_new();
4001 TCGv t1 = tcg_temp_new();
4002 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4003 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4004 tcg_gen_or_tl(t0, t0, t1);
4005 tcg_temp_free(t1);
4006 gen_helper_store_msr(t0);
4007 tcg_temp_free(t0);
4008 } else
4009 #endif
4010 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4011 /* Must stop the translation as machine state (may have) changed */
4012 /* Note that mtmsr is not always defined as context-synchronizing */
4013 gen_stop_exception(ctx);
4014 }
4015 #endif
4016 }
4017
4018 /* mtspr */
4019 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4020 {
4021 void (*write_cb)(void *opaque, int sprn, int gprn);
4022 uint32_t sprn = SPR(ctx->opcode);
4023
4024 #if !defined(CONFIG_USER_ONLY)
4025 if (ctx->mem_idx == 2)
4026 write_cb = ctx->spr_cb[sprn].hea_write;
4027 else if (ctx->mem_idx)
4028 write_cb = ctx->spr_cb[sprn].oea_write;
4029 else
4030 #endif
4031 write_cb = ctx->spr_cb[sprn].uea_write;
4032 if (likely(write_cb != NULL)) {
4033 if (likely(write_cb != SPR_NOACCESS)) {
4034 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4035 } else {
4036 /* Privilege exception */
4037 if (loglevel != 0) {
4038 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4039 ADDRX "\n", sprn, sprn, ctx->nip);
4040 }
4041 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4042 sprn, sprn, ctx->nip);
4043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4044 }
4045 } else {
4046 /* Not defined */
4047 if (loglevel != 0) {
4048 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4049 ADDRX "\n", sprn, sprn, ctx->nip);
4050 }
4051 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4052 sprn, sprn, ctx->nip);
4053 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4054 }
4055 }
4056
4057 /*** Cache management ***/
4058 /* dcbf */
4059 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4060 {
4061 /* XXX: specification says this is treated as a load by the MMU */
4062 TCGv t0;
4063 gen_set_access_type(ctx, ACCESS_CACHE);
4064 t0 = tcg_temp_new();
4065 gen_addr_reg_index(ctx, t0);
4066 gen_qemu_ld8u(ctx, t0, t0);
4067 tcg_temp_free(t0);
4068 }
4069
4070 /* dcbi (Supervisor only) */
4071 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4072 {
4073 #if defined(CONFIG_USER_ONLY)
4074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4075 #else
4076 TCGv EA, val;
4077 if (unlikely(!ctx->mem_idx)) {
4078 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4079 return;
4080 }
4081 EA = tcg_temp_new();
4082 gen_set_access_type(ctx, ACCESS_CACHE);
4083 gen_addr_reg_index(ctx, EA);
4084 val = tcg_temp_new();
4085 /* XXX: specification says this should be treated as a store by the MMU */
4086 gen_qemu_ld8u(ctx, val, EA);
4087 gen_qemu_st8(ctx, val, EA);
4088 tcg_temp_free(val);
4089 tcg_temp_free(EA);
4090 #endif
4091 }
4092
4093 /* dcdst */
4094 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4095 {
4096 /* XXX: specification say this is treated as a load by the MMU */
4097 TCGv t0;
4098 gen_set_access_type(ctx, ACCESS_CACHE);
4099 t0 = tcg_temp_new();
4100 gen_addr_reg_index(ctx, t0);
4101 gen_qemu_ld8u(ctx, t0, t0);
4102 tcg_temp_free(t0);
4103 }
4104
4105 /* dcbt */
4106 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4107 {
4108 /* interpreted as no-op */
4109 /* XXX: specification say this is treated as a load by the MMU
4110 * but does not generate any exception
4111 */
4112 }
4113
4114 /* dcbtst */
4115 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4116 {
4117 /* interpreted as no-op */
4118 /* XXX: specification say this is treated as a load by the MMU
4119 * but does not generate any exception
4120 */
4121 }
4122
4123 /* dcbz */
4124 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4125 {
4126 TCGv t0;
4127 gen_set_access_type(ctx, ACCESS_CACHE);
4128 /* NIP cannot be restored if the memory exception comes from an helper */
4129 gen_update_nip(ctx, ctx->nip - 4);
4130 t0 = tcg_temp_new();
4131 gen_addr_reg_index(ctx, t0);
4132 gen_helper_dcbz(t0);
4133 tcg_temp_free(t0);
4134 }
4135
4136 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4137 {
4138 TCGv t0;
4139 gen_set_access_type(ctx, ACCESS_CACHE);
4140 /* NIP cannot be restored if the memory exception comes from an helper */
4141 gen_update_nip(ctx, ctx->nip - 4);
4142 t0 = tcg_temp_new();
4143 gen_addr_reg_index(ctx, t0);
4144 if (ctx->opcode & 0x00200000)
4145 gen_helper_dcbz(t0);
4146 else
4147 gen_helper_dcbz_970(t0);
4148 tcg_temp_free(t0);
4149 }
4150
4151 /* icbi */
4152 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4153 {
4154 TCGv t0;
4155 gen_set_access_type(ctx, ACCESS_CACHE);
4156 /* NIP cannot be restored if the memory exception comes from an helper */
4157 gen_update_nip(ctx, ctx->nip - 4);
4158 t0 = tcg_temp_new();
4159 gen_addr_reg_index(ctx, t0);
4160 gen_helper_icbi(t0);
4161 tcg_temp_free(t0);
4162 }
4163
4164 /* Optional: */
4165 /* dcba */
4166 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4167 {
4168 /* interpreted as no-op */
4169 /* XXX: specification say this is treated as a store by the MMU
4170 * but does not generate any exception
4171 */
4172 }
4173
4174 /*** Segment register manipulation ***/
4175 /* Supervisor only: */
4176 /* mfsr */
4177 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4178 {
4179 #if defined(CONFIG_USER_ONLY)
4180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4181 #else
4182 TCGv t0;
4183 if (unlikely(!ctx->mem_idx)) {
4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4185 return;
4186 }
4187 t0 = tcg_const_tl(SR(ctx->opcode));
4188 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4189 tcg_temp_free(t0);
4190 #endif
4191 }
4192
4193 /* mfsrin */
4194 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4195 {
4196 #if defined(CONFIG_USER_ONLY)
4197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4198 #else
4199 TCGv t0;
4200 if (unlikely(!ctx->mem_idx)) {
4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202 return;
4203 }
4204 t0 = tcg_temp_new();
4205 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4206 tcg_gen_andi_tl(t0, t0, 0xF);
4207 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4208 tcg_temp_free(t0);
4209 #endif
4210 }
4211
4212 /* mtsr */
4213 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4214 {
4215 #if defined(CONFIG_USER_ONLY)
4216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4217 #else
4218 TCGv t0;
4219 if (unlikely(!ctx->mem_idx)) {
4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221 return;
4222 }
4223 t0 = tcg_const_tl(SR(ctx->opcode));
4224 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4225 tcg_temp_free(t0);
4226 #endif
4227 }
4228
4229 /* mtsrin */
4230 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4231 {
4232 #if defined(CONFIG_USER_ONLY)
4233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4234 #else
4235 TCGv t0;
4236 if (unlikely(!ctx->mem_idx)) {
4237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4238 return;
4239 }
4240 t0 = tcg_temp_new();
4241 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4242 tcg_gen_andi_tl(t0, t0, 0xF);
4243 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4244 tcg_temp_free(t0);
4245 #endif
4246 }
4247
4248 #if defined(TARGET_PPC64)
4249 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4250 /* mfsr */
4251 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4252 {
4253 #if defined(CONFIG_USER_ONLY)
4254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4255 #else
4256 TCGv t0;
4257 if (unlikely(!ctx->mem_idx)) {
4258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259 return;
4260 }
4261 t0 = tcg_const_tl(SR(ctx->opcode));
4262 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4263 tcg_temp_free(t0);
4264 #endif
4265 }
4266
4267 /* mfsrin */
4268 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4269 PPC_SEGMENT_64B)
4270 {
4271 #if defined(CONFIG_USER_ONLY)
4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4273 #else
4274 TCGv t0;
4275 if (unlikely(!ctx->mem_idx)) {
4276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4277 return;
4278 }
4279 t0 = tcg_temp_new();
4280 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4281 tcg_gen_andi_tl(t0, t0, 0xF);
4282 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4283 tcg_temp_free(t0);
4284 #endif
4285 }
4286
4287 /* mtsr */
4288 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4289 {
4290 #if defined(CONFIG_USER_ONLY)
4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4292 #else
4293 TCGv t0;
4294 if (unlikely(!ctx->mem_idx)) {
4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4296 return;
4297 }
4298 t0 = tcg_const_tl(SR(ctx->opcode));
4299 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4300 tcg_temp_free(t0);
4301 #endif
4302 }
4303
4304 /* mtsrin */
4305 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4306 PPC_SEGMENT_64B)
4307 {
4308 #if defined(CONFIG_USER_ONLY)
4309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4310 #else
4311 TCGv t0;
4312 if (unlikely(!ctx->mem_idx)) {
4313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4314 return;
4315 }
4316 t0 = tcg_temp_new();
4317 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4318 tcg_gen_andi_tl(t0, t0, 0xF);
4319 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4320 tcg_temp_free(t0);
4321 #endif
4322 }
4323 #endif /* defined(TARGET_PPC64) */
4324
4325 /*** Lookaside buffer management ***/
4326 /* Optional & mem_idx only: */
4327 /* tlbia */
4328 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4329 {
4330 #if defined(CONFIG_USER_ONLY)
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4332 #else
4333 if (unlikely(!ctx->mem_idx)) {
4334 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4335 return;
4336 }
4337 gen_helper_tlbia();
4338 #endif
4339 }
4340
4341 /* tlbie */
4342 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4343 {
4344 #if defined(CONFIG_USER_ONLY)
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4346 #else
4347 if (unlikely(!ctx->mem_idx)) {
4348 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4349 return;
4350 }
4351 #if defined(TARGET_PPC64)
4352 if (!ctx->sf_mode) {
4353 TCGv t0 = tcg_temp_new();
4354 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4355 gen_helper_tlbie(t0);
4356 tcg_temp_free(t0);
4357 } else
4358 #endif
4359 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4360 #endif
4361 }
4362
4363 /* tlbsync */
4364 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4365 {
4366 #if defined(CONFIG_USER_ONLY)
4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4368 #else
4369 if (unlikely(!ctx->mem_idx)) {
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4371 return;
4372 }
4373 /* This has no effect: it should ensure that all previous
4374 * tlbie have completed
4375 */
4376 gen_stop_exception(ctx);
4377 #endif
4378 }
4379
4380 #if defined(TARGET_PPC64)
4381 /* slbia */
4382 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4383 {
4384 #if defined(CONFIG_USER_ONLY)
4385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4386 #else
4387 if (unlikely(!ctx->mem_idx)) {
4388 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4389 return;
4390 }
4391 gen_helper_slbia();
4392 #endif
4393 }
4394
4395 /* slbie */
4396 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4397 {
4398 #if defined(CONFIG_USER_ONLY)
4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4400 #else
4401 if (unlikely(!ctx->mem_idx)) {
4402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4403 return;
4404 }
4405 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4406 #endif
4407 }
4408 #endif
4409
4410 /*** External control ***/
4411 /* Optional: */
4412 /* eciwx */
4413 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4414 {
4415 TCGv t0;
4416 /* Should check EAR[E] ! */
4417 gen_set_access_type(ctx, ACCESS_EXT);
4418 t0 = tcg_temp_new();
4419 gen_addr_reg_index(ctx, t0);
4420 gen_check_align(ctx, t0, 0x03);
4421 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4422 tcg_temp_free(t0);
4423 }
4424
4425 /* ecowx */
4426 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4427 {
4428 TCGv t0;
4429 /* Should check EAR[E] ! */
4430 gen_set_access_type(ctx, ACCESS_EXT);
4431 t0 = tcg_temp_new();
4432 gen_addr_reg_index(ctx, t0);
4433 gen_check_align(ctx, t0, 0x03);
4434 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4435 tcg_temp_free(t0);
4436 }
4437
4438 /* PowerPC 601 specific instructions */
4439 /* abs - abs. */
4440 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4441 {
4442 int l1 = gen_new_label();
4443 int l2 = gen_new_label();
4444 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4445 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4446 tcg_gen_br(l2);
4447 gen_set_label(l1);
4448 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4449 gen_set_label(l2);
4450 if (unlikely(Rc(ctx->opcode) != 0))
4451 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4452 }
4453
4454 /* abso - abso. */
4455 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4456 {
4457 int l1 = gen_new_label();
4458 int l2 = gen_new_label();
4459 int l3 = gen_new_label();
4460 /* Start with XER OV disabled, the most likely case */
4461 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4462 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4463 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4464 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4465 tcg_gen_br(l2);
4466 gen_set_label(l1);
4467 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4468 tcg_gen_br(l3);
4469 gen_set_label(l2);
4470 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4471 gen_set_label(l3);
4472 if (unlikely(Rc(ctx->opcode) != 0))
4473 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4474 }
4475
4476 /* clcs */
4477 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4478 {
4479 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4480 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4481 tcg_temp_free_i32(t0);
4482 /* Rc=1 sets CR0 to an undefined state */
4483 }
4484
4485 /* div - div. */
4486 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4487 {
4488 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4489 if (unlikely(Rc(ctx->opcode) != 0))
4490 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4491 }
4492
4493 /* divo - divo. */
4494 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4495 {
4496 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4497 if (unlikely(Rc(ctx->opcode) != 0))
4498 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4499 }
4500
4501 /* divs - divs. */
4502 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4503 {
4504 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4505 if (unlikely(Rc(ctx->opcode) != 0))
4506 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4507 }
4508
4509 /* divso - divso. */
4510 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4511 {
4512 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4513 if (unlikely(Rc(ctx->opcode) != 0))
4514 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4515 }
4516
4517 /* doz - doz. */
4518 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4519 {
4520 int l1 = gen_new_label();
4521 int l2 = gen_new_label();
4522 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4523 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4524 tcg_gen_br(l2);
4525 gen_set_label(l1);
4526 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4527 gen_set_label(l2);
4528 if (unlikely(Rc(ctx->opcode) != 0))
4529 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4530 }
4531
4532 /* dozo - dozo. */
4533 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4534 {
4535 int l1 = gen_new_label();
4536 int l2 = gen_new_label();
4537 TCGv t0 = tcg_temp_new();
4538 TCGv t1 = tcg_temp_new();
4539 TCGv t2 = tcg_temp_new();
4540 /* Start with XER OV disabled, the most likely case */
4541 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4542 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4543 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4544 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4545 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4546 tcg_gen_andc_tl(t1, t1, t2);
4547 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4548 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4549 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4550 tcg_gen_br(l2);
4551 gen_set_label(l1);
4552 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4553 gen_set_label(l2);
4554 tcg_temp_free(t0);
4555 tcg_temp_free(t1);
4556 tcg_temp_free(t2);
4557 if (unlikely(Rc(ctx->opcode) != 0))
4558 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4559 }
4560
4561 /* dozi */
4562 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4563 {
4564 target_long simm = SIMM(ctx->opcode);
4565 int l1 = gen_new_label();
4566 int l2 = gen_new_label();
4567 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4568 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4569 tcg_gen_br(l2);
4570 gen_set_label(l1);
4571 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4572 gen_set_label(l2);
4573 if (unlikely(Rc(ctx->opcode) != 0))
4574 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4575 }
4576
4577 /* lscbx - lscbx. */
4578 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4579 {
4580 TCGv t0 = tcg_temp_new();
4581 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4582 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4583 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4584
4585 gen_addr_reg_index(ctx, t0);
4586 /* NIP cannot be restored if the memory exception comes from an helper */
4587 gen_update_nip(ctx, ctx->nip - 4);
4588 gen_helper_lscbx(t0, t0, t1, t2, t3);
4589 tcg_temp_free_i32(t1);
4590 tcg_temp_free_i32(t2);
4591 tcg_temp_free_i32(t3);
4592 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4593 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4594 if (unlikely(Rc(ctx->opcode) != 0))
4595 gen_set_Rc0(ctx, t0);
4596 tcg_temp_free(t0);
4597 }
4598
4599 /* maskg - maskg. */
4600 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4601 {
4602 int l1 = gen_new_label();
4603 TCGv t0 = tcg_temp_new();
4604 TCGv t1 = tcg_temp_new();
4605 TCGv t2 = tcg_temp_new();
4606 TCGv t3 = tcg_temp_new();
4607 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4608 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4609 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4610 tcg_gen_addi_tl(t2, t0, 1);
4611 tcg_gen_shr_tl(t2, t3, t2);
4612 tcg_gen_shr_tl(t3, t3, t1);
4613 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4614 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4615 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4616 gen_set_label(l1);
4617 tcg_temp_free(t0);
4618 tcg_temp_free(t1);
4619 tcg_temp_free(t2);
4620 tcg_temp_free(t3);
4621 if (unlikely(Rc(ctx->opcode) != 0))
4622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4623 }
4624
4625 /* maskir - maskir. */
4626 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4627 {
4628 TCGv t0 = tcg_temp_new();
4629 TCGv t1 = tcg_temp_new();
4630 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4631 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4632 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4633 tcg_temp_free(t0);
4634 tcg_temp_free(t1);
4635 if (unlikely(Rc(ctx->opcode) != 0))
4636 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4637 }
4638
4639 /* mul - mul. */
4640 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4641 {
4642 TCGv_i64 t0 = tcg_temp_new_i64();
4643 TCGv_i64 t1 = tcg_temp_new_i64();
4644 TCGv t2 = tcg_temp_new();
4645 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4646 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4647 tcg_gen_mul_i64(t0, t0, t1);
4648 tcg_gen_trunc_i64_tl(t2, t0);
4649 gen_store_spr(SPR_MQ, t2);
4650 tcg_gen_shri_i64(t1, t0, 32);
4651 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4652 tcg_temp_free_i64(t0);
4653 tcg_temp_free_i64(t1);
4654 tcg_temp_free(t2);
4655 if (unlikely(Rc(ctx->opcode) != 0))
4656 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4657 }
4658
4659 /* mulo - mulo. */
4660 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4661 {
4662 int l1 = gen_new_label();
4663 TCGv_i64 t0 = tcg_temp_new_i64();
4664 TCGv_i64 t1 = tcg_temp_new_i64();
4665 TCGv t2 = tcg_temp_new();
4666 /* Start with XER OV disabled, the most likely case */
4667 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4668 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4669 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4670 tcg_gen_mul_i64(t0, t0, t1);
4671 tcg_gen_trunc_i64_tl(t2, t0);
4672 gen_store_spr(SPR_MQ, t2);
4673 tcg_gen_shri_i64(t1, t0, 32);
4674 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4675 tcg_gen_ext32s_i64(t1, t0);
4676 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4677 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4678 gen_set_label(l1);
4679 tcg_temp_free_i64(t0);
4680 tcg_temp_free_i64(t1);
4681 tcg_temp_free(t2);
4682 if (unlikely(Rc(ctx->opcode) != 0))
4683 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4684 }
4685
4686 /* nabs - nabs. */
4687 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4688 {
4689 int l1 = gen_new_label();
4690 int l2 = gen_new_label();
4691 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4692 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4693 tcg_gen_br(l2);
4694 gen_set_label(l1);
4695 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4696 gen_set_label(l2);
4697 if (unlikely(Rc(ctx->opcode) != 0))
4698 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4699 }
4700
4701 /* nabso - nabso. */
4702 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4703 {
4704 int l1 = gen_new_label();
4705 int l2 = gen_new_label();
4706 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4707 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4708 tcg_gen_br(l2);
4709 gen_set_label(l1);
4710 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4711 gen_set_label(l2);
4712 /* nabs never overflows */
4713 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4714 if (unlikely(Rc(ctx->opcode) != 0))
4715 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4716 }
4717
4718 /* rlmi - rlmi. */
4719 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4720 {
4721 uint32_t mb = MB(ctx->opcode);
4722 uint32_t me = ME(ctx->opcode);
4723 TCGv t0 = tcg_temp_new();
4724 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4725 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4726 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4727 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4728 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4729 tcg_temp_free(t0);
4730 if (unlikely(Rc(ctx->opcode) != 0))
4731 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4732 }
4733
4734 /* rrib - rrib. */
4735 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4736 {
4737 TCGv t0 = tcg_temp_new();
4738 TCGv t1 = tcg_temp_new();
4739 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4740 tcg_gen_movi_tl(t1, 0x80000000);
4741 tcg_gen_shr_tl(t1, t1, t0);
4742 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4743 tcg_gen_and_tl(t0, t0, t1);
4744 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4745 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4746 tcg_temp_free(t0);
4747 tcg_temp_free(t1);
4748 if (unlikely(Rc(ctx->opcode) != 0))
4749 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4750 }
4751
4752 /* sle - sle. */
4753 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4754 {
4755 TCGv t0 = tcg_temp_new();
4756 TCGv t1 = tcg_temp_new();
4757 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4758 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4759 tcg_gen_subfi_tl(t1, 32, t1);
4760 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4761 tcg_gen_or_tl(t1, t0, t1);
4762 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4763 gen_store_spr(SPR_MQ, t1);
4764 tcg_temp_free(t0);
4765 tcg_temp_free(t1);
4766 if (unlikely(Rc(ctx->opcode) != 0))
4767 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4768 }
4769
4770 /* sleq - sleq. */
4771 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4772 {
4773 TCGv t0 = tcg_temp_new();
4774 TCGv t1 = tcg_temp_new();
4775 TCGv t2 = tcg_temp_new();
4776 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4777 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4778 tcg_gen_shl_tl(t2, t2, t0);
4779 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4780 gen_load_spr(t1, SPR_MQ);
4781 gen_store_spr(SPR_MQ, t0);
4782 tcg_gen_and_tl(t0, t0, t2);
4783 tcg_gen_andc_tl(t1, t1, t2);
4784 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4785 tcg_temp_free(t0);
4786 tcg_temp_free(t1);
4787 tcg_temp_free(t2);
4788 if (unlikely(Rc(ctx->opcode) != 0))
4789 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4790 }
4791
4792 /* sliq - sliq. */
4793 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4794 {
4795 int sh = SH(ctx->opcode);
4796 TCGv t0 = tcg_temp_new();
4797 TCGv t1 = tcg_temp_new();
4798 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4799 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4800 tcg_gen_or_tl(t1, t0, t1);
4801 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4802 gen_store_spr(SPR_MQ, t1);
4803 tcg_temp_free(t0);
4804 tcg_temp_free(t1);
4805 if (unlikely(Rc(ctx->opcode) != 0))
4806 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4807 }
4808
4809 /* slliq - slliq. */
4810 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4811 {
4812 int sh = SH(ctx->opcode);
4813 TCGv t0 = tcg_temp_new();
4814 TCGv t1 = tcg_temp_new();
4815 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4816 gen_load_spr(t1, SPR_MQ);
4817 gen_store_spr(SPR_MQ, t0);
4818 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4819 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4820 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4821 tcg_temp_free(t0);
4822 tcg_temp_free(t1);
4823 if (unlikely(Rc(ctx->opcode) != 0))
4824 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4825 }
4826
4827 /* sllq - sllq. */
4828 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4829 {
4830 int l1 = gen_new_label();
4831 int l2 = gen_new_label();
4832 TCGv t0 = tcg_temp_local_new();
4833 TCGv t1 = tcg_temp_local_new();
4834 TCGv t2 = tcg_temp_local_new();
4835 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4836 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4837 tcg_gen_shl_tl(t1, t1, t2);
4838 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4839 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4840 gen_load_spr(t0, SPR_MQ);
4841 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4842 tcg_gen_br(l2);
4843 gen_set_label(l1);
4844 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4845 gen_load_spr(t2, SPR_MQ);
4846 tcg_gen_andc_tl(t1, t2, t1);
4847 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4848 gen_set_label(l2);
4849 tcg_temp_free(t0);
4850 tcg_temp_free(t1);
4851 tcg_temp_free(t2);
4852 if (unlikely(Rc(ctx->opcode) != 0))
4853 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4854 }
4855
4856 /* slq - slq. */
4857 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4858 {
4859 int l1 = gen_new_label();
4860 TCGv t0 = tcg_temp_new();
4861 TCGv t1 = tcg_temp_new();
4862 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4863 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4864 tcg_gen_subfi_tl(t1, 32, t1);
4865 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4866 tcg_gen_or_tl(t1, t0, t1);
4867 gen_store_spr(SPR_MQ, t1);
4868 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4869 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4870 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4871 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4872 gen_set_label(l1);
4873 tcg_temp_free(t0);
4874 tcg_temp_free(t1);
4875 if (unlikely(Rc(ctx->opcode) != 0))
4876 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4877 }
4878
4879 /* sraiq - sraiq. */
4880 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4881 {
4882 int sh = SH(ctx->opcode);
4883 int l1 = gen_new_label();
4884 TCGv t0 = tcg_temp_new();
4885 TCGv t1 = tcg_temp_new();
4886 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4887 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4888 tcg_gen_or_tl(t0, t0, t1);
4889 gen_store_spr(SPR_MQ, t0);
4890 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4891 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4892 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4893 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4894 gen_set_label(l1);
4895 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4896 tcg_temp_free(t0);
4897 tcg_temp_free(t1);
4898 if (unlikely(Rc(ctx->opcode) != 0))
4899 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4900 }
4901
4902 /* sraq - sraq. */
4903 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4904 {
4905 int l1 = gen_new_label();
4906 int l2 = gen_new_label();
4907 TCGv t0 = tcg_temp_new();
4908 TCGv t1 = tcg_temp_local_new();
4909 TCGv t2 = tcg_temp_local_new();
4910 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4911 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4912 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4913 tcg_gen_subfi_tl(t2, 32, t2);
4914 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4915 tcg_gen_or_tl(t0, t0, t2);
4916 gen_store_spr(SPR_MQ, t0);
4917 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4918 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4919 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4920 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4921 gen_set_label(l1);
4922 tcg_temp_free(t0);
4923 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4924 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4925 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4926 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4927 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4928 gen_set_label(l2);
4929 tcg_temp_free(t1);
4930 tcg_temp_free(t2);
4931 if (unlikely(Rc(ctx->opcode) != 0))
4932 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4933 }
4934
4935 /* sre - sre. */
4936 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4937 {
4938 TCGv t0 = tcg_temp_new();
4939 TCGv t1 = tcg_temp_new();
4940 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4941 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4942 tcg_gen_subfi_tl(t1, 32, t1);
4943 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4944 tcg_gen_or_tl(t1, t0, t1);
4945 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4946 gen_store_spr(SPR_MQ, t1);
4947 tcg_temp_free(t0);
4948 tcg_temp_free(t1);
4949 if (unlikely(Rc(ctx->opcode) != 0))
4950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4951 }
4952
4953 /* srea - srea. */
4954 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4955 {
4956 TCGv t0 = tcg_temp_new();
4957 TCGv t1 = tcg_temp_new();
4958 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4959 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4960 gen_store_spr(SPR_MQ, t0);
4961 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4962 tcg_temp_free(t0);
4963 tcg_temp_free(t1);
4964 if (unlikely(Rc(ctx->opcode) != 0))
4965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4966 }
4967
4968 /* sreq */
4969 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4970 {
4971 TCGv t0 = tcg_temp_new();
4972 TCGv t1 = tcg_temp_new();
4973 TCGv t2 = tcg_temp_new();
4974 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4975 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4976 tcg_gen_shr_tl(t1, t1, t0);
4977 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4978 gen_load_spr(t2, SPR_MQ);
4979 gen_store_spr(SPR_MQ, t0);
4980 tcg_gen_and_tl(t0, t0, t1);
4981 tcg_gen_andc_tl(t2, t2, t1);
4982 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4983 tcg_temp_free(t0);
4984 tcg_temp_free(t1);
4985 tcg_temp_free(t2);
4986 if (unlikely(Rc(ctx->opcode) != 0))
4987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4988 }
4989
4990 /* sriq */
4991 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4992 {
4993 int sh = SH(ctx->opcode);
4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4997 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4998 tcg_gen_or_tl(t1, t0, t1);
4999 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5000 gen_store_spr(SPR_MQ, t1);
5001 tcg_temp_free(t0);
5002 tcg_temp_free(t1);
5003 if (unlikely(Rc(ctx->opcode) != 0))
5004 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5005 }
5006
5007 /* srliq */
5008 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5009 {
5010 int sh = SH(ctx->opcode);
5011 TCGv t0 = tcg_temp_new();
5012 TCGv t1 = tcg_temp_new();
5013 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5014 gen_load_spr(t1, SPR_MQ);
5015 gen_store_spr(SPR_MQ, t0);
5016 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5017 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5018 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5019 tcg_temp_free(t0);
5020 tcg_temp_free(t1);
5021 if (unlikely(Rc(ctx->opcode) != 0))
5022 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5023 }
5024
5025 /* srlq */
5026 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5027 {
5028 int l1 = gen_new_label();
5029 int l2 = gen_new_label();
5030 TCGv t0 = tcg_temp_local_new();
5031 TCGv t1 = tcg_temp_local_new();
5032 TCGv t2 = tcg_temp_local_new();
5033 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5034 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5035 tcg_gen_shr_tl(t2, t1, t2);
5036 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5037 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5038 gen_load_spr(t0, SPR_MQ);
5039 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5040 tcg_gen_br(l2);
5041 gen_set_label(l1);
5042 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5043 tcg_gen_and_tl(t0, t0, t2);
5044 gen_load_spr(t1, SPR_MQ);
5045 tcg_gen_andc_tl(t1, t1, t2);
5046 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5047 gen_set_label(l2);
5048 tcg_temp_free(t0);
5049 tcg_temp_free(t1);
5050 tcg_temp_free(t2);
5051 if (unlikely(Rc(ctx->opcode) != 0))
5052 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5053 }
5054
5055 /* srq */
5056 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5057 {
5058 int l1 = gen_new_label();
5059 TCGv t0 = tcg_temp_new();
5060 TCGv t1 = tcg_temp_new();
5061 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5062 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5063 tcg_gen_subfi_tl(t1, 32, t1);
5064 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5065 tcg_gen_or_tl(t1, t0, t1);
5066 gen_store_spr(SPR_MQ, t1);
5067 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5068 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5069 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5070 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5071 gen_set_label(l1);
5072 tcg_temp_free(t0);
5073 tcg_temp_free(t1);
5074 if (unlikely(Rc(ctx->opcode) != 0))
5075 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5076 }
5077
5078 /* PowerPC 602 specific instructions */
5079 /* dsa */
5080 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5081 {
5082 /* XXX: TODO */
5083 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5084 }
5085
5086 /* esa */
5087 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5088 {
5089 /* XXX: TODO */
5090 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5091 }
5092
5093 /* mfrom */
5094 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5095 {
5096 #if defined(CONFIG_USER_ONLY)
5097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5098 #else
5099 if (unlikely(!ctx->mem_idx)) {
5100 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5101 return;
5102 }
5103 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5104 #endif
5105 }
5106
5107 /* 602 - 603 - G2 TLB management */
5108 /* tlbld */
5109 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5110 {
5111 #if defined(CONFIG_USER_ONLY)
5112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5113 #else
5114 if (unlikely(!ctx->mem_idx)) {
5115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5116 return;
5117 }
5118 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5119 #endif
5120 }
5121
5122 /* tlbli */
5123 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5124 {
5125 #if defined(CONFIG_USER_ONLY)
5126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5127 #else
5128 if (unlikely(!ctx->mem_idx)) {
5129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5130 return;
5131 }
5132 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5133 #endif
5134 }
5135
5136 /* 74xx TLB management */
5137 /* tlbld */
5138 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5139 {
5140 #if defined(CONFIG_USER_ONLY)
5141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5142 #else
5143 if (unlikely(!ctx->mem_idx)) {
5144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5145 return;
5146 }
5147 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5148 #endif
5149 }
5150
5151 /* tlbli */
5152 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5153 {
5154 #if defined(CONFIG_USER_ONLY)
5155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5156 #else
5157 if (unlikely(!ctx->mem_idx)) {
5158 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5159 return;
5160 }
5161 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5162 #endif
5163 }
5164
5165 /* POWER instructions not in PowerPC 601 */
5166 /* clf */
5167 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5168 {
5169 /* Cache line flush: implemented as no-op */
5170 }
5171
5172 /* cli */
5173 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5174 {
5175 /* Cache line invalidate: privileged and treated as no-op */
5176 #if defined(CONFIG_USER_ONLY)
5177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5178 #else
5179 if (unlikely(!ctx->mem_idx)) {
5180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5181 return;
5182 }
5183 #endif
5184 }
5185
5186 /* dclst */
5187 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5188 {
5189 /* Data cache line store: treated as no-op */
5190 }
5191
5192 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5193 {
5194 #if defined(CONFIG_USER_ONLY)
5195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5196 #else
5197 int ra = rA(ctx->opcode);
5198 int rd = rD(ctx->opcode);
5199 TCGv t0;
5200 if (unlikely(!ctx->mem_idx)) {
5201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5202 return;
5203 }
5204 t0 = tcg_temp_new();
5205 gen_addr_reg_index(ctx, t0);
5206 tcg_gen_shri_tl(t0, t0, 28);
5207 tcg_gen_andi_tl(t0, t0, 0xF);
5208 gen_helper_load_sr(cpu_gpr[rd], t0);
5209 tcg_temp_free(t0);
5210 if (ra != 0 && ra != rd)
5211 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5212 #endif
5213 }
5214
5215 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5216 {
5217 #if defined(CONFIG_USER_ONLY)
5218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5219 #else
5220 TCGv t0;
5221 if (unlikely(!ctx->mem_idx)) {
5222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5223 return;
5224 }
5225 t0 = tcg_temp_new();
5226 gen_addr_reg_index(ctx, t0);
5227 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5228 tcg_temp_free(t0);
5229 #endif
5230 }
5231
5232 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5233 {
5234 #if defined(CONFIG_USER_ONLY)
5235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5236 #else
5237 if (unlikely(!ctx->mem_idx)) {
5238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5239 return;
5240 }
5241 gen_helper_rfsvc();
5242 gen_sync_exception(ctx);
5243 #endif
5244 }
5245
5246 /* svc is not implemented for now */
5247
5248 /* POWER2 specific instructions */
5249 /* Quad manipulation (load/store two floats at a time) */
5250
5251 /* lfq */
5252 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5253 {
5254 int rd = rD(ctx->opcode);
5255 TCGv t0;
5256 gen_set_access_type(ctx, ACCESS_FLOAT);
5257 t0 = tcg_temp_new();
5258 gen_addr_imm_index(ctx, t0, 0);
5259 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5260 gen_addr_add(ctx, t0, t0, 8);
5261 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5262 tcg_temp_free(t0);
5263 }
5264
5265 /* lfqu */
5266 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5267 {
5268 int ra = rA(ctx->opcode);
5269 int rd = rD(ctx->opcode);
5270 TCGv t0, t1;
5271 gen_set_access_type(ctx, ACCESS_FLOAT);
5272 t0 = tcg_temp_new();
5273 t1 = tcg_temp_new();
5274 gen_addr_imm_index(ctx, t0, 0);
5275 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5276 gen_addr_add(ctx, t1, t0, 8);
5277 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5278 if (ra != 0)
5279 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5280 tcg_temp_free(t0);
5281 tcg_temp_free(t1);
5282 }
5283
5284 /* lfqux */
5285 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5286 {
5287 int ra = rA(ctx->opcode);
5288 int rd = rD(ctx->opcode);
5289 gen_set_access_type(ctx, ACCESS_FLOAT);
5290 TCGv t0, t1;
5291 t0 = tcg_temp_new();
5292 gen_addr_reg_index(ctx, t0);
5293 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5294 t1 = tcg_temp_new();
5295 gen_addr_add(ctx, t1, t0, 8);
5296 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5297 tcg_temp_free(t1);
5298 if (ra != 0)
5299 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5300 tcg_temp_free(t0);
5301 }
5302
5303 /* lfqx */
5304 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5305 {
5306 int rd = rD(ctx->opcode);
5307 TCGv t0;
5308 gen_set_access_type(ctx, ACCESS_FLOAT);
5309 t0 = tcg_temp_new();
5310 gen_addr_reg_index(ctx, t0);
5311 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5312 gen_addr_add(ctx, t0, t0, 8);
5313 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5314 tcg_temp_free(t0);
5315 }
5316
5317 /* stfq */
5318 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5319 {
5320 int rd = rD(ctx->opcode);
5321 TCGv t0;
5322 gen_set_access_type(ctx, ACCESS_FLOAT);
5323 t0 = tcg_temp_new();
5324 gen_addr_imm_index(ctx, t0, 0);
5325 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5326 gen_addr_add(ctx, t0, t0, 8);
5327 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5328 tcg_temp_free(t0);
5329 }
5330
5331 /* stfqu */
5332 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5333 {
5334 int ra = rA(ctx->opcode);
5335 int rd = rD(ctx->opcode);
5336 TCGv t0, t1;
5337 gen_set_access_type(ctx, ACCESS_FLOAT);
5338 t0 = tcg_temp_new();
5339 gen_addr_imm_index(ctx, t0, 0);
5340 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5341 t1 = tcg_temp_new();
5342 gen_addr_add(ctx, t1, t0, 8);
5343 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5344 tcg_temp_free(t1);
5345 if (ra != 0)
5346 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5347 tcg_temp_free(t0);
5348 }
5349
5350 /* stfqux */
5351 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5352 {
5353 int ra = rA(ctx->opcode);
5354 int rd = rD(ctx->opcode);
5355 TCGv t0, t1;
5356 gen_set_access_type(ctx, ACCESS_FLOAT);
5357 t0 = tcg_temp_new();
5358 gen_addr_reg_index(ctx, t0);
5359 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5360 t1 = tcg_temp_new();
5361 gen_addr_add(ctx, t1, t0, 8);
5362 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5363 tcg_temp_free(t1);
5364 if (ra != 0)
5365 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5366 tcg_temp_free(t0);
5367 }
5368
5369 /* stfqx */
5370 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5371 {
5372 int rd = rD(ctx->opcode);
5373 TCGv t0;
5374 gen_set_access_type(ctx, ACCESS_FLOAT);
5375 t0 = tcg_temp_new();
5376 gen_addr_reg_index(ctx, t0);
5377 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5378 gen_addr_add(ctx, t0, t0, 8);
5379 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5380 tcg_temp_free(t0);
5381 }
5382
5383 /* BookE specific instructions */
5384 /* XXX: not implemented on 440 ? */
5385 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5386 {
5387 /* XXX: TODO */
5388 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5389 }
5390
5391 /* XXX: not implemented on 440 ? */
5392 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5393 {
5394 #if defined(CONFIG_USER_ONLY)
5395 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5396 #else
5397 TCGv t0;
5398 if (unlikely(!ctx->mem_idx)) {
5399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5400 return;
5401 }
5402 t0 = tcg_temp_new();
5403 gen_addr_reg_index(ctx, t0);
5404 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5405 tcg_temp_free(t0);
5406 #endif
5407 }
5408
5409 /* All 405 MAC instructions are translated here */
5410 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5411 int opc2, int opc3,
5412 int ra, int rb, int rt, int Rc)
5413 {
5414 TCGv t0, t1;
5415
5416 t0 = tcg_temp_local_new();
5417 t1 = tcg_temp_local_new();
5418
5419 switch (opc3 & 0x0D) {
5420 case 0x05:
5421 /* macchw - macchw. - macchwo - macchwo. */
5422 /* macchws - macchws. - macchwso - macchwso. */
5423 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5424 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5425 /* mulchw - mulchw. */
5426 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5427 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5428 tcg_gen_ext16s_tl(t1, t1);
5429 break;
5430 case 0x04:
5431 /* macchwu - macchwu. - macchwuo - macchwuo. */
5432 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5433 /* mulchwu - mulchwu. */
5434 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5435 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5436 tcg_gen_ext16u_tl(t1, t1);
5437 break;
5438 case 0x01:
5439 /* machhw - machhw. - machhwo - machhwo. */
5440 /* machhws - machhws. - machhwso - machhwso. */
5441 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5442 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5443 /* mulhhw - mulhhw. */
5444 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5445 tcg_gen_ext16s_tl(t0, t0);
5446 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5447 tcg_gen_ext16s_tl(t1, t1);
5448 break;
5449 case 0x00:
5450 /* machhwu - machhwu. - machhwuo - machhwuo. */
5451 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5452 /* mulhhwu - mulhhwu. */
5453 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5454 tcg_gen_ext16u_tl(t0, t0);
5455 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5456 tcg_gen_ext16u_tl(t1, t1);
5457 break;
5458 case 0x0D:
5459 /* maclhw - maclhw. - maclhwo - maclhwo. */
5460 /* maclhws - maclhws. - maclhwso - maclhwso. */
5461 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5462 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5463 /* mullhw - mullhw. */
5464 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5465 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5466 break;
5467 case 0x0C:
5468 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5469 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5470 /* mullhwu - mullhwu. */
5471 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5472 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5473 break;
5474 }
5475 if (opc2 & 0x04) {
5476 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5477 tcg_gen_mul_tl(t1, t0, t1);
5478 if (opc2 & 0x02) {
5479 /* nmultiply-and-accumulate (0x0E) */
5480 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5481 } else {
5482 /* multiply-and-accumulate (0x0C) */
5483 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5484 }
5485
5486 if (opc3 & 0x12) {
5487 /* Check overflow and/or saturate */
5488 int l1 = gen_new_label();
5489
5490 if (opc3 & 0x10) {
5491 /* Start with XER OV disabled, the most likely case */
5492 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5493 }
5494 if (opc3 & 0x01) {
5495 /* Signed */
5496 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5497 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5498 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5499 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5500 if (opc3 & 0x02) {
5501 /* Saturate */
5502 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5503 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5504 }
5505 } else {
5506 /* Unsigned */
5507 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5508 if (opc3 & 0x02) {
5509 /* Saturate */
5510 tcg_gen_movi_tl(t0, UINT32_MAX);
5511 }
5512 }
5513 if (opc3 & 0x10) {
5514 /* Check overflow */
5515 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5516 }
5517 gen_set_label(l1);
5518 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5519 }
5520 } else {
5521 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5522 }
5523 tcg_temp_free(t0);
5524 tcg_temp_free(t1);
5525 if (unlikely(Rc) != 0) {
5526 /* Update Rc0 */
5527 gen_set_Rc0(ctx, cpu_gpr[rt]);
5528 }
5529 }
5530
5531 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5532 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5533 { \
5534 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5535 rD(ctx->opcode), Rc(ctx->opcode)); \
5536 }
5537
5538 /* macchw - macchw. */
5539 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5540 /* macchwo - macchwo. */
5541 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5542 /* macchws - macchws. */
5543 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5544 /* macchwso - macchwso. */
5545 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5546 /* macchwsu - macchwsu. */
5547 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5548 /* macchwsuo - macchwsuo. */
5549 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5550 /* macchwu - macchwu. */
5551 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5552 /* macchwuo - macchwuo. */
5553 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5554 /* machhw - machhw. */
5555 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5556 /* machhwo - machhwo. */
5557 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5558 /* machhws - machhws. */
5559 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5560 /* machhwso - machhwso. */
5561 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5562 /* machhwsu - machhwsu. */
5563 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5564 /* machhwsuo - machhwsuo. */
5565 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5566 /* machhwu - machhwu. */
5567 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5568 /* machhwuo - machhwuo. */
5569 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5570 /* maclhw - maclhw. */
5571 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5572 /* maclhwo - maclhwo. */
5573 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5574 /* maclhws - maclhws. */
5575 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5576 /* maclhwso - maclhwso. */
5577 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5578 /* maclhwu - maclhwu. */
5579 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5580 /* maclhwuo - maclhwuo. */
5581 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5582 /* maclhwsu - maclhwsu. */
5583 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5584 /* maclhwsuo - maclhwsuo. */
5585 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5586 /* nmacchw - nmacchw. */
5587 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5588 /* nmacchwo - nmacchwo. */
5589 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5590 /* nmacchws - nmacchws. */
5591 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5592 /* nmacchwso - nmacchwso. */
5593 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5594 /* nmachhw - nmachhw. */
5595 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5596 /* nmachhwo - nmachhwo. */
5597 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5598 /* nmachhws - nmachhws. */
5599 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5600 /* nmachhwso - nmachhwso. */
5601 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5602 /* nmaclhw - nmaclhw. */
5603 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5604 /* nmaclhwo - nmaclhwo. */
5605 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5606 /* nmaclhws - nmaclhws. */
5607 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5608 /* nmaclhwso - nmaclhwso. */
5609 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5610
5611 /* mulchw - mulchw. */
5612 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5613 /* mulchwu - mulchwu. */
5614 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5615 /* mulhhw - mulhhw. */
5616 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5617 /* mulhhwu - mulhhwu. */
5618 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5619 /* mullhw - mullhw. */
5620 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5621 /* mullhwu - mullhwu. */
5622 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5623
5624 /* mfdcr */
5625 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5626 {
5627 #if defined(CONFIG_USER_ONLY)
5628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5629 #else
5630 TCGv dcrn;
5631 if (unlikely(!ctx->mem_idx)) {
5632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5633 return;
5634 }
5635 /* NIP cannot be restored if the memory exception comes from an helper */
5636 gen_update_nip(ctx, ctx->nip - 4);
5637 dcrn = tcg_const_tl(SPR(ctx->opcode));
5638 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5639 tcg_temp_free(dcrn);
5640 #endif
5641 }
5642
5643 /* mtdcr */
5644 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5645 {
5646 #if defined(CONFIG_USER_ONLY)
5647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5648 #else
5649 TCGv dcrn;
5650 if (unlikely(!ctx->mem_idx)) {
5651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5652 return;
5653 }
5654 /* NIP cannot be restored if the memory exception comes from an helper */
5655 gen_update_nip(ctx, ctx->nip - 4);
5656 dcrn = tcg_const_tl(SPR(ctx->opcode));
5657 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5658 tcg_temp_free(dcrn);
5659 #endif
5660 }
5661
5662 /* mfdcrx */
5663 /* XXX: not implemented on 440 ? */
5664 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5665 {
5666 #if defined(CONFIG_USER_ONLY)
5667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5668 #else
5669 if (unlikely(!ctx->mem_idx)) {
5670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5671 return;
5672 }
5673 /* NIP cannot be restored if the memory exception comes from an helper */
5674 gen_update_nip(ctx, ctx->nip - 4);
5675 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5676 /* Note: Rc update flag set leads to undefined state of Rc0 */
5677 #endif
5678 }
5679
5680 /* mtdcrx */
5681 /* XXX: not implemented on 440 ? */
5682 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5683 {
5684 #if defined(CONFIG_USER_ONLY)
5685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5686 #else
5687 if (unlikely(!ctx->mem_idx)) {
5688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5689 return;
5690 }
5691 /* NIP cannot be restored if the memory exception comes from an helper */
5692 gen_update_nip(ctx, ctx->nip - 4);
5693 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5694 /* Note: Rc update flag set leads to undefined state of Rc0 */
5695 #endif
5696 }
5697
5698 /* mfdcrux (PPC 460) : user-mode access to DCR */
5699 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5700 {
5701 /* NIP cannot be restored if the memory exception comes from an helper */
5702 gen_update_nip(ctx, ctx->nip - 4);
5703 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5704 /* Note: Rc update flag set leads to undefined state of Rc0 */
5705 }
5706
5707 /* mtdcrux (PPC 460) : user-mode access to DCR */
5708 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5709 {
5710 /* NIP cannot be restored if the memory exception comes from an helper */
5711 gen_update_nip(ctx, ctx->nip - 4);
5712 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5713 /* Note: Rc update flag set leads to undefined state of Rc0 */
5714 }
5715
5716 /* dccci */
5717 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5718 {
5719 #if defined(CONFIG_USER_ONLY)
5720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5721 #else
5722 if (unlikely(!ctx->mem_idx)) {
5723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5724 return;
5725 }
5726 /* interpreted as no-op */
5727 #endif
5728 }
5729
5730 /* dcread */
5731 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5732 {
5733 #if defined(CONFIG_USER_ONLY)
5734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5735 #else
5736 TCGv EA, val;
5737 if (unlikely(!ctx->mem_idx)) {
5738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5739 return;
5740 }
5741 gen_set_access_type(ctx, ACCESS_CACHE);
5742 EA = tcg_temp_new();
5743 gen_addr_reg_index(ctx, EA);
5744 val = tcg_temp_new();
5745 gen_qemu_ld32u(ctx, val, EA);
5746 tcg_temp_free(val);
5747 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5748 tcg_temp_free(EA);
5749 #endif
5750 }
5751
5752 /* icbt */
5753 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5754 {
5755 /* interpreted as no-op */
5756 /* XXX: specification say this is treated as a load by the MMU
5757 * but does not generate any exception
5758 */
5759 }
5760
5761 /* iccci */
5762 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5763 {
5764 #if defined(CONFIG_USER_ONLY)
5765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5766 #else
5767 if (unlikely(!ctx->mem_idx)) {
5768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5769 return;
5770 }
5771 /* interpreted as no-op */
5772 #endif
5773 }
5774
5775 /* icread */
5776 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5777 {
5778 #if defined(CONFIG_USER_ONLY)
5779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5780 #else
5781 if (unlikely(!ctx->mem_idx)) {
5782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5783 return;
5784 }
5785 /* interpreted as no-op */
5786 #endif
5787 }
5788
5789 /* rfci (mem_idx only) */
5790 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5791 {
5792 #if defined(CONFIG_USER_ONLY)
5793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5794 #else
5795 if (unlikely(!ctx->mem_idx)) {
5796 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5797 return;
5798 }
5799 /* Restore CPU state */
5800 gen_helper_40x_rfci();
5801 gen_sync_exception(ctx);
5802 #endif
5803 }
5804
5805 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5806 {
5807 #if defined(CONFIG_USER_ONLY)
5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5809 #else
5810 if (unlikely(!ctx->mem_idx)) {
5811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5812 return;
5813 }
5814 /* Restore CPU state */
5815 gen_helper_rfci();
5816 gen_sync_exception(ctx);
5817 #endif
5818 }
5819
5820 /* BookE specific */
5821 /* XXX: not implemented on 440 ? */
5822 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5823 {
5824 #if defined(CONFIG_USER_ONLY)
5825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5826 #else
5827 if (unlikely(!ctx->mem_idx)) {
5828 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5829 return;
5830 }
5831 /* Restore CPU state */
5832 gen_helper_rfdi();
5833 gen_sync_exception(ctx);
5834 #endif
5835 }
5836
5837 /* XXX: not implemented on 440 ? */
5838 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5839 {
5840 #if defined(CONFIG_USER_ONLY)
5841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5842 #else
5843 if (unlikely(!ctx->mem_idx)) {
5844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5845 return;
5846 }
5847 /* Restore CPU state */
5848 gen_helper_rfmci();
5849 gen_sync_exception(ctx);
5850 #endif
5851 }
5852
5853 /* TLB management - PowerPC 405 implementation */
5854 /* tlbre */
5855 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5856 {
5857 #if defined(CONFIG_USER_ONLY)
5858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5859 #else
5860 if (unlikely(!ctx->mem_idx)) {
5861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5862 return;
5863 }
5864 switch (rB(ctx->opcode)) {
5865 case 0:
5866 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5867 break;
5868 case 1:
5869 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5870 break;
5871 default:
5872 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5873 break;
5874 }
5875 #endif
5876 }
5877
5878 /* tlbsx - tlbsx. */
5879 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5880 {
5881 #if defined(CONFIG_USER_ONLY)
5882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5883 #else
5884 TCGv t0;
5885 if (unlikely(!ctx->mem_idx)) {
5886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5887 return;
5888 }
5889 t0 = tcg_temp_new();
5890 gen_addr_reg_index(ctx, t0);
5891 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5892 tcg_temp_free(t0);
5893 if (Rc(ctx->opcode)) {
5894 int l1 = gen_new_label();
5895 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5896 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5897 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5898 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5899 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5900 gen_set_label(l1);
5901 }
5902 #endif
5903 }
5904
5905 /* tlbwe */
5906 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5907 {
5908 #if defined(CONFIG_USER_ONLY)
5909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5910 #else
5911 if (unlikely(!ctx->mem_idx)) {
5912 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5913 return;
5914 }
5915 switch (rB(ctx->opcode)) {
5916 case 0:
5917 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5918 break;
5919 case 1:
5920 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5921 break;
5922 default:
5923 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5924 break;
5925 }
5926 #endif
5927 }
5928
5929 /* TLB management - PowerPC 440 implementation */
5930 /* tlbre */
5931 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5932 {
5933 #if defined(CONFIG_USER_ONLY)
5934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5935 #else
5936 if (unlikely(!ctx->mem_idx)) {
5937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5938 return;
5939 }
5940 switch (rB(ctx->opcode)) {
5941 case 0:
5942 case 1:
5943 case 2:
5944 {
5945 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5946 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5947 tcg_temp_free_i32(t0);
5948 }
5949 break;
5950 default:
5951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5952 break;
5953 }
5954 #endif
5955 }
5956
5957 /* tlbsx - tlbsx. */
5958 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5959 {
5960 #if defined(CONFIG_USER_ONLY)
5961 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5962 #else
5963 TCGv t0;
5964 if (unlikely(!ctx->mem_idx)) {
5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5966 return;
5967 }
5968 t0 = tcg_temp_new();
5969 gen_addr_reg_index(ctx, t0);
5970 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5971 tcg_temp_free(t0);
5972 if (Rc(ctx->opcode)) {
5973 int l1 = gen_new_label();
5974 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5975 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5976 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5977 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5978 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5979 gen_set_label(l1);
5980 }
5981 #endif
5982 }
5983
5984 /* tlbwe */
5985 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5986 {
5987 #if defined(CONFIG_USER_ONLY)
5988 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5989 #else
5990 if (unlikely(!ctx->mem_idx)) {
5991 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5992 return;
5993 }
5994 switch (rB(ctx->opcode)) {
5995 case 0:
5996 case 1:
5997 case 2:
5998 {
5999 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6000 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6001 tcg_temp_free_i32(t0);
6002 }
6003 break;
6004 default:
6005 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6006 break;
6007 }
6008 #endif
6009 }
6010
6011 /* wrtee */
6012 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6013 {
6014 #if defined(CONFIG_USER_ONLY)
6015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6016 #else
6017 TCGv t0;
6018 if (unlikely(!ctx->mem_idx)) {
6019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6020 return;
6021 }
6022 t0 = tcg_temp_new();
6023 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6024 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6025 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6026 tcg_temp_free(t0);
6027 /* Stop translation to have a chance to raise an exception
6028 * if we just set msr_ee to 1
6029 */
6030 gen_stop_exception(ctx);
6031 #endif
6032 }
6033
6034 /* wrteei */
6035 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6036 {
6037 #if defined(CONFIG_USER_ONLY)
6038 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6039 #else
6040 if (unlikely(!ctx->mem_idx)) {
6041 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6042 return;
6043 }
6044 if (ctx->opcode & 0x00010000) {
6045 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6046 /* Stop translation to have a chance to raise an exception */
6047 gen_stop_exception(ctx);
6048 } else {
6049 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6050 }
6051 #endif
6052 }
6053
6054 /* PowerPC 440 specific instructions */
6055 /* dlmzb */
6056 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6057 {
6058 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6059 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6060 cpu_gpr[rB(ctx->opcode)], t0);
6061 tcg_temp_free_i32(t0);
6062 }
6063
6064 /* mbar replaces eieio on 440 */
6065 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
6066 {
6067 /* interpreted as no-op */
6068 }
6069
6070 /* msync replaces sync on 440 */
6071 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6072 {
6073 /* interpreted as no-op */
6074 }
6075
6076 /* icbt */
6077 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6078 {
6079 /* interpreted as no-op */
6080 /* XXX: specification say this is treated as a load by the MMU
6081 * but does not generate any exception
6082 */
6083 }
6084
6085 /*** Altivec vector extension ***/
6086 /* Altivec registers moves */
6087
6088 static always_inline TCGv_ptr gen_avr_ptr(int reg)
6089 {
6090 TCGv_ptr r = tcg_temp_new_ptr();
6091 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6092 return r;
6093 }
6094
6095 #define GEN_VR_LDX(name, opc2, opc3) \
6096 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6097 { \
6098 TCGv EA; \
6099 if (unlikely(!ctx->altivec_enabled)) { \
6100 gen_exception(ctx, POWERPC_EXCP_VPU); \
6101 return; \
6102 } \
6103 gen_set_access_type(ctx, ACCESS_INT); \
6104 EA = tcg_temp_new(); \
6105 gen_addr_reg_index(ctx, EA); \
6106 tcg_gen_andi_tl(EA, EA, ~0xf); \
6107 if (ctx->le_mode) { \
6108 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6109 tcg_gen_addi_tl(EA, EA, 8); \
6110 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6111 } else { \
6112 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6113 tcg_gen_addi_tl(EA, EA, 8); \
6114 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6115 } \
6116 tcg_temp_free(EA); \
6117 }
6118
6119 #define GEN_VR_STX(name, opc2, opc3) \
6120 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6121 { \
6122 TCGv EA; \
6123 if (unlikely(!ctx->altivec_enabled)) { \
6124 gen_exception(ctx, POWERPC_EXCP_VPU); \
6125 return; \
6126 } \
6127 gen_set_access_type(ctx, ACCESS_INT); \
6128 EA = tcg_temp_new(); \
6129 gen_addr_reg_index(ctx, EA); \
6130 tcg_gen_andi_tl(EA, EA, ~0xf); \
6131 if (ctx->le_mode) { \
6132 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6133 tcg_gen_addi_tl(EA, EA, 8); \
6134 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6135 } else { \
6136 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6137 tcg_gen_addi_tl(EA, EA, 8); \
6138 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6139 } \
6140 tcg_temp_free(EA); \
6141 }
6142
6143 GEN_VR_LDX(lvx, 0x07, 0x03);
6144 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6145 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6146
6147 GEN_VR_STX(svx, 0x07, 0x07);
6148 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6149 GEN_VR_STX(svxl, 0x07, 0x0F);
6150
6151 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6152 {
6153 TCGv_ptr rd;
6154 TCGv EA;
6155 if (unlikely(!ctx->altivec_enabled)) {
6156 gen_exception(ctx, POWERPC_EXCP_VPU);
6157 return;
6158 }
6159 EA = tcg_temp_new();
6160 gen_addr_reg_index(ctx, EA);
6161 rd = gen_avr_ptr(rD(ctx->opcode));
6162 gen_helper_lvsl(rd, EA);
6163 tcg_temp_free(EA);
6164 tcg_temp_free_ptr(rd);
6165 }
6166
6167 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6168 {
6169 TCGv_ptr rd;
6170 TCGv EA;
6171 if (unlikely(!ctx->altivec_enabled)) {
6172 gen_exception(ctx, POWERPC_EXCP_VPU);
6173 return;
6174 }
6175 EA = tcg_temp_new();
6176 gen_addr_reg_index(ctx, EA);
6177 rd = gen_avr_ptr(rD(ctx->opcode));
6178 gen_helper_lvsr(rd, EA);
6179 tcg_temp_free(EA);
6180 tcg_temp_free_ptr(rd);
6181 }
6182
6183 /* Logical operations */
6184 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6185 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6186 { \
6187 if (unlikely(!ctx->altivec_enabled)) { \
6188 gen_exception(ctx, POWERPC_EXCP_VPU); \
6189 return; \
6190 } \
6191 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6192 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6193 }
6194
6195 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6196 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6197 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6198 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6199 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6200
6201 #define GEN_VXFORM(name, opc2, opc3) \
6202 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6203 { \
6204 TCGv_ptr ra, rb, rd; \
6205 if (unlikely(!ctx->altivec_enabled)) { \
6206 gen_exception(ctx, POWERPC_EXCP_VPU); \
6207 return; \
6208 } \
6209 ra = gen_avr_ptr(rA(ctx->opcode)); \
6210 rb = gen_avr_ptr(rB(ctx->opcode)); \
6211 rd = gen_avr_ptr(rD(ctx->opcode)); \
6212 gen_helper_##name (rd, ra, rb); \
6213 tcg_temp_free_ptr(ra); \
6214 tcg_temp_free_ptr(rb); \
6215 tcg_temp_free_ptr(rd); \
6216 }
6217
6218 GEN_VXFORM(vaddubm, 0, 0);
6219 GEN_VXFORM(vadduhm, 0, 1);
6220 GEN_VXFORM(vadduwm, 0, 2);
6221 GEN_VXFORM(vsububm, 0, 16);
6222 GEN_VXFORM(vsubuhm, 0, 17);
6223 GEN_VXFORM(vsubuwm, 0, 18);
6224 GEN_VXFORM(vmaxub, 1, 0);
6225 GEN_VXFORM(vmaxuh, 1, 1);
6226 GEN_VXFORM(vmaxuw, 1, 2);
6227 GEN_VXFORM(vmaxsb, 1, 4);
6228 GEN_VXFORM(vmaxsh, 1, 5);
6229 GEN_VXFORM(vmaxsw, 1, 6);
6230 GEN_VXFORM(vminub, 1, 8);
6231 GEN_VXFORM(vminuh, 1, 9);
6232 GEN_VXFORM(vminuw, 1, 10);
6233 GEN_VXFORM(vminsb, 1, 12);
6234 GEN_VXFORM(vminsh, 1, 13);
6235 GEN_VXFORM(vminsw, 1, 14);
6236 GEN_VXFORM(vavgub, 1, 16);
6237 GEN_VXFORM(vavguh, 1, 17);
6238 GEN_VXFORM(vavguw, 1, 18);
6239 GEN_VXFORM(vavgsb, 1, 20);
6240 GEN_VXFORM(vavgsh, 1, 21);
6241 GEN_VXFORM(vavgsw, 1, 22);
6242 GEN_VXFORM(vmrghb, 6, 0);
6243 GEN_VXFORM(vmrghh, 6, 1);
6244 GEN_VXFORM(vmrghw, 6, 2);
6245 GEN_VXFORM(vmrglb, 6, 4);
6246 GEN_VXFORM(vmrglh, 6, 5);
6247 GEN_VXFORM(vmrglw, 6, 6);
6248 GEN_VXFORM(vmuloub, 4, 0);
6249 GEN_VXFORM(vmulouh, 4, 1);
6250 GEN_VXFORM(vmulosb, 4, 4);
6251 GEN_VXFORM(vmulosh, 4, 5);
6252 GEN_VXFORM(vmuleub, 4, 8);
6253 GEN_VXFORM(vmuleuh, 4, 9);
6254 GEN_VXFORM(vmulesb, 4, 12);
6255 GEN_VXFORM(vmulesh, 4, 13);
6256 GEN_VXFORM(vslb, 2, 4);
6257 GEN_VXFORM(vslh, 2, 5);
6258 GEN_VXFORM(vslw, 2, 6);
6259 GEN_VXFORM(vsrb, 2, 8);
6260 GEN_VXFORM(vsrh, 2, 9);
6261 GEN_VXFORM(vsrw, 2, 10);
6262 GEN_VXFORM(vsrab, 2, 12);
6263 GEN_VXFORM(vsrah, 2, 13);
6264 GEN_VXFORM(vsraw, 2, 14);
6265 GEN_VXFORM(vslo, 6, 16);
6266 GEN_VXFORM(vsro, 6, 17);
6267 GEN_VXFORM(vaddcuw, 0, 6);
6268 GEN_VXFORM(vsubcuw, 0, 22);
6269 GEN_VXFORM(vrlb, 2, 0);
6270 GEN_VXFORM(vrlh, 2, 1);
6271 GEN_VXFORM(vrlw, 2, 2);
6272
6273 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6274 {
6275 TCGv_ptr ra, rb, rd;
6276 TCGv sh;
6277 if (unlikely(!ctx->altivec_enabled)) {
6278 gen_exception(ctx, POWERPC_EXCP_VPU);
6279 return;
6280 }
6281 ra = gen_avr_ptr(rA(ctx->opcode));
6282 rb = gen_avr_ptr(rB(ctx->opcode));
6283 rd = gen_avr_ptr(rD(ctx->opcode));
6284 sh = tcg_const_i32(VSH(ctx->opcode));
6285 gen_helper_vsldoi (rd, ra, rb, sh);
6286 tcg_temp_free_ptr(ra);
6287 tcg_temp_free_ptr(rb);
6288 tcg_temp_free_ptr(rd);
6289 tcg_temp_free(sh);
6290 }
6291
6292 /*** SPE extension ***/
6293 /* Register moves */
6294
6295 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6296 #if defined(TARGET_PPC64)
6297 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6298 #else
6299 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6300 #endif
6301 }
6302
6303 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6304 #if defined(TARGET_PPC64)
6305 tcg_gen_mov_i64(cpu_gpr[reg], t);
6306 #else
6307 TCGv_i64 tmp = tcg_temp_new_i64();
6308 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6309 tcg_gen_shri_i64(tmp, t, 32);
6310 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6311 tcg_temp_free_i64(tmp);
6312 #endif
6313 }
6314
6315 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6316 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6317 { \
6318 if (Rc(ctx->opcode)) \
6319 gen_##name1(ctx); \
6320 else \
6321 gen_##name0(ctx); \
6322 }
6323
6324 /* Handler for undefined SPE opcodes */
6325 static always_inline void gen_speundef (DisasContext *ctx)
6326 {
6327 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6328 }
6329
6330 /* SPE logic */
6331 #if defined(TARGET_PPC64)
6332 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6333 static always_inline void gen_##name (DisasContext *ctx) \
6334 { \
6335 if (unlikely(!ctx->spe_enabled)) { \
6336 gen_exception(ctx, POWERPC_EXCP_APU); \
6337 return; \
6338 } \
6339 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6340 cpu_gpr[rB(ctx->opcode)]); \
6341 }
6342 #else
6343 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6344 static always_inline void gen_##name (DisasContext *ctx) \
6345 { \
6346 if (unlikely(!ctx->spe_enabled)) { \
6347 gen_exception(ctx, POWERPC_EXCP_APU); \
6348 return; \
6349 } \
6350 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6351 cpu_gpr[rB(ctx->opcode)]); \
6352 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6353 cpu_gprh[rB(ctx->opcode)]); \
6354 }
6355 #endif
6356
6357 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6358 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6359 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6360 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6361 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6362 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6363 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6364 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6365
6366 /* SPE logic immediate */
6367 #if defined(TARGET_PPC64)
6368 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6369 static always_inline void gen_##name (DisasContext *ctx) \
6370 { \
6371 if (unlikely(!ctx->spe_enabled)) { \
6372 gen_exception(ctx, POWERPC_EXCP_APU); \
6373 return; \
6374 } \
6375 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6376 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6377 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6378 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6379 tcg_opi(t0, t0, rB(ctx->opcode)); \
6380 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6381 tcg_gen_trunc_i64_i32(t1, t2); \
6382 tcg_temp_free_i64(t2); \
6383 tcg_opi(t1, t1, rB(ctx->opcode)); \
6384 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6385 tcg_temp_free_i32(t0); \
6386 tcg_temp_free_i32(t1); \
6387 }
6388 #else
6389 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6390 static always_inline void gen_##name (DisasContext *ctx) \
6391 { \
6392 if (unlikely(!ctx->spe_enabled)) { \
6393 gen_exception(ctx, POWERPC_EXCP_APU); \
6394 return; \
6395 } \
6396 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6397 rB(ctx->opcode)); \
6398 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6399 rB(ctx->opcode)); \
6400 }
6401 #endif
6402 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6403 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6404 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6405 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6406
6407 /* SPE arithmetic */
6408 #if defined(TARGET_PPC64)
6409 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6410 static always_inline void gen_##name (DisasContext *ctx) \
6411 { \
6412 if (unlikely(!ctx->spe_enabled)) { \
6413 gen_exception(ctx, POWERPC_EXCP_APU); \
6414 return; \
6415 } \
6416 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6417 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6418 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6419 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6420 tcg_op(t0, t0); \
6421 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6422 tcg_gen_trunc_i64_i32(t1, t2); \
6423 tcg_temp_free_i64(t2); \
6424 tcg_op(t1, t1); \
6425 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6426 tcg_temp_free_i32(t0); \
6427 tcg_temp_free_i32(t1); \
6428 }
6429 #else
6430 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6431 static always_inline void gen_##name (DisasContext *ctx) \
6432 { \
6433 if (unlikely(!ctx->spe_enabled)) { \
6434 gen_exception(ctx, POWERPC_EXCP_APU); \
6435 return; \
6436 } \
6437 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6438 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6439 }
6440 #endif
6441
6442 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6443 {
6444 int l1 = gen_new_label();
6445 int l2 = gen_new_label();
6446
6447 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6448 tcg_gen_neg_i32(ret, arg1);
6449 tcg_gen_br(l2);
6450 gen_set_label(l1);
6451 tcg_gen_mov_i32(ret, arg1);
6452 gen_set_label(l2);
6453 }
6454 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6455 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6456 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6457 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6458 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6459 {
6460 tcg_gen_addi_i32(ret, arg1, 0x8000);
6461 tcg_gen_ext16u_i32(ret, ret);
6462 }
6463 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6464 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6465 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6466
6467 #if defined(TARGET_PPC64)
6468 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6469 static always_inline void gen_##name (DisasContext *ctx) \
6470 { \
6471 if (unlikely(!ctx->spe_enabled)) { \
6472 gen_exception(ctx, POWERPC_EXCP_APU); \
6473 return; \
6474 } \
6475 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6476 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6477 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6478 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6479 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6480 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6481 tcg_op(t0, t0, t2); \
6482 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6483 tcg_gen_trunc_i64_i32(t1, t3); \
6484 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6485 tcg_gen_trunc_i64_i32(t2, t3); \
6486 tcg_temp_free_i64(t3); \
6487 tcg_op(t1, t1, t2); \
6488 tcg_temp_free_i32(t2); \
6489 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6490 tcg_temp_free_i32(t0); \
6491 tcg_temp_free_i32(t1); \
6492 }
6493 #else
6494 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6495 static always_inline void gen_##name (DisasContext *ctx) \
6496 { \
6497 if (unlikely(!ctx->spe_enabled)) { \
6498 gen_exception(ctx, POWERPC_EXCP_APU); \
6499 return; \
6500 } \
6501 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6502 cpu_gpr[rB(ctx->opcode)]); \
6503 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6504 cpu_gprh[rB(ctx->opcode)]); \
6505 }
6506 #endif
6507
6508 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6509 {
6510 TCGv_i32 t0;
6511 int l1, l2;
6512
6513 l1 = gen_new_label();
6514 l2 = gen_new_label();
6515 t0 = tcg_temp_local_new_i32();
6516 /* No error here: 6 bits are used */
6517 tcg_gen_andi_i32(t0, arg2, 0x3F);
6518 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6519 tcg_gen_shr_i32(ret, arg1, t0);
6520 tcg_gen_br(l2);
6521 gen_set_label(l1);
6522 tcg_gen_movi_i32(ret, 0);
6523 tcg_gen_br(l2);
6524 tcg_temp_free_i32(t0);
6525 }
6526 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6527 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6528 {
6529 TCGv_i32 t0;
6530 int l1, l2;
6531
6532 l1 = gen_new_label();
6533 l2 = gen_new_label();
6534 t0 = tcg_temp_local_new_i32();
6535 /* No error here: 6 bits are used */
6536 tcg_gen_andi_i32(t0, arg2, 0x3F);
6537 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6538 tcg_gen_sar_i32(ret, arg1, t0);
6539 tcg_gen_br(l2);
6540 gen_set_label(l1);
6541 tcg_gen_movi_i32(ret, 0);
6542 tcg_gen_br(l2);
6543 tcg_temp_free_i32(t0);
6544 }
6545 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6546 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6547 {
6548 TCGv_i32 t0;
6549 int l1, l2;
6550
6551 l1 = gen_new_label();
6552 l2 = gen_new_label();
6553 t0 = tcg_temp_local_new_i32();
6554 /* No error here: 6 bits are used */
6555 tcg_gen_andi_i32(t0, arg2, 0x3F);
6556 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6557 tcg_gen_shl_i32(ret, arg1, t0);
6558 tcg_gen_br(l2);
6559 gen_set_label(l1);
6560 tcg_gen_movi_i32(ret, 0);
6561 tcg_gen_br(l2);
6562 tcg_temp_free_i32(t0);
6563 }
6564 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6565 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6566 {
6567 TCGv_i32 t0 = tcg_temp_new_i32();
6568 tcg_gen_andi_i32(t0, arg2, 0x1F);
6569 tcg_gen_rotl_i32(ret, arg1, t0);
6570 tcg_temp_free_i32(t0);
6571 }
6572 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6573 static always_inline void gen_evmergehi (DisasContext *ctx)
6574 {
6575 if (unlikely(!ctx->spe_enabled)) {
6576 gen_exception(ctx, POWERPC_EXCP_APU);
6577 return;
6578 }
6579 #if defined(TARGET_PPC64)
6580 TCGv t0 = tcg_temp_new();
6581 TCGv t1 = tcg_temp_new();
6582 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6583 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6584 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6585 tcg_temp_free(t0);
6586 tcg_temp_free(t1);
6587 #else
6588 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6589 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6590 #endif
6591 }
6592 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6593 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6594 {
6595 tcg_gen_sub_i32(ret, arg2, arg1);
6596 }
6597 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6598
6599 /* SPE arithmetic immediate */
6600 #if defined(TARGET_PPC64)
6601 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6602 static always_inline void gen_##name (DisasContext *ctx) \
6603 { \
6604 if (unlikely(!ctx->spe_enabled)) { \
6605 gen_exception(ctx, POWERPC_EXCP_APU); \
6606 return; \
6607 } \
6608 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6609 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6610 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6611 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6612 tcg_op(t0, t0, rA(ctx->opcode)); \
6613 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6614 tcg_gen_trunc_i64_i32(t1, t2); \
6615 tcg_temp_free_i64(t2); \
6616 tcg_op(t1, t1, rA(ctx->opcode)); \
6617 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6618 tcg_temp_free_i32(t0); \
6619 tcg_temp_free_i32(t1); \
6620 }
6621 #else
6622 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6623 static always_inline void gen_##name (DisasContext *ctx) \
6624 { \
6625 if (unlikely(!ctx->spe_enabled)) { \
6626 gen_exception(ctx, POWERPC_EXCP_APU); \
6627 return; \
6628 } \
6629 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6630 rA(ctx->opcode)); \
6631 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6632 rA(ctx->opcode)); \
6633 }
6634 #endif
6635 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6636 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6637
6638 /* SPE comparison */
6639 #if defined(TARGET_PPC64)
6640 #define GEN_SPEOP_COMP(name, tcg_cond) \
6641 static always_inline void gen_##name (DisasContext *ctx) \
6642 { \
6643 if (unlikely(!ctx->spe_enabled)) { \
6644 gen_exception(ctx, POWERPC_EXCP_APU); \
6645 return; \
6646 } \
6647 int l1 = gen_new_label(); \
6648 int l2 = gen_new_label(); \
6649 int l3 = gen_new_label(); \
6650 int l4 = gen_new_label(); \
6651 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6652 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6653 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6654 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6655 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6656 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6657 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6658 tcg_gen_br(l2); \
6659 gen_set_label(l1); \
6660 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6661 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6662 gen_set_label(l2); \
6663 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6664 tcg_gen_trunc_i64_i32(t0, t2); \
6665 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6666 tcg_gen_trunc_i64_i32(t1, t2); \
6667 tcg_temp_free_i64(t2); \
6668 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6669 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6670 ~(CRF_CH | CRF_CH_AND_CL)); \
6671 tcg_gen_br(l4); \
6672 gen_set_label(l3); \
6673 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6674 CRF_CH | CRF_CH_OR_CL); \
6675 gen_set_label(l4); \
6676 tcg_temp_free_i32(t0); \
6677 tcg_temp_free_i32(t1); \
6678 }
6679 #else
6680 #define GEN_SPEOP_COMP(name, tcg_cond) \
6681 static always_inline void gen_##name (DisasContext *ctx) \
6682 { \
6683 if (unlikely(!ctx->spe_enabled)) { \
6684 gen_exception(ctx, POWERPC_EXCP_APU); \
6685 return; \
6686 } \
6687 int l1 = gen_new_label(); \
6688 int l2 = gen_new_label(); \
6689 int l3 = gen_new_label(); \
6690 int l4 = gen_new_label(); \
6691 \
6692 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6693 cpu_gpr[rB(ctx->opcode)], l1); \
6694 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6695 tcg_gen_br(l2); \
6696 gen_set_label(l1); \
6697 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6698 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6699 gen_set_label(l2); \
6700 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6701 cpu_gprh[rB(ctx->opcode)], l3); \
6702 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6703 ~(CRF_CH | CRF_CH_AND_CL)); \
6704 tcg_gen_br(l4); \
6705 gen_set_label(l3); \
6706 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6707 CRF_CH | CRF_CH_OR_CL); \
6708 gen_set_label(l4); \
6709 }
6710 #endif
6711 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6712 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6713 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6714 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6715 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6716
6717 /* SPE misc */
6718 static always_inline void gen_brinc (DisasContext *ctx)
6719 {
6720 /* Note: brinc is usable even if SPE is disabled */
6721 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6722 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6723 }
6724 static always_inline void gen_evmergelo (DisasContext *ctx)
6725 {
6726 if (unlikely(!ctx->spe_enabled)) {
6727 gen_exception(ctx, POWERPC_EXCP_APU);
6728 return;
6729 }
6730 #if defined(TARGET_PPC64)
6731 TCGv t0 = tcg_temp_new();
6732 TCGv t1 = tcg_temp_new();
6733 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6734 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6735 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6736 tcg_temp_free(t0);
6737 tcg_temp_free(t1);
6738 #else
6739 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6740 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6741 #endif
6742 }
6743 static always_inline void gen_evmergehilo (DisasContext *ctx)
6744 {
6745 if (unlikely(!ctx->spe_enabled)) {
6746 gen_exception(ctx, POWERPC_EXCP_APU);
6747 return;
6748 }
6749 #if defined(TARGET_PPC64)
6750 TCGv t0 = tcg_temp_new();
6751 TCGv t1 = tcg_temp_new();
6752 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6753 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6754 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6755 tcg_temp_free(t0);
6756 tcg_temp_free(t1);
6757 #else
6758 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6759 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6760 #endif
6761 }
6762 static always_inline void gen_evmergelohi (DisasContext *ctx)
6763 {
6764 if (unlikely(!ctx->spe_enabled)) {
6765 gen_exception(ctx, POWERPC_EXCP_APU);
6766 return;
6767 }
6768 #if defined(TARGET_PPC64)
6769 TCGv t0 = tcg_temp_new();
6770 TCGv t1 = tcg_temp_new();
6771 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6772 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6773 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6774 tcg_temp_free(t0);
6775 tcg_temp_free(t1);
6776 #else
6777 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6778 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6779 #endif
6780 }
6781 static always_inline void gen_evsplati (DisasContext *ctx)
6782 {
6783 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
6784
6785 #if defined(TARGET_PPC64)
6786 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6787 #else
6788 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6789 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6790 #endif
6791 }
6792 static always_inline void gen_evsplatfi (DisasContext *ctx)
6793 {
6794 uint64_t imm = rA(ctx->opcode) << 11;
6795
6796 #if defined(TARGET_PPC64)
6797 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6798 #else
6799 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6800 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6801 #endif
6802 }
6803
6804 static always_inline void gen_evsel (DisasContext *ctx)
6805 {
6806 int l1 = gen_new_label();
6807 int l2 = gen_new_label();
6808 int l3 = gen_new_label();
6809 int l4 = gen_new_label();
6810 TCGv_i32 t0 = tcg_temp_local_new_i32();
6811 #if defined(TARGET_PPC64)
6812 TCGv t1 = tcg_temp_local_new();
6813 TCGv t2 = tcg_temp_local_new();
6814 #endif
6815 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6816 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6817 #if defined(TARGET_PPC64)
6818 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6819 #else
6820 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6821 #endif
6822 tcg_gen_br(l2);
6823 gen_set_label(l1);
6824 #if defined(TARGET_PPC64)
6825 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6826 #else
6827 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6828 #endif
6829 gen_set_label(l2);
6830 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6831 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6832 #if defined(TARGET_PPC64)
6833 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6834 #else
6835 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6836 #endif
6837 tcg_gen_br(l4);
6838 gen_set_label(l3);
6839 #if defined(TARGET_PPC64)
6840 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6841 #else
6842 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6843 #endif
6844 gen_set_label(l4);
6845 tcg_temp_free_i32(t0);
6846 #if defined(TARGET_PPC64)
6847 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6848 tcg_temp_free(t1);
6849 tcg_temp_free(t2);
6850 #endif
6851 }
6852 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6853 {
6854 gen_evsel(ctx);
6855 }
6856 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6857 {
6858 gen_evsel(ctx);
6859 }
6860 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6861 {
6862 gen_evsel(ctx);
6863 }
6864 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6865 {
6866 gen_evsel(ctx);
6867 }
6868
6869 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6870 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6871 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6872 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6873 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6874 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6875 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6876 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6877 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6878 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6879 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6880 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6881 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6882 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6883 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6884 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6885 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6886 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6887 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6888 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6889 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6890 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6891 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6892 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6893 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6894
6895 /* SPE load and stores */
6896 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6897 {
6898 target_ulong uimm = rB(ctx->opcode);
6899
6900 if (rA(ctx->opcode) == 0) {
6901 tcg_gen_movi_tl(EA, uimm << sh);
6902 } else {
6903 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
6904 #if defined(TARGET_PPC64)
6905 if (!ctx->sf_mode) {
6906 tcg_gen_ext32u_tl(EA, EA);
6907 }
6908 #endif
6909 }
6910 }
6911
6912 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6913 {
6914 #if defined(TARGET_PPC64)
6915 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6916 #else
6917 TCGv_i64 t0 = tcg_temp_new_i64();
6918 gen_qemu_ld64(ctx, t0, addr);
6919 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6920 tcg_gen_shri_i64(t0, t0, 32);
6921 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6922 tcg_temp_free_i64(t0);
6923 #endif
6924 }
6925
6926 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6927 {
6928 #if defined(TARGET_PPC64)
6929 TCGv t0 = tcg_temp_new();
6930 gen_qemu_ld32u(ctx, t0, addr);
6931 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6932 gen_addr_add(ctx, addr, addr, 4);
6933 gen_qemu_ld32u(ctx, t0, addr);
6934 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6935 tcg_temp_free(t0);
6936 #else
6937 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
6938 gen_addr_add(ctx, addr, addr, 4);
6939 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6940 #endif
6941 }
6942
6943 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6944 {
6945 TCGv t0 = tcg_temp_new();
6946 #if defined(TARGET_PPC64)
6947 gen_qemu_ld16u(ctx, t0, addr);
6948 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6949 gen_addr_add(ctx, addr, addr, 2);
6950 gen_qemu_ld16u(ctx, t0, addr);
6951 tcg_gen_shli_tl(t0, t0, 32);
6952 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6953 gen_addr_add(ctx, addr, addr, 2);
6954 gen_qemu_ld16u(ctx, t0, addr);
6955 tcg_gen_shli_tl(t0, t0, 16);
6956 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6957 gen_addr_add(ctx, addr, addr, 2);
6958 gen_qemu_ld16u(ctx, t0, addr);
6959 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6960 #else
6961 gen_qemu_ld16u(ctx, t0, addr);
6962 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6963 gen_addr_add(ctx, addr, addr, 2);
6964 gen_qemu_ld16u(ctx, t0, addr);
6965 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6966 gen_addr_add(ctx, addr, addr, 2);
6967 gen_qemu_ld16u(ctx, t0, addr);
6968 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6969 gen_addr_add(ctx, addr, addr, 2);
6970 gen_qemu_ld16u(ctx, t0, addr);
6971 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6972 #endif
6973 tcg_temp_free(t0);
6974 }
6975
6976 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6977 {
6978 TCGv t0 = tcg_temp_new();
6979 gen_qemu_ld16u(ctx, t0, addr);
6980 #if defined(TARGET_PPC64)
6981 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6982 tcg_gen_shli_tl(t0, t0, 16);
6983 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6984 #else
6985 tcg_gen_shli_tl(t0, t0, 16);
6986 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6987 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6988 #endif
6989 tcg_temp_free(t0);
6990 }
6991
6992 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6993 {
6994 TCGv t0 = tcg_temp_new();
6995 gen_qemu_ld16u(ctx, t0, addr);
6996 #if defined(TARGET_PPC64)
6997 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6998 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6999 #else
7000 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7001 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7002 #endif
7003 tcg_temp_free(t0);
7004 }
7005
7006 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7007 {
7008 TCGv t0 = tcg_temp_new();
7009 gen_qemu_ld16s(ctx, t0, addr);
7010 #if defined(TARGET_PPC64)
7011 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7012 tcg_gen_ext32u_tl(t0, t0);
7013 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7014 #else
7015 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7016 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7017 #endif
7018 tcg_temp_free(t0);
7019 }
7020
7021 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7022 {
7023 TCGv t0 = tcg_temp_new();
7024 #if defined(TARGET_PPC64)
7025 gen_qemu_ld16u(ctx, t0, addr);
7026 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7027 gen_addr_add(ctx, addr, addr, 2);
7028 gen_qemu_ld16u(ctx, t0, addr);
7029 tcg_gen_shli_tl(t0, t0, 16);
7030 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7031 #else
7032 gen_qemu_ld16u(ctx, t0, addr);
7033 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7034 gen_addr_add(ctx, addr, addr, 2);
7035 gen_qemu_ld16u(ctx, t0, addr);
7036 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7037 #endif
7038 tcg_temp_free(t0);
7039 }
7040
7041 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7042 {
7043 #if defined(TARGET_PPC64)
7044 TCGv t0 = tcg_temp_new();
7045 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7046 gen_addr_add(ctx, addr, addr, 2);
7047 gen_qemu_ld16u(ctx, t0, addr);
7048 tcg_gen_shli_tl(t0, t0, 32);
7049 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7050 tcg_temp_free(t0);
7051 #else
7052 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7053 gen_addr_add(ctx, addr, addr, 2);
7054 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7055 #endif
7056 }
7057
7058 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7059 {
7060 #if defined(TARGET_PPC64)
7061 TCGv t0 = tcg_temp_new();
7062 gen_qemu_ld16s(ctx, t0, addr);
7063 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7064 gen_addr_add(ctx, addr, addr, 2);
7065 gen_qemu_ld16s(ctx, t0, addr);
7066 tcg_gen_shli_tl(t0, t0, 32);
7067 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7068 tcg_temp_free(t0);
7069 #else
7070 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7071 gen_addr_add(ctx, addr, addr, 2);
7072 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7073 #endif
7074 }
7075
7076 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7077 {
7078 TCGv t0 = tcg_temp_new();
7079 gen_qemu_ld32u(ctx, t0, addr);
7080 #if defined(TARGET_PPC64)
7081 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7082 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7083 #else
7084 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7085 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7086 #endif
7087 tcg_temp_free(t0);
7088 }
7089
7090 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7091 {
7092 TCGv t0 = tcg_temp_new();
7093 #if defined(TARGET_PPC64)
7094 gen_qemu_ld16u(ctx, t0, addr);
7095 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7096 tcg_gen_shli_tl(t0, t0, 32);
7097 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7098 gen_addr_add(ctx, addr, addr, 2);
7099 gen_qemu_ld16u(ctx, t0, addr);
7100 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7101 tcg_gen_shli_tl(t0, t0, 16);
7102 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7103 #else
7104 gen_qemu_ld16u(ctx, t0, addr);
7105 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7106 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7107 gen_addr_add(ctx, addr, addr, 2);
7108 gen_qemu_ld16u(ctx, t0, addr);
7109 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7110 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7111 #endif
7112 tcg_temp_free(t0);
7113 }
7114
7115 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7116 {
7117 #if defined(TARGET_PPC64)
7118 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7119 #else
7120 TCGv_i64 t0 = tcg_temp_new_i64();
7121 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7122 gen_qemu_st64(ctx, t0, addr);
7123 tcg_temp_free_i64(t0);
7124 #endif
7125 }
7126
7127 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7128 {
7129 #if defined(TARGET_PPC64)
7130 TCGv t0 = tcg_temp_new();
7131 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7132 gen_qemu_st32(ctx, t0, addr);
7133 tcg_temp_free(t0);
7134 #else
7135 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7136 #endif
7137 gen_addr_add(ctx, addr, addr, 4);
7138 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7139 }
7140
7141 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7142 {
7143 TCGv t0 = tcg_temp_new();
7144 #if defined(TARGET_PPC64)
7145 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7146 #else
7147 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7148 #endif
7149 gen_qemu_st16(ctx, t0, addr);
7150 gen_addr_add(ctx, addr, addr, 2);
7151 #if defined(TARGET_PPC64)
7152 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7153 gen_qemu_st16(ctx, t0, addr);
7154 #else
7155 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7156 #endif
7157 gen_addr_add(ctx, addr, addr, 2);
7158 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7159 gen_qemu_st16(ctx, t0, addr);
7160 tcg_temp_free(t0);
7161 gen_addr_add(ctx, addr, addr, 2);
7162 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7163 }
7164
7165 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7166 {
7167 TCGv t0 = tcg_temp_new();
7168 #if defined(TARGET_PPC64)
7169 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7170 #else
7171 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7172 #endif
7173 gen_qemu_st16(ctx, t0, addr);
7174 gen_addr_add(ctx, addr, addr, 2);
7175 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7176 gen_qemu_st16(ctx, t0, addr);
7177 tcg_temp_free(t0);
7178 }
7179
7180 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7181 {
7182 #if defined(TARGET_PPC64)
7183 TCGv t0 = tcg_temp_new();
7184 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7185 gen_qemu_st16(ctx, t0, addr);
7186 tcg_temp_free(t0);
7187 #else
7188 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7189 #endif
7190 gen_addr_add(ctx, addr, addr, 2);
7191 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7192 }
7193
7194 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7195 {
7196 #if defined(TARGET_PPC64)
7197 TCGv t0 = tcg_temp_new();
7198 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7199 gen_qemu_st32(ctx, t0, addr);
7200 tcg_temp_free(t0);
7201 #else
7202 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7203 #endif
7204 }
7205
7206 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7207 {
7208 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7209 }
7210
7211 #define GEN_SPEOP_LDST(name, opc2, sh) \
7212 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7213 { \
7214 TCGv t0; \
7215 if (unlikely(!ctx->spe_enabled)) { \
7216 gen_exception(ctx, POWERPC_EXCP_APU); \
7217 return; \
7218 } \
7219 gen_set_access_type(ctx, ACCESS_INT); \
7220 t0 = tcg_temp_new(); \
7221 if (Rc(ctx->opcode)) { \
7222 gen_addr_spe_imm_index(ctx, t0, sh); \
7223 } else { \
7224 gen_addr_reg_index(ctx, t0); \
7225 } \
7226 gen_op_##name(ctx, t0); \
7227 tcg_temp_free(t0); \
7228 }
7229
7230 GEN_SPEOP_LDST(evldd, 0x00, 3);
7231 GEN_SPEOP_LDST(evldw, 0x01, 3);
7232 GEN_SPEOP_LDST(evldh, 0x02, 3);
7233 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7234 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7235 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7236 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7237 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7238 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7239 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7240 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7241
7242 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7243 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7244 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7245 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7246 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7247 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7248 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7249
7250 /* Multiply and add - TODO */
7251 #if 0
7252 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7253 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7254 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7255 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7256 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7257 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7258 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7259 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7260 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7261 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7262 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7263 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7264
7265 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7266 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7267 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7268 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7269 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7270 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7271 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7272 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7273 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7274 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7275 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7276 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7277 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7278 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7279
7280 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7281 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7282 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7283 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7284 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7285 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7286
7287 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7288 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7289 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7290 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7291 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7292 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7293 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7294 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7295 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7296 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7297 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7298 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7299
7300 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7301 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7302 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7303 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7304 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7305
7306 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7307 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7308 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7309 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7310 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7311 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7312 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7313 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7314 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7315 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7316 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7317 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7318
7319 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7320 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7321 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7322 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7323 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7324 #endif
7325
7326 /*** SPE floating-point extension ***/
7327 #if defined(TARGET_PPC64)
7328 #define GEN_SPEFPUOP_CONV_32_32(name) \
7329 static always_inline void gen_##name (DisasContext *ctx) \
7330 { \
7331 TCGv_i32 t0; \
7332 TCGv t1; \
7333 t0 = tcg_temp_new_i32(); \
7334 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7335 gen_helper_##name(t0, t0); \
7336 t1 = tcg_temp_new(); \
7337 tcg_gen_extu_i32_tl(t1, t0); \
7338 tcg_temp_free_i32(t0); \
7339 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7340 0xFFFFFFFF00000000ULL); \
7341 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7342 tcg_temp_free(t1); \
7343 }
7344 #define GEN_SPEFPUOP_CONV_32_64(name) \
7345 static always_inline void gen_##name (DisasContext *ctx) \
7346 { \
7347 TCGv_i32 t0; \
7348 TCGv t1; \
7349 t0 = tcg_temp_new_i32(); \
7350 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7351 t1 = tcg_temp_new(); \
7352 tcg_gen_extu_i32_tl(t1, t0); \
7353 tcg_temp_free_i32(t0); \
7354 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7355 0xFFFFFFFF00000000ULL); \
7356 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7357 tcg_temp_free(t1); \
7358 }
7359 #define GEN_SPEFPUOP_CONV_64_32(name) \
7360 static always_inline void gen_##name (DisasContext *ctx) \
7361 { \
7362 TCGv_i32 t0 = tcg_temp_new_i32(); \
7363 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7364 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7365 tcg_temp_free_i32(t0); \
7366 }
7367 #define GEN_SPEFPUOP_CONV_64_64(name) \
7368 static always_inline void gen_##name (DisasContext *ctx) \
7369 { \
7370 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7371 }
7372 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7373 static always_inline void gen_##name (DisasContext *ctx) \
7374 { \
7375 TCGv_i32 t0, t1; \
7376 TCGv_i64 t2; \
7377 if (unlikely(!ctx->spe_enabled)) { \
7378 gen_exception(ctx, POWERPC_EXCP_APU); \
7379 return; \
7380 } \
7381 t0 = tcg_temp_new_i32(); \
7382 t1 = tcg_temp_new_i32(); \
7383 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7384 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7385 gen_helper_##name(t0, t0, t1); \
7386 tcg_temp_free_i32(t1); \
7387 t2 = tcg_temp_new(); \
7388 tcg_gen_extu_i32_tl(t2, t0); \
7389 tcg_temp_free_i32(t0); \
7390 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7391 0xFFFFFFFF00000000ULL); \
7392 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7393 tcg_temp_free(t2); \
7394 }
7395 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7396 static always_inline void gen_##name (DisasContext *ctx) \
7397 { \
7398 if (unlikely(!ctx->spe_enabled)) { \
7399 gen_exception(ctx, POWERPC_EXCP_APU); \
7400 return; \
7401 } \
7402 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7403 cpu_gpr[rB(ctx->opcode)]); \
7404 }
7405 #define GEN_SPEFPUOP_COMP_32(name) \
7406 static always_inline void gen_##name (DisasContext *ctx) \
7407 { \
7408 TCGv_i32 t0, t1; \
7409 if (unlikely(!ctx->spe_enabled)) { \
7410 gen_exception(ctx, POWERPC_EXCP_APU); \
7411 return; \
7412 } \
7413 t0 = tcg_temp_new_i32(); \
7414 t1 = tcg_temp_new_i32(); \
7415 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7416 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7417 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7418 tcg_temp_free_i32(t0); \
7419 tcg_temp_free_i32(t1); \
7420 }
7421 #define GEN_SPEFPUOP_COMP_64(name) \
7422 static always_inline void gen_##name (DisasContext *ctx) \
7423 { \
7424 if (unlikely(!ctx->spe_enabled)) { \
7425 gen_exception(ctx, POWERPC_EXCP_APU); \
7426 return; \
7427 } \
7428 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7429 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7430 }
7431 #else
7432 #define GEN_SPEFPUOP_CONV_32_32(name) \
7433 static always_inline void gen_##name (DisasContext *ctx) \
7434 { \
7435 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7436 }
7437 #define GEN_SPEFPUOP_CONV_32_64(name) \
7438 static always_inline void gen_##name (DisasContext *ctx) \
7439 { \
7440 TCGv_i64 t0 = tcg_temp_new_i64(); \
7441 gen_load_gpr64(t0, rB(ctx->opcode)); \
7442 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7443 tcg_temp_free_i64(t0); \
7444 }
7445 #define GEN_SPEFPUOP_CONV_64_32(name) \
7446 static always_inline void gen_##name (DisasContext *ctx) \
7447 { \
7448 TCGv_i64 t0 = tcg_temp_new_i64(); \
7449 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7450 gen_store_gpr64(rD(ctx->opcode), t0); \
7451 tcg_temp_free_i64(t0); \
7452 }
7453 #define GEN_SPEFPUOP_CONV_64_64(name) \
7454 static always_inline void gen_##name (DisasContext *ctx) \
7455 { \
7456 TCGv_i64 t0 = tcg_temp_new_i64(); \
7457 gen_load_gpr64(t0, rB(ctx->opcode)); \
7458 gen_helper_##name(t0, t0); \
7459 gen_store_gpr64(rD(ctx->opcode), t0); \
7460 tcg_temp_free_i64(t0); \
7461 }
7462 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7463 static always_inline void gen_##name (DisasContext *ctx) \
7464 { \
7465 if (unlikely(!ctx->spe_enabled)) { \
7466 gen_exception(ctx, POWERPC_EXCP_APU); \
7467 return; \
7468 } \
7469 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7470 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7471 }
7472 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7473 static always_inline void gen_##name (DisasContext *ctx) \
7474 { \
7475 TCGv_i64 t0, t1; \
7476 if (unlikely(!ctx->spe_enabled)) { \
7477 gen_exception(ctx, POWERPC_EXCP_APU); \
7478 return; \
7479 } \
7480 t0 = tcg_temp_new_i64(); \
7481 t1 = tcg_temp_new_i64(); \
7482 gen_load_gpr64(t0, rA(ctx->opcode)); \
7483 gen_load_gpr64(t1, rB(ctx->opcode)); \
7484 gen_helper_##name(t0, t0, t1); \
7485 gen_store_gpr64(rD(ctx->opcode), t0); \
7486 tcg_temp_free_i64(t0); \
7487 tcg_temp_free_i64(t1); \
7488 }
7489 #define GEN_SPEFPUOP_COMP_32(name) \
7490 static always_inline void gen_##name (DisasContext *ctx) \
7491 { \
7492 if (unlikely(!ctx->spe_enabled)) { \
7493 gen_exception(ctx, POWERPC_EXCP_APU); \
7494 return; \
7495 } \
7496 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7497 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7498 }
7499 #define GEN_SPEFPUOP_COMP_64(name) \
7500 static always_inline void gen_##name (DisasContext *ctx) \
7501 { \
7502 TCGv_i64 t0, t1; \
7503 if (unlikely(!ctx->spe_enabled)) { \
7504 gen_exception(ctx, POWERPC_EXCP_APU); \
7505 return; \
7506 } \
7507 t0 = tcg_temp_new_i64(); \
7508 t1 = tcg_temp_new_i64(); \
7509 gen_load_gpr64(t0, rA(ctx->opcode)); \
7510 gen_load_gpr64(t1, rB(ctx->opcode)); \
7511 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7512 tcg_temp_free_i64(t0); \
7513 tcg_temp_free_i64(t1); \
7514 }
7515 #endif
7516
7517 /* Single precision floating-point vectors operations */
7518 /* Arithmetic */
7519 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7520 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7521 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7522 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7523 static always_inline void gen_evfsabs (DisasContext *ctx)
7524 {
7525 if (unlikely(!ctx->spe_enabled)) {
7526 gen_exception(ctx, POWERPC_EXCP_APU);
7527 return;
7528 }
7529 #if defined(TARGET_PPC64)
7530 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7531 #else
7532 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7533 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7534 #endif
7535 }
7536 static always_inline void gen_evfsnabs (DisasContext *ctx)
7537 {
7538 if (unlikely(!ctx->spe_enabled)) {
7539 gen_exception(ctx, POWERPC_EXCP_APU);
7540 return;
7541 }
7542 #if defined(TARGET_PPC64)
7543 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7544 #else
7545 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7546 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7547 #endif
7548 }
7549 static always_inline void gen_evfsneg (DisasContext *ctx)
7550 {
7551 if (unlikely(!ctx->spe_enabled)) {
7552 gen_exception(ctx, POWERPC_EXCP_APU);
7553 return;
7554 }
7555 #if defined(TARGET_PPC64)
7556 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7557 #else
7558 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7559 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7560 #endif
7561 }
7562
7563 /* Conversion */
7564 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7565 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7566 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7567 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7568 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7569 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7570 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7571 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7572 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7573 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7574
7575 /* Comparison */
7576 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7577 GEN_SPEFPUOP_COMP_64(evfscmplt);
7578 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7579 GEN_SPEFPUOP_COMP_64(evfststgt);
7580 GEN_SPEFPUOP_COMP_64(evfststlt);
7581 GEN_SPEFPUOP_COMP_64(evfststeq);
7582
7583 /* Opcodes definitions */
7584 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7585 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7586 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7587 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7588 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7589 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7590 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7591 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7592 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7593 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7594 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7595 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7596 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7597 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7598
7599 /* Single precision floating-point operations */
7600 /* Arithmetic */
7601 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7602 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7603 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7604 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7605 static always_inline void gen_efsabs (DisasContext *ctx)
7606 {
7607 if (unlikely(!ctx->spe_enabled)) {
7608 gen_exception(ctx, POWERPC_EXCP_APU);
7609 return;
7610 }
7611 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7612 }
7613 static always_inline void gen_efsnabs (DisasContext *ctx)
7614 {
7615 if (unlikely(!ctx->spe_enabled)) {
7616 gen_exception(ctx, POWERPC_EXCP_APU);
7617 return;
7618 }
7619 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7620 }
7621 static always_inline void gen_efsneg (DisasContext *ctx)
7622 {
7623 if (unlikely(!ctx->spe_enabled)) {
7624 gen_exception(ctx, POWERPC_EXCP_APU);
7625 return;
7626 }
7627 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7628 }
7629
7630 /* Conversion */
7631 GEN_SPEFPUOP_CONV_32_32(efscfui);
7632 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7633 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7634 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7635 GEN_SPEFPUOP_CONV_32_32(efsctui);
7636 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7637 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7638 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7639 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7640 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7641 GEN_SPEFPUOP_CONV_32_64(efscfd);
7642
7643 /* Comparison */
7644 GEN_SPEFPUOP_COMP_32(efscmpgt);
7645 GEN_SPEFPUOP_COMP_32(efscmplt);
7646 GEN_SPEFPUOP_COMP_32(efscmpeq);
7647 GEN_SPEFPUOP_COMP_32(efststgt);
7648 GEN_SPEFPUOP_COMP_32(efststlt);
7649 GEN_SPEFPUOP_COMP_32(efststeq);
7650
7651 /* Opcodes definitions */
7652 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
7653 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7654 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7655 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7656 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7657 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7658 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7659 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7660 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7661 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
7662 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7663 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
7664 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7665 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7666
7667 /* Double precision floating-point operations */
7668 /* Arithmetic */
7669 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7670 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7671 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7672 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7673 static always_inline void gen_efdabs (DisasContext *ctx)
7674 {
7675 if (unlikely(!ctx->spe_enabled)) {
7676 gen_exception(ctx, POWERPC_EXCP_APU);
7677 return;
7678 }
7679 #if defined(TARGET_PPC64)
7680 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7681 #else
7682 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7683 #endif
7684 }
7685 static always_inline void gen_efdnabs (DisasContext *ctx)
7686 {
7687 if (unlikely(!ctx->spe_enabled)) {
7688 gen_exception(ctx, POWERPC_EXCP_APU);
7689 return;
7690 }
7691 #if defined(TARGET_PPC64)
7692 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7693 #else
7694 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7695 #endif
7696 }
7697 static always_inline void gen_efdneg (DisasContext *ctx)
7698 {
7699 if (unlikely(!ctx->spe_enabled)) {
7700 gen_exception(ctx, POWERPC_EXCP_APU);
7701 return;
7702 }
7703 #if defined(TARGET_PPC64)
7704 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7705 #else
7706 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7707 #endif
7708 }
7709
7710 /* Conversion */
7711 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7712 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7713 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7714 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7715 GEN_SPEFPUOP_CONV_32_64(efdctui);
7716 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7717 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7718 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7719 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7720 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7721 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7722 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7723 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7724 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7725 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
7726
7727 /* Comparison */
7728 GEN_SPEFPUOP_COMP_64(efdcmpgt);
7729 GEN_SPEFPUOP_COMP_64(efdcmplt);
7730 GEN_SPEFPUOP_COMP_64(efdcmpeq);
7731 GEN_SPEFPUOP_COMP_64(efdtstgt);
7732 GEN_SPEFPUOP_COMP_64(efdtstlt);
7733 GEN_SPEFPUOP_COMP_64(efdtsteq);
7734
7735 /* Opcodes definitions */
7736 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7737 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7738 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7739 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7740 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7741 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7742 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7743 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7744 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7745 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7746 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7747 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7748 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7749 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7750 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7751 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
7752
7753 /* End opcode list */
7754 GEN_OPCODE_MARK(end);
7755
7756 #include "translate_init.c"
7757 #include "helper_regs.h"
7758
7759 /*****************************************************************************/
7760 /* Misc PowerPC helpers */
7761 void cpu_dump_state (CPUState *env, FILE *f,
7762 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7763 int flags)
7764 {
7765 #define RGPL 4
7766 #define RFPL 4
7767
7768 int i;
7769
7770 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
7771 env->nip, env->lr, env->ctr, env->xer);
7772 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7773 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
7774 #if !defined(NO_TIMER_DUMP)
7775 cpu_fprintf(f, "TB %08x %08x "
7776 #if !defined(CONFIG_USER_ONLY)
7777 "DECR %08x"
7778 #endif
7779 "\n",
7780 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7781 #if !defined(CONFIG_USER_ONLY)
7782 , cpu_ppc_load_decr(env)
7783 #endif
7784 );
7785 #endif
7786 for (i = 0; i < 32; i++) {
7787 if ((i & (RGPL - 1)) == 0)
7788 cpu_fprintf(f, "GPR%02d", i);
7789 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
7790 if ((i & (RGPL - 1)) == (RGPL - 1))
7791 cpu_fprintf(f, "\n");
7792 }
7793 cpu_fprintf(f, "CR ");
7794 for (i = 0; i < 8; i++)
7795 cpu_fprintf(f, "%01x", env->crf[i]);
7796 cpu_fprintf(f, " [");
7797 for (i = 0; i < 8; i++) {
7798 char a = '-';
7799 if (env->crf[i] & 0x08)
7800 a = 'L';
7801 else if (env->crf[i] & 0x04)
7802 a = 'G';
7803 else if (env->crf[i] & 0x02)
7804 a = 'E';
7805 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7806 }
7807 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
7808 for (i = 0; i < 32; i++) {
7809 if ((i & (RFPL - 1)) == 0)
7810 cpu_fprintf(f, "FPR%02d", i);
7811 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7812 if ((i & (RFPL - 1)) == (RFPL - 1))
7813 cpu_fprintf(f, "\n");
7814 }
7815 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
7816 #if !defined(CONFIG_USER_ONLY)
7817 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
7818 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
7819 #endif
7820
7821 #undef RGPL
7822 #undef RFPL
7823 }
7824
7825 void cpu_dump_statistics (CPUState *env, FILE*f,
7826 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7827 int flags)
7828 {
7829 #if defined(DO_PPC_STATISTICS)
7830 opc_handler_t **t1, **t2, **t3, *handler;
7831 int op1, op2, op3;
7832
7833 t1 = env->opcodes;
7834 for (op1 = 0; op1 < 64; op1++) {
7835 handler = t1[op1];
7836 if (is_indirect_opcode(handler)) {
7837 t2 = ind_table(handler);
7838 for (op2 = 0; op2 < 32; op2++) {
7839 handler = t2[op2];
7840 if (is_indirect_opcode(handler)) {
7841 t3 = ind_table(handler);
7842 for (op3 = 0; op3 < 32; op3++) {
7843 handler = t3[op3];
7844 if (handler->count == 0)
7845 continue;
7846 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7847 "%016llx %lld\n",
7848 op1, op2, op3, op1, (op3 << 5) | op2,
7849 handler->oname,
7850 handler->count, handler->count);
7851 }
7852 } else {
7853 if (handler->count == 0)
7854 continue;
7855 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7856 "%016llx %lld\n",
7857 op1, op2, op1, op2, handler->oname,
7858 handler->count, handler->count);
7859 }
7860 }
7861 } else {
7862 if (handler->count == 0)
7863 continue;
7864 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7865 op1, op1, handler->oname,
7866 handler->count, handler->count);
7867 }
7868 }
7869 #endif
7870 }
7871
7872 /*****************************************************************************/
7873 static always_inline void gen_intermediate_code_internal (CPUState *env,
7874 TranslationBlock *tb,
7875 int search_pc)
7876 {
7877 DisasContext ctx, *ctxp = &ctx;
7878 opc_handler_t **table, *handler;
7879 target_ulong pc_start;
7880 uint16_t *gen_opc_end;
7881 CPUBreakpoint *bp;
7882 int j, lj = -1;
7883 int num_insns;
7884 int max_insns;
7885
7886 pc_start = tb->pc;
7887 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7888 ctx.nip = pc_start;
7889 ctx.tb = tb;
7890 ctx.exception = POWERPC_EXCP_NONE;
7891 ctx.spr_cb = env->spr_cb;
7892 ctx.mem_idx = env->mmu_idx;
7893 ctx.access_type = -1;
7894 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
7895 #if defined(TARGET_PPC64)
7896 ctx.sf_mode = msr_sf;
7897 #endif
7898 ctx.fpu_enabled = msr_fp;
7899 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7900 ctx.spe_enabled = msr_spe;
7901 else
7902 ctx.spe_enabled = 0;
7903 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7904 ctx.altivec_enabled = msr_vr;
7905 else
7906 ctx.altivec_enabled = 0;
7907 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7908 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7909 else
7910 ctx.singlestep_enabled = 0;
7911 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7912 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7913 if (unlikely(env->singlestep_enabled))
7914 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7915 #if defined (DO_SINGLE_STEP) && 0
7916 /* Single step trace mode */
7917 msr_se = 1;
7918 #endif
7919 num_insns = 0;
7920 max_insns = tb->cflags & CF_COUNT_MASK;
7921 if (max_insns == 0)
7922 max_insns = CF_COUNT_MASK;
7923
7924 gen_icount_start();
7925 /* Set env in case of segfault during code fetch */
7926 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
7927 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7928 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
7929 if (bp->pc == ctx.nip) {
7930 gen_debug_exception(ctxp);
7931 break;
7932 }
7933 }
7934 }
7935 if (unlikely(search_pc)) {
7936 j = gen_opc_ptr - gen_opc_buf;
7937 if (lj < j) {
7938 lj++;
7939 while (lj < j)
7940 gen_opc_instr_start[lj++] = 0;
7941 gen_opc_pc[lj] = ctx.nip;
7942 gen_opc_instr_start[lj] = 1;
7943 gen_opc_icount[lj] = num_insns;
7944 }
7945 }
7946 #if defined PPC_DEBUG_DISAS
7947 if (loglevel & CPU_LOG_TB_IN_ASM) {
7948 fprintf(logfile, "----------------\n");
7949 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
7950 ctx.nip, ctx.mem_idx, (int)msr_ir);
7951 }
7952 #endif
7953 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7954 gen_io_start();
7955 if (unlikely(ctx.le_mode)) {
7956 ctx.opcode = bswap32(ldl_code(ctx.nip));
7957 } else {
7958 ctx.opcode = ldl_code(ctx.nip);
7959 }
7960 #if defined PPC_DEBUG_DISAS
7961 if (loglevel & CPU_LOG_TB_IN_ASM) {
7962 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
7963 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7964 opc3(ctx.opcode), little_endian ? "little" : "big");
7965 }
7966 #endif
7967 ctx.nip += 4;
7968 table = env->opcodes;
7969 num_insns++;
7970 handler = table[opc1(ctx.opcode)];
7971 if (is_indirect_opcode(handler)) {
7972 table = ind_table(handler);
7973 handler = table[opc2(ctx.opcode)];
7974 if (is_indirect_opcode(handler)) {
7975 table = ind_table(handler);
7976 handler = table[opc3(ctx.opcode)];
7977 }
7978 }
7979 /* Is opcode *REALLY* valid ? */
7980 if (unlikely(handler->handler == &gen_invalid)) {
7981 if (loglevel != 0) {
7982 fprintf(logfile, "invalid/unsupported opcode: "
7983 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7984 opc1(ctx.opcode), opc2(ctx.opcode),
7985 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7986 } else {
7987 printf("invalid/unsupported opcode: "
7988 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7989 opc1(ctx.opcode), opc2(ctx.opcode),
7990 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7991 }
7992 } else {
7993 if (unlikely((ctx.opcode & handler->inval) != 0)) {
7994 if (loglevel != 0) {
7995 fprintf(logfile, "invalid bits: %08x for opcode: "
7996 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7997 ctx.opcode & handler->inval, opc1(ctx.opcode),
7998 opc2(ctx.opcode), opc3(ctx.opcode),
7999 ctx.opcode, ctx.nip - 4);
8000 } else {
8001 printf("invalid bits: %08x for opcode: "
8002 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8003 ctx.opcode & handler->inval, opc1(ctx.opcode),
8004 opc2(ctx.opcode), opc3(ctx.opcode),
8005 ctx.opcode, ctx.nip - 4);
8006 }
8007 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
8008 break;
8009 }
8010 }
8011 (*(handler->handler))(&ctx);
8012 #if defined(DO_PPC_STATISTICS)
8013 handler->count++;
8014 #endif
8015 /* Check trace mode exceptions */
8016 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8017 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8018 ctx.exception != POWERPC_SYSCALL &&
8019 ctx.exception != POWERPC_EXCP_TRAP &&
8020 ctx.exception != POWERPC_EXCP_BRANCH)) {
8021 gen_exception(ctxp, POWERPC_EXCP_TRACE);
8022 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
8023 (env->singlestep_enabled) ||
8024 num_insns >= max_insns)) {
8025 /* if we reach a page boundary or are single stepping, stop
8026 * generation
8027 */
8028 break;
8029 }
8030 #if defined (DO_SINGLE_STEP)
8031 break;
8032 #endif
8033 }
8034 if (tb->cflags & CF_LAST_IO)
8035 gen_io_end();
8036 if (ctx.exception == POWERPC_EXCP_NONE) {
8037 gen_goto_tb(&ctx, 0, ctx.nip);
8038 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8039 if (unlikely(env->singlestep_enabled)) {
8040 gen_debug_exception(ctxp);
8041 }
8042 /* Generate the return instruction */
8043 tcg_gen_exit_tb(0);
8044 }
8045 gen_icount_end(tb, num_insns);
8046 *gen_opc_ptr = INDEX_op_end;
8047 if (unlikely(search_pc)) {
8048 j = gen_opc_ptr - gen_opc_buf;
8049 lj++;
8050 while (lj <= j)
8051 gen_opc_instr_start[lj++] = 0;
8052 } else {
8053 tb->size = ctx.nip - pc_start;
8054 tb->icount = num_insns;
8055 }
8056 #if defined(DEBUG_DISAS)
8057 if (loglevel & CPU_LOG_TB_CPU) {
8058 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
8059 cpu_dump_state(env, logfile, fprintf, 0);
8060 }
8061 if (loglevel & CPU_LOG_TB_IN_ASM) {
8062 int flags;
8063 flags = env->bfd_mach;
8064 flags |= ctx.le_mode << 16;
8065 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
8066 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
8067 fprintf(logfile, "\n");
8068 }
8069 #endif
8070 }
8071
8072 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8073 {
8074 gen_intermediate_code_internal(env, tb, 0);
8075 }
8076
8077 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8078 {
8079 gen_intermediate_code_internal(env, tb, 1);
8080 }
8081
8082 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8083 unsigned long searched_pc, int pc_pos, void *puc)
8084 {
8085 env->nip = gen_opc_pc[pc_pos];
8086 }
jz4740 based target emulation