target-sh4: disable debug code
[qemu/qemu-JZ.git] / cache-utils.c
blob7c98144ae5c785ce2290f11feb1031924d4a64f9
1 #include "cache-utils.h"
3 #ifdef __powerpc__
4 struct qemu_cache_conf qemu_cache_conf = {
5 .dcache_bsize = 16,
6 .icache_bsize = 16
7 };
9 #if defined _AIX
10 #include <sys/systemcfg.h>
12 static void ppc_init_cacheline_sizes(void)
14 qemu_cache_conf.icache_bsize = _system_configuration.icache_line;
15 qemu_cache_conf.dcache_bsize = _system_configuration.dcache_line;
18 #elif defined __linux__
20 #define QEMU_AT_NULL 0
21 #define QEMU_AT_DCACHEBSIZE 19
22 #define QEMU_AT_ICACHEBSIZE 20
24 static void ppc_init_cacheline_sizes(char **envp)
26 unsigned long *auxv;
28 while (*envp++);
30 for (auxv = (unsigned long *) envp; *auxv != QEMU_AT_NULL; auxv += 2) {
31 switch (*auxv) {
32 case QEMU_AT_DCACHEBSIZE: qemu_cache_conf.dcache_bsize = auxv[1]; break;
33 case QEMU_AT_ICACHEBSIZE: qemu_cache_conf.icache_bsize = auxv[1]; break;
34 default: break;
39 #elif defined __APPLE__
40 #include <sys/types.h>
41 #include <sys/sysctl.h>
43 static void ppc_init_cacheline_sizes(void)
45 size_t len;
46 unsigned cacheline;
47 int name[2] = { CTL_HW, HW_CACHELINE };
49 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
50 perror("sysctl CTL_HW HW_CACHELINE failed");
51 } else {
52 qemu_cache_conf.dcache_bsize = cacheline;
53 qemu_cache_conf.icache_bsize = cacheline;
56 #endif
58 #ifdef __linux__
59 void qemu_cache_utils_init(char **envp)
61 ppc_init_cacheline_sizes(envp);
63 #else
64 void qemu_cache_utils_init(char **envp)
66 (void) envp;
67 ppc_init_cacheline_sizes();
69 #endif
71 #endif /* __powerpc__ */