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Add support for tap vectored send
[qemu/qemu-JZ.git] / hw / pxa2xx_lcd.c
blobffe7a56ad31b32925a95c1d14fa53984ffa0be5e
1 /*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
8 */
9
10 #include "hw.h"
11 #include "console.h"
12 #include "pxa.h"
13 #include "pixel_ops.h"
14 /* FIXME: For graphic_rotate. Should probably be done in common code. */
15 #include "sysemu.h"
16
17 typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int);
18
19 struct pxa2xx_lcdc_s {
20 qemu_irq irq;
21 int irqlevel;
22
23 int invalidated;
24 DisplayState *ds;
25 QEMUConsole *console;
26 drawfn *line_fn[2];
27 int dest_width;
28 int xres, yres;
29 int pal_for;
30 int transp;
31 enum {
32 pxa_lcdc_2bpp = 1,
33 pxa_lcdc_4bpp = 2,
34 pxa_lcdc_8bpp = 3,
35 pxa_lcdc_16bpp = 4,
36 pxa_lcdc_18bpp = 5,
37 pxa_lcdc_18pbpp = 6,
38 pxa_lcdc_19bpp = 7,
39 pxa_lcdc_19pbpp = 8,
40 pxa_lcdc_24bpp = 9,
41 pxa_lcdc_25bpp = 10,
42 } bpp;
43
44 uint32_t control[6];
45 uint32_t status[2];
46 uint32_t ovl1c[2];
47 uint32_t ovl2c[2];
48 uint32_t ccr;
49 uint32_t cmdcr;
50 uint32_t trgbr;
51 uint32_t tcr;
52 uint32_t liidr;
53 uint8_t bscntr;
54
55 struct {
56 target_phys_addr_t branch;
57 int up;
58 uint8_t palette[1024];
59 uint8_t pbuffer[1024];
60 void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb,
61 int *miny, int *maxy);
62
63 target_phys_addr_t descriptor;
64 target_phys_addr_t source;
65 uint32_t id;
66 uint32_t command;
67 } dma_ch[7];
68
69 qemu_irq vsync_cb;
70 int orientation;
71 };
72
73 struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
74 uint32_t fdaddr;
75 uint32_t fsaddr;
76 uint32_t fidr;
77 uint32_t ldcmd;
78 };
79
80 #define LCCR0 0x000 /* LCD Controller Control register 0 */
81 #define LCCR1 0x004 /* LCD Controller Control register 1 */
82 #define LCCR2 0x008 /* LCD Controller Control register 2 */
83 #define LCCR3 0x00c /* LCD Controller Control register 3 */
84 #define LCCR4 0x010 /* LCD Controller Control register 4 */
85 #define LCCR5 0x014 /* LCD Controller Control register 5 */
86
87 #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
88 #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
89 #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
90 #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
91 #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
92 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
93 #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
94
95 #define LCSR1 0x034 /* LCD Controller Status register 1 */
96 #define LCSR0 0x038 /* LCD Controller Status register 0 */
97 #define LIIDR 0x03c /* LCD Controller Interrupt ID register */
98
99 #define TRGBR 0x040 /* TMED RGB Seed register */
100 #define TCR 0x044 /* TMED Control register */
101
102 #define OVL1C1 0x050 /* Overlay 1 Control register 1 */
103 #define OVL1C2 0x060 /* Overlay 1 Control register 2 */
104 #define OVL2C1 0x070 /* Overlay 2 Control register 1 */
105 #define OVL2C2 0x080 /* Overlay 2 Control register 2 */
106 #define CCR 0x090 /* Cursor Control register */
107
108 #define CMDCR 0x100 /* Command Control register */
109 #define PRSR 0x104 /* Panel Read Status register */
110
111 #define PXA_LCDDMA_CHANS 7
112 #define DMA_FDADR 0x00 /* Frame Descriptor Address register */
113 #define DMA_FSADR 0x04 /* Frame Source Address register */
114 #define DMA_FIDR 0x08 /* Frame ID register */
115 #define DMA_LDCMD 0x0c /* Command register */
116
117 /* LCD Buffer Strength Control register */
118 #define BSCNTR 0x04000054
119
120 /* Bitfield masks */
121 #define LCCR0_ENB (1 << 0)
122 #define LCCR0_CMS (1 << 1)
123 #define LCCR0_SDS (1 << 2)
124 #define LCCR0_LDM (1 << 3)
125 #define LCCR0_SOFM0 (1 << 4)
126 #define LCCR0_IUM (1 << 5)
127 #define LCCR0_EOFM0 (1 << 6)
128 #define LCCR0_PAS (1 << 7)
129 #define LCCR0_DPD (1 << 9)
130 #define LCCR0_DIS (1 << 10)
131 #define LCCR0_QDM (1 << 11)
132 #define LCCR0_PDD (0xff << 12)
133 #define LCCR0_BSM0 (1 << 20)
134 #define LCCR0_OUM (1 << 21)
135 #define LCCR0_LCDT (1 << 22)
136 #define LCCR0_RDSTM (1 << 23)
137 #define LCCR0_CMDIM (1 << 24)
138 #define LCCR0_OUC (1 << 25)
139 #define LCCR0_LDDALT (1 << 26)
140 #define LCCR1_PPL(x) ((x) & 0x3ff)
141 #define LCCR2_LPP(x) ((x) & 0x3ff)
142 #define LCCR3_API (15 << 16)
143 #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
144 #define LCCR3_PDFOR(x) (((x) >> 30) & 3)
145 #define LCCR4_K1(x) (((x) >> 0) & 7)
146 #define LCCR4_K2(x) (((x) >> 3) & 7)
147 #define LCCR4_K3(x) (((x) >> 6) & 7)
148 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
149 #define LCCR5_SOFM(ch) (1 << (ch - 1))
150 #define LCCR5_EOFM(ch) (1 << (ch + 7))
151 #define LCCR5_BSM(ch) (1 << (ch + 15))
152 #define LCCR5_IUM(ch) (1 << (ch + 23))
153 #define OVLC1_EN (1 << 31)
154 #define CCR_CEN (1 << 31)
155 #define FBR_BRA (1 << 0)
156 #define FBR_BINT (1 << 1)
157 #define FBR_SRCADDR (0xfffffff << 4)
158 #define LCSR0_LDD (1 << 0)
159 #define LCSR0_SOF0 (1 << 1)
160 #define LCSR0_BER (1 << 2)
161 #define LCSR0_ABC (1 << 3)
162 #define LCSR0_IU0 (1 << 4)
163 #define LCSR0_IU1 (1 << 5)
164 #define LCSR0_OU (1 << 6)
165 #define LCSR0_QD (1 << 7)
166 #define LCSR0_EOF0 (1 << 8)
167 #define LCSR0_BS0 (1 << 9)
168 #define LCSR0_SINT (1 << 10)
169 #define LCSR0_RDST (1 << 11)
170 #define LCSR0_CMDINT (1 << 12)
171 #define LCSR0_BERCH(x) (((x) & 7) << 28)
172 #define LCSR1_SOF(ch) (1 << (ch - 1))
173 #define LCSR1_EOF(ch) (1 << (ch + 7))
174 #define LCSR1_BS(ch) (1 << (ch + 15))
175 #define LCSR1_IU(ch) (1 << (ch + 23))
176 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
177 #define LDCMD_EOFINT (1 << 21)
178 #define LDCMD_SOFINT (1 << 22)
179 #define LDCMD_PAL (1 << 26)
180
181 /* Route internal interrupt lines to the global IC */
182 static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
183 {
184 int level = 0;
185 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
186 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
187 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
188 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
189 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
190 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
191 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
192 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
193 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
194 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
195 level |= (s->status[1] & ~s->control[5]);
196
197 qemu_set_irq(s->irq, !!level);
198 s->irqlevel = level;
199 }
200
201 /* Set Branch Status interrupt high and poke associated registers */
202 static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
203 {
204 int unmasked;
205 if (ch == 0) {
206 s->status[0] |= LCSR0_BS0;
207 unmasked = !(s->control[0] & LCCR0_BSM0);
208 } else {
209 s->status[1] |= LCSR1_BS(ch);
210 unmasked = !(s->control[5] & LCCR5_BSM(ch));
211 }
212
213 if (unmasked) {
214 if (s->irqlevel)
215 s->status[0] |= LCSR0_SINT;
216 else
217 s->liidr = s->dma_ch[ch].id;
218 }
219 }
220
221 /* Set Start Of Frame Status interrupt high and poke associated registers */
222 static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
223 {
224 int unmasked;
225 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
226 return;
227
228 if (ch == 0) {
229 s->status[0] |= LCSR0_SOF0;
230 unmasked = !(s->control[0] & LCCR0_SOFM0);
231 } else {
232 s->status[1] |= LCSR1_SOF(ch);
233 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
234 }
235
236 if (unmasked) {
237 if (s->irqlevel)
238 s->status[0] |= LCSR0_SINT;
239 else
240 s->liidr = s->dma_ch[ch].id;
241 }
242 }
243
244 /* Set End Of Frame Status interrupt high and poke associated registers */
245 static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
246 {
247 int unmasked;
248 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
249 return;
250
251 if (ch == 0) {
252 s->status[0] |= LCSR0_EOF0;
253 unmasked = !(s->control[0] & LCCR0_EOFM0);
254 } else {
255 s->status[1] |= LCSR1_EOF(ch);
256 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
257 }
258
259 if (unmasked) {
260 if (s->irqlevel)
261 s->status[0] |= LCSR0_SINT;
262 else
263 s->liidr = s->dma_ch[ch].id;
264 }
265 }
266
267 /* Set Bus Error Status interrupt high and poke associated registers */
268 static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
269 {
270 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
271 if (s->irqlevel)
272 s->status[0] |= LCSR0_SINT;
273 else
274 s->liidr = s->dma_ch[ch].id;
275 }
276
277 /* Set Read Status interrupt high and poke associated registers */
278 static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
279 {
280 s->status[0] |= LCSR0_RDST;
281 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
282 s->status[0] |= LCSR0_SINT;
283 }
284
285 /* Load new Frame Descriptors from DMA */
286 static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
287 {
288 struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
289 target_phys_addr_t descptr;
290 int i;
291
292 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
293 desc[i] = 0;
294 s->dma_ch[i].source = 0;
295
296 if (!s->dma_ch[i].up)
297 continue;
298
299 if (s->dma_ch[i].branch & FBR_BRA) {
300 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
301 if (s->dma_ch[i].branch & FBR_BINT)
302 pxa2xx_dma_bs_set(s, i);
303 s->dma_ch[i].branch &= ~FBR_BRA;
304 } else
305 descptr = s->dma_ch[i].descriptor;
306
307 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
308 sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
309 continue;
310
311 descptr -= PXA2XX_SDRAM_BASE;
312 desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
313 s->dma_ch[i].descriptor = desc[i]->fdaddr;
314 s->dma_ch[i].source = desc[i]->fsaddr;
315 s->dma_ch[i].id = desc[i]->fidr;
316 s->dma_ch[i].command = desc[i]->ldcmd;
317 }
318 }
319
320 static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
321 {
322 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
323 int ch;
324
325 switch (offset) {
326 case LCCR0:
327 return s->control[0];
328 case LCCR1:
329 return s->control[1];
330 case LCCR2:
331 return s->control[2];
332 case LCCR3:
333 return s->control[3];
334 case LCCR4:
335 return s->control[4];
336 case LCCR5:
337 return s->control[5];
338
339 case OVL1C1:
340 return s->ovl1c[0];
341 case OVL1C2:
342 return s->ovl1c[1];
343 case OVL2C1:
344 return s->ovl2c[0];
345 case OVL2C2:
346 return s->ovl2c[1];
347
348 case CCR:
349 return s->ccr;
350
351 case CMDCR:
352 return s->cmdcr;
353
354 case TRGBR:
355 return s->trgbr;
356 case TCR:
357 return s->tcr;
358
359 case 0x200 ... 0x1000: /* DMA per-channel registers */
360 ch = (offset - 0x200) >> 4;
361 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
362 goto fail;
363
364 switch (offset & 0xf) {
365 case DMA_FDADR:
366 return s->dma_ch[ch].descriptor;
367 case DMA_FSADR:
368 return s->dma_ch[ch].source;
369 case DMA_FIDR:
370 return s->dma_ch[ch].id;
371 case DMA_LDCMD:
372 return s->dma_ch[ch].command;
373 default:
374 goto fail;
375 }
376
377 case FBR0:
378 return s->dma_ch[0].branch;
379 case FBR1:
380 return s->dma_ch[1].branch;
381 case FBR2:
382 return s->dma_ch[2].branch;
383 case FBR3:
384 return s->dma_ch[3].branch;
385 case FBR4:
386 return s->dma_ch[4].branch;
387 case FBR5:
388 return s->dma_ch[5].branch;
389 case FBR6:
390 return s->dma_ch[6].branch;
391
392 case BSCNTR:
393 return s->bscntr;
394
395 case PRSR:
396 return 0;
397
398 case LCSR0:
399 return s->status[0];
400 case LCSR1:
401 return s->status[1];
402 case LIIDR:
403 return s->liidr;
404
405 default:
406 fail:
407 cpu_abort(cpu_single_env,
408 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
409 }
410
411 return 0;
412 }
413
414 static void pxa2xx_lcdc_write(void *opaque,
415 target_phys_addr_t offset, uint32_t value)
416 {
417 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
418 int ch;
419
420 switch (offset) {
421 case LCCR0:
422 /* ACK Quick Disable done */
423 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
424 s->status[0] |= LCSR0_QD;
425
426 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
427 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
428
429 if ((s->control[3] & LCCR3_API) &&
430 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
431 s->status[0] |= LCSR0_ABC;
432
433 s->control[0] = value & 0x07ffffff;
434 pxa2xx_lcdc_int_update(s);
435
436 s->dma_ch[0].up = !!(value & LCCR0_ENB);
437 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
438 break;
439
440 case LCCR1:
441 s->control[1] = value;
442 break;
443
444 case LCCR2:
445 s->control[2] = value;
446 break;
447
448 case LCCR3:
449 s->control[3] = value & 0xefffffff;
450 s->bpp = LCCR3_BPP(value);
451 break;
452
453 case LCCR4:
454 s->control[4] = value & 0x83ff81ff;
455 break;
456
457 case LCCR5:
458 s->control[5] = value & 0x3f3f3f3f;
459 break;
460
461 case OVL1C1:
462 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
463 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
464
465 s->ovl1c[0] = value & 0x80ffffff;
466 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
467 break;
468
469 case OVL1C2:
470 s->ovl1c[1] = value & 0x000fffff;
471 break;
472
473 case OVL2C1:
474 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
475 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
476
477 s->ovl2c[0] = value & 0x80ffffff;
478 s->dma_ch[2].up = !!(value & OVLC1_EN);
479 s->dma_ch[3].up = !!(value & OVLC1_EN);
480 s->dma_ch[4].up = !!(value & OVLC1_EN);
481 break;
482
483 case OVL2C2:
484 s->ovl2c[1] = value & 0x007fffff;
485 break;
486
487 case CCR:
488 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
489 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
490
491 s->ccr = value & 0x81ffffe7;
492 s->dma_ch[5].up = !!(value & CCR_CEN);
493 break;
494
495 case CMDCR:
496 s->cmdcr = value & 0xff;
497 break;
498
499 case TRGBR:
500 s->trgbr = value & 0x00ffffff;
501 break;
502
503 case TCR:
504 s->tcr = value & 0x7fff;
505 break;
506
507 case 0x200 ... 0x1000: /* DMA per-channel registers */
508 ch = (offset - 0x200) >> 4;
509 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
510 goto fail;
511
512 switch (offset & 0xf) {
513 case DMA_FDADR:
514 s->dma_ch[ch].descriptor = value & 0xfffffff0;
515 break;
516
517 default:
518 goto fail;
519 }
520 break;
521
522 case FBR0:
523 s->dma_ch[0].branch = value & 0xfffffff3;
524 break;
525 case FBR1:
526 s->dma_ch[1].branch = value & 0xfffffff3;
527 break;
528 case FBR2:
529 s->dma_ch[2].branch = value & 0xfffffff3;
530 break;
531 case FBR3:
532 s->dma_ch[3].branch = value & 0xfffffff3;
533 break;
534 case FBR4:
535 s->dma_ch[4].branch = value & 0xfffffff3;
536 break;
537 case FBR5:
538 s->dma_ch[5].branch = value & 0xfffffff3;
539 break;
540 case FBR6:
541 s->dma_ch[6].branch = value & 0xfffffff3;
542 break;
543
544 case BSCNTR:
545 s->bscntr = value & 0xf;
546 break;
547
548 case PRSR:
549 break;
550
551 case LCSR0:
552 s->status[0] &= ~(value & 0xfff);
553 if (value & LCSR0_BER)
554 s->status[0] &= ~LCSR0_BERCH(7);
555 break;
556
557 case LCSR1:
558 s->status[1] &= ~(value & 0x3e3f3f);
559 break;
560
561 default:
562 fail:
563 cpu_abort(cpu_single_env,
564 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
565 }
566 }
567
568 static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
569 pxa2xx_lcdc_read,
570 pxa2xx_lcdc_read,
571 pxa2xx_lcdc_read
572 };
573
574 static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
575 pxa2xx_lcdc_write,
576 pxa2xx_lcdc_write,
577 pxa2xx_lcdc_write
578 };
579
580 /* Load new palette for a given DMA channel, convert to internal format */
581 static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
582 {
583 int i, n, format, r, g, b, alpha;
584 uint32_t *dest, *src;
585 s->pal_for = LCCR4_PALFOR(s->control[4]);
586 format = s->pal_for;
587
588 switch (bpp) {
589 case pxa_lcdc_2bpp:
590 n = 4;
591 break;
592 case pxa_lcdc_4bpp:
593 n = 16;
594 break;
595 case pxa_lcdc_8bpp:
596 n = 256;
597 break;
598 default:
599 format = 0;
600 return;
601 }
602
603 src = (uint32_t *) s->dma_ch[ch].pbuffer;
604 dest = (uint32_t *) s->dma_ch[ch].palette;
605 alpha = r = g = b = 0;
606
607 for (i = 0; i < n; i ++) {
608 switch (format) {
609 case 0: /* 16 bpp, no transparency */
610 alpha = 0;
611 if (s->control[0] & LCCR0_CMS)
612 r = g = b = *src & 0xff;
613 else {
614 r = (*src & 0xf800) >> 8;
615 g = (*src & 0x07e0) >> 3;
616 b = (*src & 0x001f) << 3;
617 }
618 break;
619 case 1: /* 16 bpp plus transparency */
620 alpha = *src & (1 << 24);
621 if (s->control[0] & LCCR0_CMS)
622 r = g = b = *src & 0xff;
623 else {
624 r = (*src & 0xf800) >> 8;
625 g = (*src & 0x07e0) >> 3;
626 b = (*src & 0x001f) << 3;
627 }
628 break;
629 case 2: /* 18 bpp plus transparency */
630 alpha = *src & (1 << 24);
631 if (s->control[0] & LCCR0_CMS)
632 r = g = b = *src & 0xff;
633 else {
634 r = (*src & 0xf80000) >> 16;
635 g = (*src & 0x00fc00) >> 8;
636 b = (*src & 0x0000f8);
637 }
638 break;
639 case 3: /* 24 bpp plus transparency */
640 alpha = *src & (1 << 24);
641 if (s->control[0] & LCCR0_CMS)
642 r = g = b = *src & 0xff;
643 else {
644 r = (*src & 0xff0000) >> 16;
645 g = (*src & 0x00ff00) >> 8;
646 b = (*src & 0x0000ff);
647 }
648 break;
649 }
650 switch (ds_get_bits_per_pixel(s->ds)) {
651 case 8:
652 *dest = rgb_to_pixel8(r, g, b) | alpha;
653 break;
654 case 15:
655 *dest = rgb_to_pixel15(r, g, b) | alpha;
656 break;
657 case 16:
658 *dest = rgb_to_pixel16(r, g, b) | alpha;
659 break;
660 case 24:
661 *dest = rgb_to_pixel24(r, g, b) | alpha;
662 break;
663 case 32:
664 *dest = rgb_to_pixel32(r, g, b) | alpha;
665 break;
666 }
667 src ++;
668 dest ++;
669 }
670 }
671
672 static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
673 uint8_t *fb, int *miny, int *maxy)
674 {
675 int y, src_width, dest_width, dirty[2];
676 uint8_t *src, *dest;
677 ram_addr_t x, addr, new_addr, start, end;
678 drawfn fn = 0;
679 if (s->dest_width)
680 fn = s->line_fn[s->transp][s->bpp];
681 if (!fn)
682 return;
683
684 src = fb;
685 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
686 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
687 src_width *= 3;
688 else if (s->bpp > pxa_lcdc_16bpp)
689 src_width *= 4;
690 else if (s->bpp > pxa_lcdc_8bpp)
691 src_width *= 2;
692
693 dest = ds_get_data(s->ds);
694 dest_width = s->xres * s->dest_width;
695
696 addr = (ram_addr_t) (fb - phys_ram_base);
697 start = addr + s->yres * src_width;
698 end = addr;
699 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
700 for (y = 0; y < s->yres; y ++) {
701 new_addr = addr + src_width;
702 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
703 x += TARGET_PAGE_SIZE) {
704 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
705 dirty[0] |= dirty[1];
706 }
707 if (dirty[0] || s->invalidated) {
708 fn((uint32_t *) s->dma_ch[0].palette,
709 dest, src, s->xres, s->dest_width);
710 if (addr < start)
711 start = addr;
712 end = new_addr;
713 if (y < *miny)
714 *miny = y;
715 if (y >= *maxy)
716 *maxy = y + 1;
717 }
718 addr = new_addr;
719 dirty[0] = dirty[1];
720 src += src_width;
721 dest += dest_width;
722 }
723
724 if (end > start)
725 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
726 }
727
728 static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
729 uint8_t *fb, int *miny, int *maxy)
730 {
731 int y, src_width, dest_width, dirty[2];
732 uint8_t *src, *dest;
733 ram_addr_t x, addr, new_addr, start, end;
734 drawfn fn = 0;
735 if (s->dest_width)
736 fn = s->line_fn[s->transp][s->bpp];
737 if (!fn)
738 return;
739
740 src = fb;
741 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
742 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
743 src_width *= 3;
744 else if (s->bpp > pxa_lcdc_16bpp)
745 src_width *= 4;
746 else if (s->bpp > pxa_lcdc_8bpp)
747 src_width *= 2;
748
749 dest_width = s->yres * s->dest_width;
750 dest = ds_get_data(s->ds) + dest_width * (s->xres - 1);
751
752 addr = (ram_addr_t) (fb - phys_ram_base);
753 start = addr + s->yres * src_width;
754 end = addr;
755 x = addr + TARGET_PAGE_SIZE;
756 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
757 for (y = 0; y < s->yres; y ++) {
758 new_addr = addr + src_width;
759 for (; x < new_addr; x += TARGET_PAGE_SIZE) {
760 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
761 dirty[0] |= dirty[1];
762 }
763 if (dirty[0] || s->invalidated) {
764 fn((uint32_t *) s->dma_ch[0].palette,
765 dest, src, s->xres, -dest_width);
766 if (addr < start)
767 start = addr;
768 end = new_addr;
769 if (y < *miny)
770 *miny = y;
771 if (y >= *maxy)
772 *maxy = y + 1;
773 }
774 addr = new_addr;
775 dirty[0] = dirty[1];
776 src += src_width;
777 dest += s->dest_width;
778 }
779
780 if (end > start)
781 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
782 }
783
784 static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
785 {
786 int width, height;
787 if (!(s->control[0] & LCCR0_ENB))
788 return;
789
790 width = LCCR1_PPL(s->control[1]) + 1;
791 height = LCCR2_LPP(s->control[2]) + 1;
792
793 if (width != s->xres || height != s->yres) {
794 if (s->orientation)
795 qemu_console_resize(s->console, height, width);
796 else
797 qemu_console_resize(s->console, width, height);
798 s->invalidated = 1;
799 s->xres = width;
800 s->yres = height;
801 }
802 }
803
804 static void pxa2xx_update_display(void *opaque)
805 {
806 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
807 uint8_t *fb;
808 target_phys_addr_t fbptr;
809 int miny, maxy;
810 int ch;
811 if (!(s->control[0] & LCCR0_ENB))
812 return;
813
814 pxa2xx_descriptor_load(s);
815
816 pxa2xx_lcdc_resize(s);
817 miny = s->yres;
818 maxy = 0;
819 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
820 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
821 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
822 if (s->dma_ch[ch].up) {
823 if (!s->dma_ch[ch].source) {
824 pxa2xx_dma_ber_set(s, ch);
825 continue;
826 }
827 fbptr = s->dma_ch[ch].source;
828 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
829 fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) {
830 pxa2xx_dma_ber_set(s, ch);
831 continue;
832 }
833 fbptr -= PXA2XX_SDRAM_BASE;
834 fb = phys_ram_base + fbptr;
835
836 if (s->dma_ch[ch].command & LDCMD_PAL) {
837 memcpy(s->dma_ch[ch].pbuffer, fb,
838 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
839 sizeof(s->dma_ch[ch].pbuffer)));
840 pxa2xx_palette_parse(s, ch, s->bpp);
841 } else {
842 /* Do we need to reparse palette */
843 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
844 pxa2xx_palette_parse(s, ch, s->bpp);
845
846 /* ACK frame start */
847 pxa2xx_dma_sof_set(s, ch);
848
849 s->dma_ch[ch].redraw(s, fb, &miny, &maxy);
850 s->invalidated = 0;
851
852 /* ACK frame completed */
853 pxa2xx_dma_eof_set(s, ch);
854 }
855 }
856
857 if (s->control[0] & LCCR0_DIS) {
858 /* ACK last frame completed */
859 s->control[0] &= ~LCCR0_ENB;
860 s->status[0] |= LCSR0_LDD;
861 }
862
863 if (s->orientation)
864 dpy_update(s->ds, miny, 0, maxy, s->xres);
865 else
866 dpy_update(s->ds, 0, miny, s->xres, maxy);
867 pxa2xx_lcdc_int_update(s);
868
869 qemu_irq_raise(s->vsync_cb);
870 }
871
872 static void pxa2xx_invalidate_display(void *opaque)
873 {
874 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
875 s->invalidated = 1;
876 }
877
878 static void pxa2xx_screen_dump(void *opaque, const char *filename)
879 {
880 /* TODO */
881 }
882
883 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
884 {
885 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
886
887 if (angle) {
888 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
889 } else {
890 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
891 }
892
893 s->orientation = angle;
894 s->xres = s->yres = -1;
895 pxa2xx_lcdc_resize(s);
896 }
897
898 static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
899 {
900 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
901 int i;
902
903 qemu_put_be32(f, s->irqlevel);
904 qemu_put_be32(f, s->transp);
905
906 for (i = 0; i < 6; i ++)
907 qemu_put_be32s(f, &s->control[i]);
908 for (i = 0; i < 2; i ++)
909 qemu_put_be32s(f, &s->status[i]);
910 for (i = 0; i < 2; i ++)
911 qemu_put_be32s(f, &s->ovl1c[i]);
912 for (i = 0; i < 2; i ++)
913 qemu_put_be32s(f, &s->ovl2c[i]);
914 qemu_put_be32s(f, &s->ccr);
915 qemu_put_be32s(f, &s->cmdcr);
916 qemu_put_be32s(f, &s->trgbr);
917 qemu_put_be32s(f, &s->tcr);
918 qemu_put_be32s(f, &s->liidr);
919 qemu_put_8s(f, &s->bscntr);
920
921 for (i = 0; i < 7; i ++) {
922 qemu_put_betl(f, s->dma_ch[i].branch);
923 qemu_put_byte(f, s->dma_ch[i].up);
924 qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
925
926 qemu_put_betl(f, s->dma_ch[i].descriptor);
927 qemu_put_betl(f, s->dma_ch[i].source);
928 qemu_put_be32s(f, &s->dma_ch[i].id);
929 qemu_put_be32s(f, &s->dma_ch[i].command);
930 }
931 }
932
933 static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
934 {
935 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
936 int i;
937
938 s->irqlevel = qemu_get_be32(f);
939 s->transp = qemu_get_be32(f);
940
941 for (i = 0; i < 6; i ++)
942 qemu_get_be32s(f, &s->control[i]);
943 for (i = 0; i < 2; i ++)
944 qemu_get_be32s(f, &s->status[i]);
945 for (i = 0; i < 2; i ++)
946 qemu_get_be32s(f, &s->ovl1c[i]);
947 for (i = 0; i < 2; i ++)
948 qemu_get_be32s(f, &s->ovl2c[i]);
949 qemu_get_be32s(f, &s->ccr);
950 qemu_get_be32s(f, &s->cmdcr);
951 qemu_get_be32s(f, &s->trgbr);
952 qemu_get_be32s(f, &s->tcr);
953 qemu_get_be32s(f, &s->liidr);
954 qemu_get_8s(f, &s->bscntr);
955
956 for (i = 0; i < 7; i ++) {
957 s->dma_ch[i].branch = qemu_get_betl(f);
958 s->dma_ch[i].up = qemu_get_byte(f);
959 qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
960
961 s->dma_ch[i].descriptor = qemu_get_betl(f);
962 s->dma_ch[i].source = qemu_get_betl(f);
963 qemu_get_be32s(f, &s->dma_ch[i].id);
964 qemu_get_be32s(f, &s->dma_ch[i].command);
965 }
966
967 s->bpp = LCCR3_BPP(s->control[3]);
968 s->xres = s->yres = s->pal_for = -1;
969
970 return 0;
971 }
972
973 #define BITS 8
974 #include "pxa2xx_template.h"
975 #define BITS 15
976 #include "pxa2xx_template.h"
977 #define BITS 16
978 #include "pxa2xx_template.h"
979 #define BITS 24
980 #include "pxa2xx_template.h"
981 #define BITS 32
982 #include "pxa2xx_template.h"
983
984 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
985 DisplayState *ds)
986 {
987 int iomemtype;
988 struct pxa2xx_lcdc_s *s;
989
990 s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
991 s->invalidated = 1;
992 s->irq = irq;
993 s->ds = ds;
994
995 pxa2xx_lcdc_orientation(s, graphic_rotate);
996
997 iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
998 pxa2xx_lcdc_writefn, s);
999 cpu_register_physical_memory(base, 0x00100000, iomemtype);
1000
1001 s->console = graphic_console_init(ds, pxa2xx_update_display,
1002 pxa2xx_invalidate_display,
1003 pxa2xx_screen_dump, NULL, s);
1004
1005 switch (ds_get_bits_per_pixel(s->ds)) {
1006 case 0:
1007 s->dest_width = 0;
1008 break;
1009 case 8:
1010 s->line_fn[0] = pxa2xx_draw_fn_8;
1011 s->line_fn[1] = pxa2xx_draw_fn_8t;
1012 s->dest_width = 1;
1013 break;
1014 case 15:
1015 s->line_fn[0] = pxa2xx_draw_fn_15;
1016 s->line_fn[1] = pxa2xx_draw_fn_15t;
1017 s->dest_width = 2;
1018 break;
1019 case 16:
1020 s->line_fn[0] = pxa2xx_draw_fn_16;
1021 s->line_fn[1] = pxa2xx_draw_fn_16t;
1022 s->dest_width = 2;
1023 break;
1024 case 24:
1025 s->line_fn[0] = pxa2xx_draw_fn_24;
1026 s->line_fn[1] = pxa2xx_draw_fn_24t;
1027 s->dest_width = 3;
1028 break;
1029 case 32:
1030 s->line_fn[0] = pxa2xx_draw_fn_32;
1031 s->line_fn[1] = pxa2xx_draw_fn_32t;
1032 s->dest_width = 4;
1033 break;
1034 default:
1035 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1036 exit(1);
1037 }
1038
1039 register_savevm("pxa2xx_lcdc", 0, 0,
1040 pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
1041
1042 return s;
1043 }
1044
1045 void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler)
1046 {
1047 s->vsync_cb = handler;
1048 }
jz4740 based target emulation