target-mips: optimize gen_muldiv()
[qemu/qemu-JZ.git] / target-ppc / exec.h
blob2b1cfe2586375b9fb4cfa24f4be2c5082890d076
1 /*
2 * PowerPC emulation definitions for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #if !defined (__PPC_H__)
21 #define __PPC_H__
23 #include "config.h"
25 #include "dyngen-exec.h"
27 #include "cpu.h"
28 #include "exec-all.h"
30 /* For normal operations, precise emulation should not be needed */
31 //#define USE_PRECISE_EMULATION 1
32 #define USE_PRECISE_EMULATION 0
34 register struct CPUPPCState *env asm(AREG0);
35 #if TARGET_LONG_BITS > HOST_LONG_BITS
36 /* no registers can be used */
37 #define T0 (env->t0)
38 #define T1 (env->t1)
39 #define T2 (env->t2)
40 #define TDX "%016" PRIx64
41 #else
42 register target_ulong T0 asm(AREG1);
43 register target_ulong T1 asm(AREG2);
44 register target_ulong T2 asm(AREG3);
45 #define TDX "%016lx"
46 #endif
47 /* We may, sometime, need 64 bits registers on 32 bits targets */
48 #if !defined(TARGET_PPC64)
49 #define T0_64 (env->t0_64)
50 #define T1_64 (env->t1_64)
51 #define T2_64 (env->t2_64)
52 #else
53 #define T0_64 T0
54 #define T1_64 T1
55 #define T2_64 T2
56 #endif
57 /* Provision for Altivec */
58 #define AVR0 (env->avr0)
59 #define AVR1 (env->avr1)
60 #define AVR2 (env->avr2)
62 #define FT0 (env->ft0)
63 #define FT1 (env->ft1)
64 #define FT2 (env->ft2)
66 #if defined (DEBUG_OP)
67 # define RETURN() __asm__ __volatile__("nop" : : : "memory");
68 #else
69 # define RETURN() __asm__ __volatile__("" : : : "memory");
70 #endif
72 static always_inline target_ulong rotl8 (target_ulong i, int n)
74 return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n)));
77 static always_inline target_ulong rotl16 (target_ulong i, int n)
79 return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n)));
82 static always_inline target_ulong rotl32 (target_ulong i, int n)
84 return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n)));
87 #if defined(TARGET_PPC64)
88 static always_inline target_ulong rotl64 (target_ulong i, int n)
90 return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n)));
92 #endif
94 #if !defined(CONFIG_USER_ONLY)
95 #include "softmmu_exec.h"
96 #endif /* !defined(CONFIG_USER_ONLY) */
98 void do_raise_exception_err (uint32_t exception, int error_code);
99 void do_raise_exception (uint32_t exception);
101 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
102 int rw, int access_type);
104 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
105 target_ulong pte0, target_ulong pte1);
107 static always_inline void env_to_regs (void)
111 static always_inline void regs_to_env (void)
115 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
116 int mmu_idx, int is_softmmu);
118 static always_inline int cpu_halted (CPUState *env)
120 if (!env->halted)
121 return 0;
122 if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
123 env->halted = 0;
124 return 0;
126 return EXCP_HALTED;
129 #endif /* !defined (__PPC_H__) */